Sanyo LV4124W Specifications

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Monolithic Linear IC

82198RM (OT) No.6000-1/21

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

LV4124W

Ordering number : EN6000

Overview

The LV4124W is a LCD panel driver for use in lowtemperature polysilicon TFT LCDs that integrates an RGB decoder, a driver, and a timing controller in a single chip. This IC is manufactured in Bi-CMOS process and supports the ALP202 2.0-inch color LCD panel.

Functions

• Analog block: RGB decoder/driver

• Digital block: Timing generator

Features

• Supports NTSC/PAL standard

• Supports composite, Y/C, and Y/color difference inputs

• Built-in BPF, TRAP, and DL circuits

• Sharpness function

• Dual point γ correction circuit

• Pre-charge circuit

• R and B outputs delay time correction circuit (Supports up and down and right and left inversions)

• Polarity reverse circuit

• External RGB input supported

• Line inversion supported

• Supports AC drive for the LCD panel during no signal

• Serial bus for mode setting and electric VR

Package

• SQFP-64 plastic package

Package Dimensions

unit: mm

SQFP-64

[LV4124W]

SANYO: SQFP64

Single-chip LCD panel driver IC

(Supports the ALP202 LCD panel)

No.6000-2/21

LV4124W

Electrical Characteristics at VCC1 = 4.5 V, VCC2 = VCCPCD = 12.0 V, GND1 = GND2 = GNDPCD = 0 V, VDD=

3.0 V VSS1 = VSS2 = 0 V, and Ta = 25°C

DC Characteristics

Parameter Symbol Conditions

Ratings

Unit

min typ max

[Current Characteristics]

ICC11

Input SIG4 to (A) and SIG2 (0 dB) to (B).

Composite input 22 29 35 mA

Current drain: V

ICC12

Measure the ICC1 current.

Y/C input 21 28 34 mA

4.5V system ICC13

Input SIG4 to (A), (D), and (E). Y/color difference

18 23 28 mA

Measure the ICC1 current. input

Current drain: V

ICC2

Input SIG4 to (A) and SIG2 (0 dB) to (B).

4.5 6.5 8.5 mA

12V system Measure the ICC2 current. Current drain: V

IDD

Input SIG4 to (A) and SIG2 (0 dB) to (B).

4.5 6.0 7.5 mA

MOS circuit blocks Measure the IDD current. [Digital Block Input and Output Characteristics]

Input current

II1 Input pins with built-in pull-up resistors *

VIN= V

–24 –60 –145 µA

II2 Input pins with built-in pull-down resistors *

VIN= V

24 60 145 µA

High-level output voltage V

1 Ioh = –1 mA *

VDD– 0.2 V

Low-level output voltage V

1 Iol = 1 mA *

0.3 V

CKO pin high-level output voltage V

2 Ioh = –3 mA 0.5V

CKO pin low-level output voltage V

2 Iol = 3 mA 0.5V

RPD pin high-level output voltage V

3 Ioh = –0.5 mA VDD– 1.2 V

RPD pin low-level output voltage V

3 Ioh = 0.7 mA 1.0 V

RPD pin output off leakage current IOFF In the high-impedance state, V

OUT

= VSSor VDD. –40 40 µA

Input voltage threshold (high) VTDH Input pins *

, *

0.7V

Input voltage threshold (low) VTDL Input pins *

, *

0.3V

Notes: 1. Input pins with built-in pull-up resistors: VDIN, CSH, CSV, SCLK, DATA, and LOAD

2. Input pins with built-in pull-down resistors: PANEL and TEST

3. Output pins other than CKO and RPD: XSTH, STH, CKH2, CKH1, PCG2, PCG1, HD, XSTV, STV, CKV2, CKV1, XENB, ENB, and VD.

Specifications

Maximum Ratings at Ta = 25°C

Note *: When mounted on a printed circuit board (30 × 30 mm, t = 1.6 mm, material: glass/epoxy)

Operating Conditions at Ta = 25°C

Parameter Symbol Conditions Rating Units

1 max Analog 4.5V system 6 V

Maximum supply voltage V

2 max Analog 12V system 14 V

max Digital system 4.5 V Allowable power dissipation Pd max With Ta ≤ 75°C* 350 mV Operating temperature Topr –15 to +75 °C Storage temperature Tstg –40 to +125 °C

Input pin voltage

VINA Analog input pins –0.3 to V

1 V

VIND Digital input pins –0.3 to V

+0.3 V

Parameter Symbol Conditions Rating Units

1 Analog 4.5V system 4.5 V

Recommended supply voltage V

2 Analog 12V system 12.0 V

Digital system 3.0 V

1op Analog 4.5V system 4.25 to 5.25 V Operating supply voltage range V

2op Analog 12V system 11 to 13.5 V

op Digital system 2.7 to 3.6 V

No.6000-3/21

LV4124W

AC Characteristics (1) when the T41, T44, and T46 outputs are measured at the noninverted outputs.

Parameter Symbol Conditions

Ratings

Unit

min typ max

[Luminance Signal System]

Contrast characteristics (typ.) GCNTTP

Input SIG4 to (A) and measure the ratio of the T44 output

13 17 21 dB

amplitude (white - black) to the input amplitude.

Contrast characteristics (min.) GCNTMN

Input SIG4 to (A) and measure the ratio of the T44 output

–9 –5 –1 dB

amplitude (white - black) to the input amplitude.

Maximum video gain GV

Input SIG4 to (A) and measure the ratio of the T44 output

19 22 25 dB

amplitude (white - black) to the input amplitude.

[Luminance Signal Frequency Characteristics]

Y/C input FCYYC

Take the T44 output amplitude with SIG7 (0 dB, no burst,

5.0

100 kHz) input to (A) as 0 dB. Modify the input frequency

FCYCMN 2.5 MHz

Composite input

NTSC

and determine the frequency such that the output is down

FCYCMP 2.5

PAL

–3 dB.

GSHP1X Take the T44 output amplitude with SIG7 MAX 12 16 Image quality adjustment (100 kHz) input to (A) as 0 dB. Determine range 1 (Y/C input)

GSHP1N

the ratio of the output amplitude with a

MIN 0 2

2.5-MHz SIG7 input.

GSHP3X Take the T44 output amplitude with SIG7 MAX 6 10 Image quality adjustment (100 kHz) input to (A) as 0 dB. Determine the range 3 (composite input)

GSHP3N

ratio of the output amplitude with a 2.0-MHz

MIN –2 3

SIG7 input.

Input SIG2 (0 dB) to (A) and using a spectrum analyzer, measure the 3.58 and 4.43 MHz components in the input and

Chrominance signal leakage CRLEKY in T44. Let ∆CLK be that difference. Use that value to 30 mV

determine CRLEKY from the following formula:

CRLEKY

= 150 mV × 10

∆CLK/20

[Luminance Signal Input to Output Delay]

Y/C input TDYYC 250 350 450 ns

Input SIG5 (VL = 150 mV) to (A).Measure the delay time

TDYCMN

between a rising edge in the input and the corresponding

500 600 700 ns

Composite input

NTSC

rising edge in the T44 noninverted output.

PAL TDYCMP 500 600 700 ns

[Color Difference Signal System]

Input SIG5 (VL = 150 mV) to (A) and SIG1 (0 dB, 100 kHz,

GEXCMX

no burst) to (D). Let VC0 be the T41 output amplitude

+4 +6 dB

(100 kHz) when COL = 128. Let VC2 be the T41 output Color difference input color amplitude (100 kHz) when COL = 0. Let VC1 be the T41 adjustment output amplitude (100 kHz) when SIG1 is set to -10 dB and

GEXCMN

COL = 255. Then calculate the following formulas.

–15 –11 dB

GEXCMX = 20log (VC1/VC0) +10

GEXCMN = 20log (VC2/VC0)

Input SIG5 (VL = 150 mV) to (A) and SIG1 (0 dB, 100 kHz,

no burst) to (D) and (E). Color difference balance VEXCBL Let VB be the T41 output amplitude (100 kHz), and let VR 0.85 1 1.15 –

be the T46 output amplitude (100 kHz).

Calculate VEXCBL = VR/VB.

Continued on next page.

Parameter Symbol Conditions

Ratings

Unit

min typ max

[Chrominance Signal System]

NTSC –3 0 +3

ACC amplitude characteristics 1 ACC1

PAL –3 0 +3

VTSC –3 0 +3

ACC amplitude characteristics 2 ACC2

PAL –3 0 +3

NTSC ±500

APC pull-in range FAPC Hz

PAL ±500

No.6000-4/21

LV4124W

Continued from preceding page

Parameter Symbol Conditions

Ratings

Unit

min typ max

[Color Difference Signal System]

GEXRMX +2 +3 dB Color difference input balance adjustment R

GEXRMN –3 –4.5 dB

GEXBMX –3 –4.5 dB Color difference input balance adjustment B

GEXBMN +2 +3 dB

VEXGBN 0.21 0.24 0.27 –

G-Y matrix characteristics (NTSC)

VEXGRN 0.46 0.51 0.56 –

VEXGRP 0.17 0.19 0.21 –

G-Y matrix characteristics (PAL)

VEXGRP 0.46 0.51 0.56 –

Continued on next page.

Input SIG5 (VL = 150 mV) to (A) and SIG1 (–6 dB, 100 kHz, no burst) to (D) and (E). When TINT = 128, let VR0 be the T46 output amplitude (100 kHz) and let VB0 be the T41 output amplitude (100 kHz). When TINT = 255, let VR1 be the T46 output amplitude and let VB1 be the T41 output amplitude. When TINT = 0, let VR2 be the T46 output amplitude and let VB2 be the T41 output amplitude. Then calculate the following formulas. GEXRMX = 20log (VR1/VR0) GEXRMN = 20log (VR2/VR0) GEXBMX = 20log (VB1/VB0) GEXBMN = 20log (VB2/VB0)

Input SIG5 (VL = 150 mV) to (A) and SIG1 (0 dB, 100 kHz, no burst) to (D). Let VEXB be the T41 output amplitude (100 kHz) and VEXBG be the T44 output amplitude (100 kHz).Calculate VEXGB = VEXBG/VEXB.

Input SIG5 (VL = 150 mV) to (A) and SIG1 (0 dB, 100 kHz, no burst) to (E). Let VEXR be the T46 output amplitude (100 kHz) and VEXRG be the T44 output amplitude (100 kHz). Calculate VEXGR = VEXRG/VEXR.

Input SIG5 (VL = 150 mV) to (A) and SIG1 (0 dB, 100 kHz, no burst) to (D). Let VEXB be the T41 output amplitude (100 kHz) and VEXBG be the T44 output amplitude (100 kHz).Calculate VEXGB = VEXBG/VEXB.

AC Characteristics (2)

Input SIG5 (VL = 150 mV) to (A), and to (B), input SIG2 (0 dB, 3.58 MHz, burst/chrominance phase = 180°, and also 4.43 MHz, burst/chrominance phase = ±135°). Measure the T44 output amplitude. Modify the SIG2 burst frequency, until the killer is released. Measure the frequency f1 that appears in the T41 output. NTSC f1 = 3579545 Hz PAL f1 = 4433619 Hz

Input SIG5 (VL = 150 mV) to (A), and to (B), input SIG2 (0, +6, and –20 dB, 3.58 MHz, burst/chrominance phase = 180°, and also

4.43 MHz, burst/chrominance phase = ±135°). Measure the T53 output amplitude, and let V0, V1, and V2 correspond to 0 dB, +6 dB, and –20 dB, respectively. ACC1 = 20log (V1/V0) ACC2 = 20log (V2/V0)

No.6000-5/21

LV4124W

Continued from preceding page

Parameter Symbol Conditions

Ratings

Unit

min typ max

[Chrominance Signal System]

Color adjustment characteristics (maximum)

GCOLMX +4 +6 dB

Color adjustment characteristics (minimum)

GCOLMN –20 –15 dB

Tint adjustment range (maximum)

TNTMX –30 –40 deg

Tint adjustment range (minimum)

TNTMN 30 40 deg

ACKN NTSC –36 30 dB

Killer operating input level

ACKP PAL –33 –27 dB

VRBN 0.53 0.63 0.73 –

Demodulator output amplitude ratio (NTSC)

VGBN 0.25 0.32 0.39 –

θ RBN 99 109 119 deg

Demodulator output phase difference (NTSC)

θ GBN 230 242 254 deg

VRBP 0.65 0.75 0.85 –

Demodulator output amplitude ratio (PAL)

VGBP 0.33 0.40 0.47 –

θ RBP 80 90 100 deg

Demodulator output phase difference (PAL)

θ GBP 232 244 256 deg

Input SIG5 (VL = 150 mV) to (A), and input SIG2 (0 dB, burst/chrominance phase = 180°) to (B). Let V0, V1, and V2 be the chrominance signal amplitude when COL = 128, COL = 255, and COL = 0, respectively. Calculate GCOLMX = 20log (V1/V0), and GCOLMN = 20log (V2/V0).

Input SIG5 (VL = 150 mV) to (A), and input SIG2 (0 dB, with a variable burst/chrominance phase) to (B). Let θ 0, θ 1, and θ2 be the phases when the T41 output amplitude is minimum when TINT = 128, TINT = 255, and TINT = 0, respectively. Calculate TNTMX = θ1 – θ0, and TNTMN = θ2 – θ0.

Input SIG5 (VL = 150 mV) to (A), and to (B), input SIG2 (with a variable level, burst/chrominance phase = 180°, and also burst/chrominance phase = ±135°). Measure the T41 output amplitude. Gradually lower the SIG3 level (amplitude) until the killer function operates and measure that level.

Input SIG5 (VL = 150 mV) to (A), and input SIG3 (0 dB) to (B). Modify the chrominance signal phase, let VB be the maximum amplitude of the T41 chrominance demodulated signal, let VG be the maximum amplitude of the T44 chrominance demodulated signal, and let VR be the maximum amplitude of the T46 chrominance demodulated signal Calculate VRBN = VR/VB and VGBN = VG/VB.

Input SIG5 (VL = 150 mV) to (A), and input SIG3 (0 dB) to (B). Modify the chrominance signal phase, let θ B be the phase at the maximum amplitude of the T41 chrominance demodulated signal, let θ G be the phase at the maximum amplitude of the T44 chrominance demodulated signal, and let θ R be the phase at the maximum amplitude of the T46 chrominance demodulated signal. Calculate θ RBN = θ R – θ B and θ GBN = θ G – θ B.

No.6000-6/21

LV4124W

Parameter Symbol Conditions

Ratings

Unit

min typ max

[RGB Signal and PCD Output Systems]

RGB signal and PCD output

Input SIG5 (VL = 0 mV) to (A), adjust the BRIGHT parameter

DC voltage

VOUT with the serial bus data so that T44 is 9 Vp-p, and measure 5.85 6.00 6.15 V

the DC voltages on T39, T41, T44, and T46.

RGB signal and PCD output

Determine the maximum value of the differences in the

DC voltage difference

∆VOUT measured values of VOUT in the previous item for T39, T41, 0 100 mV

T44, and T46.

VLIMMX 9.0 Vpp

RGB signal and PCD output Color difference input balance

VLIMMN 5.2 Vpp

BRTMX 9.0 Vpp

Brightness variation

BRTMN 4.0 Vpp

PCD variation

PCDMX 9.0 Vpp

PCDMN 3 Vpp

Sub-brightness variation SBBRT ±2.0 ±3.0 V

Input SIG4 to (A) and determine the level difference between

RGB inter-signal gain difference ∆GRGB the largest and the smallest of the noninverted output –0.5 0 0.5 dB

amplitudes (white - black) for T41, T44, and T46.

RGB inverted/noninverted gain

Input SIG4 to (A) and determine the difference between

difference

∆GINV the inverted output amplitude and the noninverted output –0.5 0 0.5 dB

amplitude (white - black) for T41, T44, and T46.

RGB inter-signal black level

Input SIG4 to (A) and determine the difference between the

potential difference

∆VBL highest and lowest black levels in the inverted and 300 mV

noninverted T41, T44, and T46 outputs.

Gγ1 23.0 26.0 29.0 dB

Gamma gain Gγ2 12.0 15.0 18.0 dB

Gγ3 18.0 21.0 25.0 dB

Vγ1MN 0 IRE

Gamma 1 adjustment range

Vγ1MX 70 IRE

Vγ2MN 100 IRE

Gamma 2 adjustment range

Vγ2MX 30 IRE

tPCDH

The transition time for a load of 8000 pF and an amplitude of

2.5 µs

PCD transition time 9 V p-p.

tPCDL

tPCDH: For rising edges. tPCDL: For falling edges.

2.5 µs

Input SIG3 to (A), and measure the maximum value (VLIMMX) and minimum value (VLIMMN) of the voltage range (black - black) over which the black limiter operates when V54 is varied for T39, T41, T44, and T46. Measure VLIMMX when V54 = 0 V, and measure VLIMMN when V54 = 4.5 V.

Input SIG5 (VL = 0 mV) to (A) and set BRT to 0. Measure the T41, T44, and T46 outputs (black - black).

Input SIG5 (VL = 0 mV) to (A) and measure the T39 output (black - black) when P-BRT is set to 255.

Input SIG5 (VL = 0 mV) to (A) and measure the T44 output (black - black) with respect to the T41 and T46 outputs (black - black) when R-BRT = B-BRT = 0, and when R-BRT = B-BRT = 255.

Input SIG8 to (A), adjust the T44 inverted output black level to be 1.5 V with BRT, and adjust the amplitude (black white) to be 3.5 V with CONT. Measure VG1, VG2, and VG3 and calculate the following formulas. Gγ1 = 20log (VG1/0.0357) Gγ2 = 20log (VG2/0.0357) Gγ3 = 20log (VG3/0.0357)

Input SIG8 to (A) and set the T44 output (black - black) to 9 V p-p with the BRIGHT adjustment. Read the gamma gain transition point at the input signal IRE level when γ1 = 0 and when γ1 = 255. V γ1MN is when γ1 = 0, and Vγ1MX is when γ1 = 255.

Input SIG8 to (A) and set the T44 output (black - black) to 9 V p-p with the BRIGHT adjustment. Read the gamma gain transition point at the input signal IRE level when γ2 = 0 and when γ2 = 255. V γ2MN is when γ2 = 0, and Vγ2MX is when γ2 = 255.

Input SIG5 (VL = 0 mV) to (A) and set BRT to 255. Measure the T41, T44, and T46 outputs (black - black).

Input SIG5 (VL = 0 mV) to (A) and measure the T39 output (black - black) when P-BRT is set to 0.

AC Characteristics (3)

No.6000-7/21

LV4124W

Parameter Symbol Conditions

Ratings

Unit

min typ max

[Filter Characteristics]

NTSC 1.50 MHz –15 –10 dB

Bandpass filter attenuation ATBPF

PAL 2.00 MHZ –15 –10 dB

NTSC 5.50 MHz –7 –2 dB PAL 6.80 MHz –8 –3 dB

ATRAPN NTSC –40 –30 dB

Trap attenuation

ATRAPP PAL –40 –30 dB

R-Y and B-Y low-pass filter DEMLPF 0.7 0.9 1.1 MHz

[Sync Separator Circuit and TG System]

Input synchronizing signal amplitude sensitivity

WSSEP 2.0 µs

Sync separator circuit input sensitivity

VSSEP 40 60 mV

TDSYL 430 630 830 ns Sync separator circuit output delay

TDSYH 4.7 5.0 5.3 µs

HPLLN NTSC ±500 Hz

Horizontal pull-in range

HPLLP PAL ±500 Hz

Continued on next page.

Input SIG5 (VL = 0 mV) to (A) and SIG1 (0 dB) to (B). Take the T53 chrominance amplitude when the center frequency (3.58 and 4.43 MHz) is input to be 0 dB, and measure the T53 output attenuation for the frequencies listed at the right.

Input SIG7 (0 dB, 3.58 and 4.43 MHz) to (A) and measure the T44 output with a spectrum analyzer. Taking the T44 amplitude in Y/C mode to be 0 dB, determine the attenuation in composite input mode.

Input SIG5 (VL = 150 mV) to (A) and SIG2 (0 dB, 3.58 MHz + 100 kHz) to (B). Take the T44 output 100 kHz component am plitude at this time to be 0 dB, and determine the frequency at which the output beat component is reduced by 3 dB when the SIG2 frequency is increased from 3.58 MHz.

Input SIG5 (VL = 0 mV, VS = 143 mV, variable WS) to (A) and verify synchronization with the T23 HD output. Determine the value of WS at the point synchronization with the T23 HD output is lost when the SIG5 WS is gradually made narrower starting at 4.7 µs.

Input SIG5 (VL = 0 mV, WS = 4.7 µs, variable VS) to (A) and verify synchronization with the T23 HD output. Determine the value of VS at the point synchronization with the T23 HD output is lost when the SIG5 VS is gradually reduced starting at 143 mV.

Input SIG5 (VL = 0 mV, WS = 4.7 µs, VS = 143 mV) to (A) and measure the delay time with respect to the T12 RPD output. Here, TDSYL is the delay from the fall of the input HSYNC signal to the fall of the T12 RPD output, and TDSYH is the delay from the rise of the input HSYNC signal to the rise of the T12 RPD output.

Input SIG5 (VL = 0 mV, WS = 4.7 µs, VS = 143 mV, variable horizontal frequency) to (A) and verify synchronization withthe T23 HD output. Determine the frequency fH at which synchronization is achieved when the SIG5 horizontal frequency is varied starting from the state where I/O synchronization is lost. Calculate HPLLN = fH – 15734 and HPLLP = fH – 15625.

AC Characteristics (4)

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