SANYO LC875164A, LC875148A, LC875132A Datasheet

Ordering number : ENN*6715

CMOS IC

LC875164A/48A/32A

8-Bit Single Chip Microcontroller with

64/48/32K-Byte ROM and 1024 -Byte RAM On Chip

Preliminary Overview

The LC875164A/48A/32A microcontroller is 8-bit single chip microcontroller with the following on-chip functional blocks:

- CPU: Operable at a minimum bus cycle time of 100ns

- 64K/48K/32K bytes ROM

- 1024 byte RAM

- two high performance 16 bit timer/counters (can be divided into 8 bit units)

- two 8 bit timers with prescalers

- timer for use as date/time clock

- two synchronous serial I/O ports (with automatic block transmit/receive function)

- one asynchronous/synchronous serial I/O port

- 12-bit PWM × 2

- 8-channel × 8-bit AD converter

- high speed 8-bit parallel interface

- 19-sour ce 10-vec tored interrupt system

All of the above functions are fabricated on a single chip.

Features

(1) Read Only Memory

- 65536 × 8 bits (LC875164A)

- 49151 × 8 bits (LC875148A)

- 32512 × 8 bits (LC875132A)

Ver.1.03 O3098

91400 RM (IM) HK / SY No.6715-1/25

LC875164A/48A/32A

(2) Bus Cycle Time

- 100ns (10MHz) Note: The bus cycle time indicates ROM read time.

(3) Minimum Instruction Cycle Time : 300ns (10MHz)

(4) Ports

- Input/output ports Each bit data direction programmable 59 (P1n,P2n,P3n,P70 to P73,P8n,PAn,PBn,PCn,S2Pn) Nibble data direction programmable 8 (P0n)

- Input ports 2 (XT1,XT2)

- PWM Output po rts 2 (PWM0,PWM1)

- Oscillator pins 2 (CF1,CF2)

- Reset pin 1 (

RES)

- Power supply 6 (VSS1 to 3,VDD1 to 3)

(5) Timers

- Timer0: 16 bit timer/counter with capture register

Mode 0: 2 channel 8 bit timer with programmable 8 bit prescaler and 8 bit capture register Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit counter with 8 bit

capture register Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register Mode 3: 16 bit counter with 16 bit capture register

- Timer1: PWM/16 b it timer/counter (with togg le output) Mode 0: 8 bit timer (with toggle output) + 8 bit timer counter (with toggle output) Mode 1: 2 channel 8 bit PWM Mode 2 : 1 6 bit timer/counter (wit h toggle outp ut) Mode 3: 16 bit timer (with toggle output) Lower order 8 bits can be used as PWM output.

- Timer4: 8-bit timer with 6-bit prescaler

- Timer5: 8-bit timer with 6-bit prescaler

- Base timer

1. The clock signal can be selected from any of the following: sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output for timer 0.

2. Interrupts can be selected to occur at one of five different times.

(6) SIO

- SIO0: 8 bit synchronous serial interface

1. LSB first/MSB first function available

2. Internal 8-bit baud-rate generator (maximum transmit clock period 4/3 T

3. Continuous automatic data communications (1 - 256 bits)

- SIO1: 8 bit asynchronous/synchronous serial interface Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2 - 512 T Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8 - 2048 T Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 - 512 T Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)

- SIO2: 8 bit synchronous serial interface

1. LSB-first

2. Built in 8-bit baud-rate generator (Maximum clock period 4/3 T

3. Continuous automatic data communication (1 - 32 bytes)

(7) AD converter

- 8-bits × 8-channels

(8) PWM

- 2 channel synchronous variable 12 bit PWM

(9) Parallel interface

RD , WR , CS0 - CS2 Outputs (reversible polarity)

- RS,

- read/write possible in 1 T

CYC

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CYC

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LC875164A/48A/32A

(10) Remote control receiver circuit (connected to P73/INT3/T0IN terminal)

- Noise rejection function (noise rejection filter time constant can selected from 1/32/128 T

(11) Watchdog timer

- The watchdog timer period set by external RC.

- Watchdog timer can be set to produce interrupt, system reset

(12) Interrupts

- 19-source, 10-vectored interrupts:

1. Three level (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or lower level interrupt request is refused.

2. If interrupt requests to two or more vector addresses occur at once, the higher level interrupt takes precedence. In the case of equal priority levels, the vector with the lowest address takes precedence.

No. Vector Selectable Level Interrupt signal

1 00003H X or L INT0 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/INT4 4 0001BH H or L INT3/INT5/Base timer 5 00023H H or L T0H 6 0002BH H or L T1L/T1H 7 00033H H or L SIO0 8 0003BH H or L SIO1/ SIO2 9 00043H H or L ADC

10 0004BH H or L Port 0/T4/T5/PWM0, 1

• Priority Lev el : X > H > L

• For equal priority levels, vector with lowest address takes precedence.

(13) Subroutine stack levels

- 512 levels max. Stack is located in RAM

(14) Multiplication and division

- 16 bit × 8 bit (executed in 5 cycles)

- 24 bit × 16 bit (12 cycles )

- 16 bit ÷ 8 bit (8 cycles)

- 24 bit ÷ 16 bit (12 cycles)

(15) Oscillation circuits

- On-chip RC oscillation circuit used for system clock

- On-chip CF oscillation circuit used for system clock

- On-chip Crystal oscillation circuit used for system clock and time-base clock

(16) Standby function

- HALT mode HALT mode is used to reduce power consumption. Program execution is stopped. Peripheral circuits still operate.

1. Oscillation circuits are not stopped automatically

2. Release on system reset

- HOLD mode HOLD mode is used to reduce the power dissipation. Both program execution and peripheral circuits are stopped.

1. CF, RC and crystal oscillation circuits stop automatically

2. Release occurs on any of the following conditions

•input to the reset pin goes low

•a specified level is input to at least one of INT0, INT1, INT2, INT4, INT5

•an interrupt condition arises at port 0

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LC875164A/48A/32A

- X’tal HOLD mode X’tal HOLD mode is used to reduce power consumption. Program execution is stopped. All peripheral circuits except the base timer are stopped.

1. CF and RC oscillation circuits stop automatically

2. Crystal oscillator is maintained in its state at HOLD mode inception.

3. Release occurs on any of the following conditions

•input to the reset pin goes low

•a specified level is input to at least one of INT0, INT1, INT2, INT4, INT5

•an interrupt condition arises at port 0

•an interrupt condition arises at the base-timer

(17) Factory shipment

- delivery form QIP80E

- delivery form SQFP80

(18) Development Tools

- Evaluation chip : LC876099

- Emulator : EVA87000 + ECB875100 (Evaluation chip board) + POD875100 (P O D)

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LC875164A/48A/32A

Pin Assignment

PB4/D4 PB3/D3 PB2/D2 PB1/D1 PB0/D0

VSS3

VDD3 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0

PA0/CS2#

66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

Package Dimension

(unit : mm)

3174

PB5/D5

PB6/D6

PB7/D7

P27/INT5/T1IN

P26/INT5/T1IN

P25/INT5/T1IN

P24/INT5/T1IN

P23/INT4/T1IN

P22/INT4/T1IN

P21/INT4/T1IN

P20/INT4/T1IN

P07

P06

P05

P04

P03

P02

P01

P00

VSS2

VDD2

PWM0

PWM1

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

LC875164A/48A/32A

QIP80

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

CF1

VSS1

CF2

VDD1

P80/AN0

P81/AN1

P82/AN2

P83/AN3

P84/AN4

P85/AN5

P86/AN6

PA1/CS1

PA2/CS0

XT1

XT2

PA5/RS

PA4/RD

PA3/WR

P70/INT0/T0LCP

P71/INT1/T0HCP

RES#

P73/INT3/T0I

P72/INT2/T0I

SI2P3/SCK20

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

P87/AN7

SI2P2/SCK2 SI2P1/S12/SB2 SI2P0/SO2 P17/T1PWMH/BUZ P16/T1PWML P15/SCK1 P14/SI1/SB1 P13/SO1 P12/SCK0 P11/SI0/SB0 P10/SO0 P34 P33 P32 P31 P30

SANYO : QIP-80E

No.6715-5/25

Pin Assignment

PB6/D6 PB5/D5 PB4/D4 PB3/D3 PB2/D2 PB1/D1 PB0/D0

VSS3

VDD3 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0

PA0/CS2# PA1/CS1# PA2/CS0#

Package Dimension

(unit : mm)

3220

LC875164A/48A/32A

PB7/D7

P27/INT5/T1IN

P26/INT5/T1IN

P25/INT5/T1IN

P24/INT5/T1IN

P23/INT4/T1IN

P22/INT4/T1IN

P21/INT4/T1IN

P20/INT4/T1IN

P07

P06

P05

P04

P03

P02

P01

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

PA5/RS

PA4/RD

PA3/WR#

LC875164A/48A/32A

SQFP80

XT1

RES#

P73/INT3/T0IN

P72/INT2/T0I

P70/INT0/T0LCP

P71/INT1/T0HCP

XT2

VSS1

CF1

CF2

VDD1

P80/AN0

P81/AN1

P00

VSS2

VDD2

PWM0

PWM1

SI2P3/SCK20

SI2P2/SCK2

SI2P1/SI2/SB2

SI2P0/SO2

P17/T1PWMH/BUZ

P16/T1PWML

P15/SCK1

P14/SI1/SB1

P13/SO1

P12/SCK0

P11/SI0/SB0

P10/SO0

P34

P33

P32

P31

P30

P87/AN7

P86/AN6

P82/AN2

P83/AN3

P84/AN4

P85/AN5

SANYO : SQFP-80

No.6715-6/25

LC875164A/48A/32A

QIP NAME SQFP QIP NAME SQFP

1 2 3 4 5 PA5/RS 3 45 VSS2 43

6 P70/INT0/T0LCP 4 46 P00 44 7 P71/INT1/T0HCP 5 47 P01 45 8 P72/INT2/T0IN 6 48 P02 46 9 P73/INT3/T0IN 7 49 P03 47

10 11 XT1 9 51 P05 49

12 XT2 10 52 P06 50 13 VSS1 11 53 P07 51 14 CF1 12 54 P20/INT4/T1IN 52 15 CF2 13 55 P21/INT4/T1IN 53 16 VDD1 14 56 P22/INT4/T1IN 54 17 P80/AN0 15 57 P23/INT4/T1IN 55 18 P81/AN1 16 58 P24/INT5/T1IN 56 19 P82/AN2 17 59 P25/INT5/T1IN 57 20 P83/AN3 18 60 P26/INT5/T1IN 58 21 P84/AN4 19 61 P27/INT5/T1IN 59 22 P85/AN5 20 62 PB7/D7 60 23 P86/AN6 21 63 PB6/D6 61 24 P87/AN7 22 64 PB5/D5 62 25 P30 23 65 PB4/D4 63 26 P31 24 66 PB3/D3 64 27 P32 25 67 PB2/D2 65 28 P33 26 68 PB1/D1 66 29 P34 27 69 PB0/D0 67 30 P10/SO0 28 70 VSS3 68 31 P11/SI0/SB0 29 71 VDD3 69 32 P12/SCK0 30 72 PC7/A7 70 33 P13/SO1 31 73 PC6/A6 71 34 P14/SI1/SB1 32 74 PC5/A5 72 35 P15/SCK1 33 75 PC4/A4 73 36 P16/T1PWML 34 76 PC3/A3 74 37 P17/T1PWMH/BUZ 35 77 PC2/A2 75 38 SI2P0/SO2 36 78 PC1/A1 76 39 SI2P1/SI2/SB2 37 79 PC0/A0 77 40 SI2P2/SCK2 38 80

PA1/ PA2/ PA3/

PA4/

RES

CS1 CS0 WR

79 41 SI2P3/SCK20 39 80 42 PWM1 40

1 43 PWM0 41 2 44 VDD2 42

8 50 P04 48

PA0/

CS2

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System Block Diagram

SIO0

SIO1

SIO2

Timer 0

Timer 1

Timer 4

Timer 5

PWM0

PWM1

Base Timer

Interrupt control

Standby control

Xtal

IR PLA

ROM

Clock

Generator

Noise Rejection Filter

Port 2 INT4,,5

Bus Interface

Port 0

Port 1

Port 3

Port 7

Port 8

ADC

INT0-3

Parallel interface

Port A Port B Port C

ACC

B Register

C Register

ALU

PSW

RAR

RAM

Stack Pointer

Watch Dog Timer

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