SANYO LC875016A, LC875032A Datasheet

Ordering number : ENN*6713

CMOS IC

LC875032A/24A/16A

8-Bit Single Chip Microcontroller with

32/24/16K-Byte EPROM an d 64 0- Byte RAM On Chip

Preliminary
Overview

The LC875032A/24A/16A microcontroller is 8-bit single chip microcontroller with the following on-chip functional blocks:

- CPU: Operable at a minimum bus cycle time of 100ns

- 32K/24K/16K bytes ROM

- 640 byte RAM

- two high performance 16 bit timer/counters (can be divided into 8 bit units)

- two 8 bit timers with prescalers

- timer for use as date/time clock

- one synchronous serial I/O ports (with automatic block transmit/receive function)

- one asynchronous/synchronous serial I/O port

- 12-bit PWM × 2

- 3-channel × 8-bit AD converter

- high speed 8-bit parallel interface

- 16-sour ce 10-vec tored interrupt system

All of the above functions are fabricated on a single chip.

Features

(1) Read Only Memory (ROM)

- 32512 × 8 bits (LC875032A)

- 24576 × 8 bits (LC875024A)

- 16256 × bits (LC875016A)

Ver.1.03
90198

91400 RM (IM) HK / SY No.6713-1/25

LC875032A/24A/16A

(2) Random Access Memory (RAM)

- 640 × 9 bits (LC875032A/24A/16A)

(3) Bus Cycle Time

- 100ns (10MHz)
Note: The bus cycle time indicates ROM read time.

(4) Minimum Instruction Cycle Time : 300ns (10MHz)

(5) Ports

- Input/output ports
Each bit data direction programmable 51 (P1n, P2n, P70 to P73, P80 to P82, PA2 to PA5,

PBn, PCn)

Nibble data direction programmable 8 (P0n)

- Input ports 2 (XT1,XT2)

- PWM Output po rts 2 (PWM0,PWM1)

- Oscillator pins 2 (CF1,CF2)

- Reset pin 1 (

RES)

- Power supply 6 (VSS1 to 3,VDD1 to 3)

(6) Timers

- Timer0: 16 bit timer/counter with capture register

Mode 0: 2 channel 8 bit timer with programmable 8 bit prescaler and 8 bit capture register
Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit counter with 8 bit

capture register
Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register
Mode 3: 16 bit counter with 16 bit capture register

- Timer1: PWM/16 b it timer/counter (with togg le output)
Mode 0: 8 bit timer (with toggle output) + 8 bit timer counter (with toggle output)
Mode 1: 2 channel 8 bit PWM
Mode 2 : 1 6 bit timer/counter (wit h toggle outp ut)
Mode 3: 16 bit timer (with toggle output) Lower order 8 bits can be used as PWM output.

- Base timer

1. The clock signal can be selected from any of the following: sub-clock (32.768kHz crystal oscillator), system
clock, and prescaler output for timer 0.

2. Interrupts can be selected to occur at one of five different times.

(7) SIO

- SIO0: 8 bit synchronous serial interface

1. LSB first/MSB first function available

2. Internal 8-bit baud-rate generator (maximum transmit clock period 4/3 T

3. Continuous automatic data communications (1 - 256 bits)

- SIO1: 8 bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2 - 512 T
Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8 - 2048 T
Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 - 512 T
Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)

(8) AD converter

- 8-bits × 3-channels

(9) PWM

- 2 channel synchronous variable 12 bit PWM

(10) Parallel interface

- RS,

RD , WR , CS0 - CS2 Outputs (reversible polarity)

- read/write possible in 1 T

CYC

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LC875032A/24A/16A

(11) Remote control receiver circuit (connected to P73/INT3/T0IN terminal)

- Noise rejection function (noise rejection filter time constant can selected from 1/32/128 T

(12) Watchdog timer

- The watchdog timer period set by external RC.

- Watchdog timer can be set to produce interrupt, system reset

(13) Interrupts

- 16-source, 10-vectored interrupts:

1. Three level (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or
lower level interrupt request is refused.

2. If interrupt requests to two or more vector addresses occur at once, the higher level interrupt takes precedence.
In the case of equal priority levels, the vector with the lowest address takes precedence.

No. Vector Selectable Level Interrupt signal

1 00003H X or L INT0
2 0000BH X or L INT1
3 00013H H or L INT2/T0L/INT4
4 0001BH H or L INT3/INT5/Base timer
5 00023H H or L T0H
6 0002BH H or L T1L/T1H
7 00033H H or L SIO0
8 0003BH H or L SIO1
9 00043H H or L ADC

10 0004BH H or L Port 0/PWM0, 1

• Priority Lev el : X > H > L

• For equal priority levels, vector with lowest address takes precedence.

(14) Subroutine stack levels

- 320 levels max. Stack is located in RAM

(15) Multiplication and division

- 16 bit × 8 bit (executed in 5 cycles)

- 24 bit × 16 bit (12 cycles )

- 16 bit ÷ 8 bit (8 cycles)

- 24 bit ÷ 16 bit (12 cycles)

(16) Oscillation circuits

- On-chip RC oscillation circuit used for system clock

- On-chip CF oscillation circuit used for system clock

- On-chip Crystal oscillation circuit used for system clock and time-base clock

(17) Standby function

- HALT mode
HALT mode is used to reduce power consumption. Program execution is stopped. Peripheral circuits still operate.

1. Oscillation circuits are not stopped automatically

2. Release on system reset

- HOLD mode
HOLD mode is used to reduce the power dissipation. Both program execution and peripheral circuits are stopped.

1. CF, RC and crystal oscillation circuits stop automatically

2. Release occurs on any of the following conditions

•input to the reset pin goes low

•a specified level is input to at least one of INT0, INT1, INT2, INT4, INT5

•an interrupt condition arises at port 0

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LC875032A/24A/16A

- X’tal HOLD mode
X’tal HOLD mode is used to reduce power consumption. Program execution is stopped. All peripheral circuits
except the base timer are stopped.

1. CF and RC oscillation circuits stop automatically

2. Crystal oscillator is maintained in its state at HOLD mode inception.

3. Release occurs on any of the following conditions

•input to the reset pin goes low

•a specified level is input to at least one of INT0, INT1, INT2, INT4, INT5

•an interrupt condition arises at port 0

•an interrupt condition arises at the base-timer

(18) Factory shipment

- delivery form QIP64E

- delivery form DIP64S

(19) Development Tools

- Evaluation chip : LC876098

- Emulator : EVA87000 + ECB875000 (Evaluation chip board) + POD875000 (P OD)

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Pin Assignment

Q

P70/INT0/T0LCP

P71/INT1/T0HCP

P72/INT2/T0IN
P73/INT3/T0IN

RES#

XT1
XT2

VSS1

CF1
CF2

VDD1
P80/AN0
P81/AN1
P82/AN2

P10/SO0

P11/SI0/SB0

Package Dimension

(unit : mm)

3159

LC875032A/24A/16A

PA5/RS

PA4/RD#

PA3/WR#

PA2/CS0#

PC0/A0

PC1/A1

PC2/A2

PC3/A3

PC4/A4

PC5/A5

PC6/A6

PC7/A7

VDD3

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

P12/SCK0

LC875032A/24A/16A

IP

PWM1

P13/SO1

P15/SCK1

P14/SI1/SB1

P16/T1PWML

PWM0

P17/T1PWMH/BUZ

P00

P01

VSS2

VDD2

P02

VSS3

P03

PB0/D0

P04

PB1/D1

P05

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

PB2/D2
PB3/D3
PB4/D4
PB5/D5
PB6/D6
PB7/D7
P27/INT5/T1IN
P26/INT5/T1IN
P25/INT5/T1IN
P24/INT5/T1IN
P23/INT4/T1IN
P22/INT4/T1IN
P21/INT4/T1IN
P20/INT4/T1IN
P07
P06

SANYO : QIP-64E

No.6713-5/25

PC3/A3
PC2/A2
PC1/A1
PC0/A0

PA2/CS0#

PA3/WR#

PA4/RD#

PA5/RS

P70/INT0/T0LCP

P71/INT1/T0HCP

P72/INT2/T0IN
P73/INT3/T0IN

P80/AN0
P81/AN1
P82/AN2

P10/SO0

P11/SI0/SB0

P12/SCK0

P13/SO1

P14/SI1/SB1

P15/SCK1

P16/T1PWML

P17/T1PWMH/BUZ

Package Dimension

(unit : mm)

3071

RES#

XT1
XT2

VSS1

CF1
CF2

VDD1

PWM1
PWM0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

LC875032A/24A/16A

LC875032A/24A/16A

DIP

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

PC4/A4
PC5/A5
PC6/A6
PC7/A7
VDD3
VSS3
PB0/D0
PB1/D1
PB2/D2
PB3/D3
PB4/D4
PB5/D5
PB6/D6
PB7/D7
P27/INT5/T1IN
P26/INT5/T1IN
P25/INT5/T1IN
P24/INT5/T1IN
P23/INT4/T1IN
P22/INT4/T1IN
P21/INT4/T1IN
P20/INT4/T1IN
P07
P06
P05
P04
P03
P02
P01
P00
VSS2
VDD2

SANYO : DIP-64S

No.6713-6/25

LC875032A/24A/16A

QIP NAME DIP QIP NAME DIP

1 P12/SCK0 25 33 PB1/D1 57
2 P13/SO1 26 34 PB0/D0 58
3 P14/SI1/SB1 27 35 VSS3 59
4 P15/SCK1 28 36 VDD3 60
5 P16/T1PWML 29 37 PC7/A7 61
6 P17/T1PWMH/BUZ 30 38 PC6/A6 62
7 PWM1 31 39 PC5/A5 63
8 PWM0 32 40 PC4/A4 64
9 VDD2 33 41 PC3/A3 1

10 VSS2 34 42 PC2/A2 2
11 P00 35 43 PC1/A1 3
12 P01 36 44 PC0/A0 4
13 P02 37 45 PA2/CS0# 5
14 P03 38 46 PA3/WR# 6
15 P04 39 47 PA4/RD# 7
16 P05 40 48 PA5/RS 8
17 P06 41 49 P70/INT0/T0LCP 9
18 P07 42 50 P71/INT1/T0HCP 10
19 P20/INT4/T1IN 43 51 P72/INT2/T0IN 11
20 P21/INT4/T1IN 44 52 P73/INT3/T0IN 12
21 P22/INT4/T1IN 45 53 RES# 13
22 P23/INT4/T1IN 46 54 XT1 14
23 P24/INT5/T1IN 47 55 XT2 15
24 P25/INT5/T1IN 48 56 VSS1 16
25 P26/INT5/T1IN 49 57 CF1 17
26 P27/INT5/T1IN 50 58 CF2 18
27 PB7/D7 51 59 VDD1 19
28 PB6/D6 52 60 P80/AN0 20
29 PB5/D5 53 61 P81/AN1 21
30 PB4/D4 54 62 P82/AN2 22
31 PB3/D3 55 63 P10/SO0 23
32 PB2/D2 56 64 P11/SI0/SB0 24

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LC875032A/24A/16A

System Block Diagram

SIO0

SIO1

Timer 0

Timer 1

PWM0

PWM1

Base Timer

Interrupt control

Standby control

CF

RC

Xtal

IR PLA

ROM

Clock

Generator

Noise Rejection Filter

Port 2 INT4,,5

Bus Interface

Port 0

Port 1

Port 7

Port 8

ADC

INT0-3

Parallel interface

Port A
Port B
Port C

PC

ACC

B Register

C Register

ALU

PSW

RAR

RAM

Stack Pointer

Watch Dog Timer

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