Sanyo LC86P4448 Specifications

Ordering number: EN*5583

Preliminary

LC86P4448

CMOS LSI

LC86P4448

8-bit Single Chip Microcontroller

Overview

The LC86P4448 is a CMOS 8-bit single chip microcontroller
with one-time PROM for the LC864400 series.
This microcontroller has the same function and the pin

Package Dimensions

unit : mm

3071-DIP64S

description as the LC864400 series mask ROM version, and
the 48K-byte PROM. It is suitable for developing programs.

1

Features

(1) Option switching by PROM data

The option function of the LC864400 series can be specified by the PROM data.

The functions of the trial pieces can be evaluated using the mass production board.
(2) Internal PROM capacity : 49152 bytes
(3) Internal RAM capacity : 384 bytes

[LC86P4448]

3364

32

57.2

0.95 0.48 1.78 1.01

SANYO : DIP64S

5.0max

4.00.51min

3.2

19.5

16.8

0.25

Mask ROM version PROM capacity RAM capacity

LC864448 49152 bytes 384 bytes
LC864444 45056 bytes 384 bytes
LC864440 40960 bytes 384 bytes
LC864436 36864 bytes 384 bytes
LC864432 32768 bytes 384 bytes
LC864428 28672 bytes 384 bytes
LC864424 24576 bytes 384 bytes
LC864420 20480 bytes 384 bytes

(4) Operating supply voltage : 4.5 V to 5.5 V
(5) Instruction cycle time : 0.99 µs to 366 µs
(6) Operating temperature : –30°C to +70°C
(7) The pin and package compatible with the LC864400 series mask ROM devices
(8) Applicable mask ROM version : LC864448/LC864444/LC864440/LC864436/LC864432

LC864428/LC864424/LC864420

(9) Factory shipment : DIP64S

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

SANYO Electric Co., Ltd. Semiconductor LSI Div. Microcomputer Development Dep.

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

22898HA (II)

No. 5583-1/20

LC86P4448

Usage Notes

The LC86P4448 is proveded for the first release and small shipping of the LC864400 series.
At using, take notice of the followings.

(1) Differences between the LC86P4448 and the LC864400 series

Item LC86P4448 LC864448/44/40/36/32/28/24/20

Operation after reset
releasing

Operating supply
voltage range (V

DD

)

Power dissipation Refer to 'electrical characteristics' on the semiconductor news.

The LC86P4448 uses 256 bytes addressed on FF00H to FFFFH in the program memory as the option configuration data area.
All options of the LC864400 series can be specified.

(2) Option

The option data is written with the option specifying program "SU86K.EXE". The option data is linked to the program area by
the linkage loader "L86K.EXE".

The option is specified by degrees until 3 ms
after going to a 'H' level to the reset terminal.
The program is executed from 00H of the
program counter.

4.5 V to 5.5 V

The program is executed from 00H of the program
counter immediately after going to a 'H' level to the
reset terminal.

2.7 V to 5.5 V

(3) ROM space

The LC86P4448 and LC864400 series use 256 bytes addressed on FF00H to FFFFH in the program memory as the option
specified data area. The program memory capacity of this series is, at most, 49152 bytes addressed on 0000H to BFFFH.

13FFFFH

0FFFFH

0FF00H

0FEFFH

0BFFFH
0AFFFH
09FFFH
08FFFH
07FFFH
06FFFH

0000H

13FFFFH

0FFFFH

0FF00H

0FEFFH

Character
generator ROM

Option specified
area 256 bytes

Program area Program area Program area Program area Program area Program area

48K bytes 44K bytes 40K bytes 36K bytes 32K bytes 26K bytes

LC864448 LC864444 LC864440 LC864436 LC864426

Character
generator ROM

Option specified
area 256 bytes

Character
generator ROM

Option specified
area 256 bytes

Character
generator ROM

Option specified
area 256 bytes

Character
generator ROM

Option specified
area 256 bytes

Character
generator ROM

Option specified
area 256 bytes

Character
generator ROM

Option specified
area 256 bytes

LC864432

Character
generator ROM

Option specified
area 256 bytes

05FFFH
04FFFH

0000H

Program area Program area

24K bytes 20K bytes

LC864424 LC864420

No. 5583-2/20

LC86P4448

How to Use

(1) Create a programming data for LC86P4448

Programming data for EPROM of the LC86P4448 is required.
Debugged evaluation file (EVA file) must be converted to an INTEL-HEX formatted file (HEX file) with the file converter
program EVA2HEX.EXE. The HEX file is used as the programming data for the LC86P4448.

(2) How to program for the PROM

The LC86P4448 can be programmed by the EPROM programmer with attachment W86EP4448D.

• Recommended EPROM programmer

Manufacturer

Productor

Advantest

Andou

AVAL

Minato electronics

EPROM programmer

R4945, R4944, R4943

AF-9704

PKW-1100, PKW-3000

MODEL1890A

• "27010 (Vpp = 12.5 V) Intel high speed programming" mode should be adopted. The address must be set to 13FFFH" and
jumper (DASEC) must be set to 'OFF' at programming.

(3) How to use the data security function

"Data security" is the function to disable the EPROM data from being read out.
The following is the process in order to execute data security function.

1. Set the jumper of attachment 'ON'.

2. Program again. The EPROM programmer will display an error. The error means that the data security functions
normally. It is not trouble of the EPROM programmer or the LSI.

Notes

• Data security is not executed when the data of all addresses have 'FF' at procedure 2 above.

• Data security cannot be executed by programming the sequential operation "BLANK=>PROGRAM=>VERIFY" at

procedure 2 above.

• Set the jumper to 'OFF' after executing the data security.

Data security

Data security OFF

the

Jumper

Pin 1

Jumper

W86EP4448D

No. 5583-3/20

Pin Assignment

LC86P4448

P10/SO0

P11/SI0/SB0

P12/SCK0

P13
P14
P15
P16

P17/PWM

XT1
XT2

DVSS

CF1
CF2

DVDD
P90/AN0
P91/AN1
P92/AN2
P93/AN3
P94/AN4
P95/AN5
P96/AN6
P97/AN7

RES
LC1

LC2
FILT
AVDD
AVSS
CVIN

VS
HS

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

I

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

P07
P06
P05
P04
P03
P02
P01
P00
P25
P24
P23
P22
P21
P20
P73/INT3/T0IN
P72/INT2/T0IN
P71/INT1
P70/INT0
PWM9
PWM8
PWM7
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
BL
B
G
R

Top view

No. 5583-4/20

System Block Diagram

LC86P4448

Base timer

SIO0

Timer 0

Timer 1

ADC

Interrupt control

Standby control

X'tal

RC

CF

Colck

generator

Bus interface

Port 1

Port 2

Port 7

Port 9

IR PLA

PROM
control

PROM(48KB)

PC

ACC

B register

C register

ALU

PSW

A16 to A0
D7 to D0
TA
CE
OE
DASEC

INT0 to INT3

Noise rejection filter

PWM

Data slicer

PLL

LC

VRAM

CGROM

OSD

control

circuit

RAR

RAM

Stack pointer

Port 0

Watchdog timer

No. 5583-5/20

LC86P4448

Pin Description

• Port option can be specified by bit units.

• At port 0, 'Pull-up resistor provided' when specifying CMOS output.

'Pull-up resistor not provided' when specifying N-ch open drain output.

• At port 1 and 2, 'Programmable pull-up resistor provided' when specifying either CMOS or N-ch open drain output.

Pin Description Table

Pin name Pin No. I/O Function description Option PROM mode

DVSS 11 — Negative power supply for digital circuit

XT1 9 I Input pin for the crystal oscillation
XT2 10 O Output pin for the crystal oscillation
CF1 12 I Input terminal for ceramic resonator
CF2 13 O Output terminal for ceramic resonator

DV

DD

RES 23 I Reset terminal

LC1 24 I LC oscillation circuit input terminal
LC2 25 O LC oscillation circuit output terminal

FILT 26 O Filter terminal for PLL
AVDD 27 — Positive power supply for analog circuit
AVSS 28 — Negative power supply for analog circuit

CVIN 29 I Video signal input terminal

VS 30 I Vertical synchronization signal input terminal
HS 31 I Horizontal synchronization signal input terminal

I 32 O Image intensity output
R 33 O Red (R) output terminal of RGB image output A4 (*1)
G 34 O Green (G) output terminal of RGB image output A5 (*1)
B 35 O Blue (B) output terminal of RGB image output A6 (*1)

BL 36 O Fast blanking control signal A7 (*1)

PWM0 37 to 46 O PWM0 to 9 output terminal PWM 0 to 8 :

to PWM9 15 V withstand A8 to A16 (*1)

Port 0 8-bit Input/output port Pull-up resistor

P00 to P07 57 to 64 I/O Input/output can be specified in nibble units Provided/not provided

Port 1 8-bit Input/output port Output Format D0 to D7 (*2)

P10 to P17 1 to 8 I/O Input/output can be specified in bit units. CMOS/Nch-OD

14 — Positive power supply for digital circuit

Switch TV image signal and caption/
OSD image signal

PWM 9 : "L" fixed

HOLD release input (in bit units)
Interrupt input Output Format

CMOS/Nch-OD
(in bit units)

Other function (in bit units)

P10 SIO0 data output
P11 SIO0 data input /bus input/output
P12 SIO0 clock input/output
P17 Timer 1 (PWM) output

Port 2 6-bit Input/output port Output Format

P20 to P25 51 to 56 I/O Input/output can be specified in bit units. CMOS/Nch-OD

(in bit units)

No. 5583-6/20

LC86P4448

Pin name Pin No. I/O Function description Option PROM mode

Port 7 4-bit input port Pull-up resistor P70 : VPP (*3)

P70 47 I/O Other function provided/ P71 : DASEC (*4)

P71 to P73 48 to 50 I not provided P72 : OE (*5)

Port 9 8-bit input port P90 to P93 :

P90 to P97 15 to 22 I Other function A0 to A3 (*1)

P70 NT0 input/HOLD release input/Nch-

transistor output for watchdog timer
P71 INT1 input/HOLD release input
P72 INT2 input/timer 0 event input
P73 INT3 input (noise rejection filter

attached input/timer 0 event input

Interrupt receiver format vector address

Rise Fall Rise/Fall H level L level Vector
INT0 enable enable disable enable enable 03H
INT1 enable enable disable enable enable 0BH
INT2 enable enable enable disable disable 13H
INT3 enable enable enable disable disable 1BH

AD converter input port (8 lines)

(in bit units) P73 : CE (*6)

*1 An → Address input
*2 Data I/O
*3 Power for programming
*4 Memory select input/output for data security
*5 Output Enable input
*6 Chip Enable input

• Port state during reset

Terminal I/O Pull-up resistor status at selecting pull-up option

Port 0 Input Pull-up resistor OFF, ON after reset release

Port 1, 2 Input Programmable pull-up resistor OFF

Port 7 Input Fixed pull-up resistor provided

* AVDD and AVSS are the power supply terminals for the analog operation block. DVDD and DVSS are the power supply

terminals for the digital operation block. Connect them like the following figure to reduce the mutual noise influence.

LSI

Power

Power

Supply

supply

DVDD

DVSS

AVDD

AVSS

No. 5583-7/20

LC86P4448

Specifications

1. Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V

Parameter Symbol Pins Conditions Ratings Unit

VDD [V] min typ max
Supply voltage VDDmax DVDD, AVDD DVDD = AVDD –0.3 +7.0 V
Input voltage VI(1) • P71, 72, 73 –0.3 VDD+0.3

• Port 9

• RES, HS, VS, CVIN

Output voltage VO(1) R, G, B, BL, I, FILT –0.3 VDD+0.3

VO(2) PWM0 to PWM9 –0.3 +15

Input/output VIO(1) Ports 0, 1, 2, P70 –0.3 VDD+0.3
voltage

I

High­level
output
current

Low­level
output
current

Peak
output
current

Total
output
current

Peak
output
current

Total
output
current

(1) Ports 0, 1, 2 –2mA

OPH

I

(2) Ports 0, 1, 2 –4

OPH

I

(3) R, G, B, BL, I –5

OPH

∑I

(1) Port 1 –10

OAH

∑I

(2) Ports 0, 2 –10

OAH

∑I

(3) R, G, B, BL, I –15

OAH

I

(1) Ports 0, 1, 2 20

OPL

I

(2) P70 30

OPL

I

(3) •R, G, B, BL, I 5

OPL

•PWM0 to PWM9

∑I

(1) Port 0, 2 40

OAL

∑I

(2) Port 1, P70 40

OAL

∑I

(3) R, G, B, BL, I 15

OAL

∑I

(4) PWM0 to PWM9 30

OAL

Maximum power Pd max DIP64S Ta = –30 to +70°C 720 mW
dissipation

Operating Topr –30 +70 °C
temperature
range

Storage Tstg –55 +125
temperature
range

•Pull-up MOS
transistor output

•At each pin

•CMOS output

•At each pin

•CMOS output

•At each pin

The total of all pins
The total of all pins
The total of all pins
At each pin
At each pin
At each pin

The total of all pins
The total of all pins
The total of all pins
The total of all pins

* DVSS and AVSS must be supplied the same voltage, VSS.V

DVDD and AVDD must be supplied the same voltage, V

.VDD = DVDD = AVDD

DD

= DVSS = AVSS

SS

No. 5583-8/20

LC86P4448

2. Recommended Operating Range at Ta = –30°C to +70°C, VSS = 0 V

Parameter Symbol Pins Conditions Ratings Unit

VDD [V] min typ max

Operating
supply
voltage range

VDD(1) DVDD, AVDD 4.5 5.5 V

VDD(2) 4.5 5.5

0.97 µs ≤ tCYC ≤ 1.02 µs

0.97 µs ≤ tCYC ≤ 400 µs

Hold voltage

Input
high-level
voltage

Input low-level
voltage

CVIN input
amplitude

Operation
cycle time

V

HD

DVDD, AVDD 2.0 5.5

RAMs and the registers

hold data at HOLD mode.
VIH(1) Port 0 (Schmitt) 4.5 to 5.5 0.6 V
VIH(2) •Ports 1, 2 (Schmitt) 4.5 to 5.5 0.75 V

Output disable

Output disable

DD

DD

V

DD

V

DD

•P72, 73

•HS, VS

VIH(3) •P70 4.5 to 5.5 0.75 V

port input / interrupt

Output N-channel

transistor OFF

DD

V

DD

•P71

•RES (Schmitt)

VIH(4) P70 4.5 to 5.5 VDD–0.5 V

Watchdog timer

Output N-channel

transistor OFF

DD

input

VIH(5) Port 9 4.5 to 5.5 0.7 V

DD

V

DD

port input
VIL(1) Port 0 (Schmitt) 4.5 to 5.5 V
VIL(2) •Porst 1, 2 (Schmitt) 4.5 to 5.5 V

Output disable
Output disable

SS

SS

0.2 V

0.25 V

DD

DD

•P72, 73

•HS, VS

•Port 9

VIL(3) •P70 4.5 to 5.5 V

N-channel transistor OFF

SS

0.25 V

DD

port input / interrupt

•P71

•RES (Schmitt)

VIL(4) P70 4.5 to 5.5 V

N-channel transistor OFF

SS

0.6 V

DD

Watchdog timer

input
VIL(5) Port 9 4.5 to 5.5 V

SS

0.3 V

DD

port input
V

CVIN

tCYC(1) 4.5 to 5.5 0.97 1 1.02 µs
tCYC(2) 4.5 to 5.5 0.97 400

CVIN 5.0 1Vp-p–3dB 1Vp-p 1Vp-p+3dB Vp-p

OSD function
Except OSD function

*

* Vp-p : Peak-to-peak voltage

No. 5583-9/20

LC86P4448

Parameter Symbol Pins Conditions Ratings Unit

VDD [V] min typ max

Oscillation
frequency range
(Note 1)

Oscillation
stable time
period
(Note 2)

FmCF(1) CF1, CF2 12 MHz (ceramic 4.5 to 5.5 11.76 12 12.24 MHz

resonator oscillation)
Refer to Figure 1.

FmCF(2) 12.08 MHz (ceramic 4.5 to 5.5 11.84 12.08 12.32

resonator oscillation)
Refer to Figure 1.

FmLC LC1, LC2 14.11 MHz 4.5 to 5.5 14.11

(LC oscillation)

Refer to Figure 2.
FmRC RC oscillation 4.5 to 5.5 0.4 0.8 3.0
FsXtal XT1, XT2 32.768 kHz (crystal 4.5 to 5.5 32.768 kHz

resonator oscillation)

Refer to Figure 3.

tmsCF(1) CF1, CF2 12 MHz (ceramic 4.5 to 5.5 0.02 0.2 ms

resonator oscillation)

Refer to Figure 4.

tmsCF(2) 12 MHz (ceramic 4.5 to 5.5 0.02 0.2

resonator oscillation)

Refer to Figure 4.

tssXtal XT1, XT2 32.768 kHz (crystal 4.5 to 5.5 1.0 5.0 s

resonator oscillation)

Refer to Figure 4.

(Note 1) Refer to tables 1, 2 and 3 for oscillation constant.
(Note 2) The oscillation stable time period refers to the time it takes to oscillate stably after the following conditions.

1. Applying the first supply voltage.

2. Release of the HOLD mode.

3. Release of the stopping of the main-clock oscillation. (Refer to Figure 4)

No. 5583-10/20

LC86P4448

3. Electrical Characteristics at Ta = –30°C to +70°C , VSS = 0 V

Parameter Symbol Pins Conditions Ratings Unit

VDD [V] min typ max

Input high-level
current

Input low-level
current

Output high-level
voltage

Output low-level
voltage

Pull-up MOS
transistor
resistance

Output off-leakage
current

Hysteresis
voltage

IIH(1) 4.5 to 5.5 1 µA

• Ports 1, 2

• Port 0 without

pull-up MOS
transistor

IIH(2) 4.5 to 5.5 1

• Port 7 without
pull-up MOS
transistor

• Port 9

• RES

• HS, VS

IIL(1) 4.5 to 5.5 –1

• Ports 1, 2

• Port 0 without

pull-up MOS
transistor

IIL(2) 4.5 to 5.5 –1

• Port 7 without
pull-up MOS
transistor

• Port 9

IIL(3) 4.5 to 5.5 –1

• RES

• HS, VS

VOH(1) 4.5 to 5.5 VDD–1V

CMOS output of

ports 0, 1, 2
VOH(2) 4.5 to 5.5 VDD–0.5
VOL(1) 4.5 to 5.5 1.5
VOL(2) 4.5 to 5.5 0.4

VOL(3) 4.5 to 5.5 0.4

R, G, B, BL, I

Ports 0, 1, 2

Ports 0, 1, 2

• R, G, B, BL, I

• PWM0 to PWM9

VOL(4) 4.5 to 5.5 0.4

Rpu 4.5 to 5.5 13 38 80 kΩ

P70

• Ports 0, 1, 2

• Port 7

PWM0 to PWM9

• Ports 0, 1, 2

V

I

OFF

HIS

• Port 7

• RES

• HS, VS

• Output disable

• Pull-up MOS

transistor OFF

• V

= V

IN

DD

(including the off-leak
current of the output
transistor)

V

= V

IN

DD

• Output disable

• Pull-up MOS

transistor OFF

• V

= V

IN

SS

(including the off-leak
current of the output
transistor)

V

= V

IN

SS

VIN = V

SS

IOH = –1.0 mA

I

= –0.1 mA

OH

I

= 10 mA

OL

• I

= 1.6 mA

OL

• The total current of
the ports 0, 1 is
40 mA or less.

• I

= 3.0 mA

OL

• The current of any
unmeasured pin is
3 mA or less.

I

= 1 mA

OL

V

= 0.9V

OH

V

OUT

DD

= 13.5 V

Output disable

4.5 to 5.5 5 µA

4.5 to 5.5 0.1V

DD

V

No. 5583-11/20

LC86P4448

Parameter Symbol Pins Conditions Ratings Unit

VDD [V] min typ max

Input clamp
voltage

Pin capacitance

V

CLMP

CP All pins •f = 1 MHz 4.5 to 5.5 10 pF

4. Serial Input/Output Characteristics at Ta = –30°C to +70°C , VSS = 0 V

Parameter Symbol Pins Conditions Ratings Unit

Cycle
Low-

level
pulse
width

Input clock

High­level
pulse
width

Cycle

Serial clock

Low­level
pulse
width

High-

Output clock

level
pulse
width

Data set-up
time

Data hold
time

Serial input

tCKCY(1) 4.5 to 5.5 2 tCYC

tCKL(1) 1

tCKH(1) 1

tCKCY(2) 4.5 to 5.5 2

tCKL(2) 1/2tCKCY

tCKH(2) 1/2tCKCY

tICK 4.5 to 5.5 0.1 µs

tCKI 0.1

CV

IN

• SCK0

• SCLK0

• SCK0

• SCLK0

• SI0

• Unmeasured

terminals for the input
are set to V

• Ta = 25°C

Refer to Figure 6.

• Use a pull-up resistor
(1 kΩ) when open
drain output

• Refer to Figure 6.

• Data set-up to SCK0

rising

• Data hold from SCK0
rising

• Refer to Figure 6.

SS

level.

5.0 2.3 2.5 2.7 V

VDD [V] min typ max

Output delay
time
(External
serial clock)

Output delay
time

Serial output

(Internal
serial clock)

tCKO(1) 4.5 to 5.5 7/12tCYC

tCKO(2) 4.5 to 5.5 1/3tCYC

• SO0

• Use a pull-up resistor

(1 kΩ) when open
drain output.

• Data set-up to SCK0
falling

• Data hold from SCK0
falling

• Refer to Figure 6.

+0.2

+0.2

No. 5583-12/20

LC86P4448

5. Pulse Input Conditions at Ta = –30°C to +70°C, VSS = 0 V

Parameter Symbol Pins Conditions Ratings Unit

VDD [V] min typ max

High/low level tPIH(1) 4.5 to 5.5 1 tCYC
pulse width tPIL(1)

tPIH(2) 4.5 to 5.5 2

tPIL(2)

•INT0, INT1

•INT2/T0IN

INT3/T0IN
(The noise rejection
clock is set to 1/1)

tPIH(3)

tPIL(3) 4.5 to 5.5 32

INT3/T0IN
(The noise rejection
clock is set to 1/16)

tPIL(4) 4.5 to 5.5 200 µs

tPIH(5) 4.5 to 5.5 10 tCYC

RES
HS, VS

tPIL(5)

Rising/falling time tTHL 4.5 to 5.5 500 ns

HS

tTLH

Horizontal FH 4.5 to 5.5 15.23 15.73 16.23 kHz

HS

pull-in range

•Interrupt acceptable

•Timer0-countable

•Interrupt acceptable

•Timer0-countable

•Interrupt acceptable

•Timer0-countable

Reset acceptable
Display position

controllable
Each active edge of
HS, VS must be more
than 1tCYC.
Refer to Figure 8.

Refer to Figure 8.

The monitor point in
Figure 11 is 1/2 V

DD

.

6. A/D Converter Characteristics at Ta = –30°C to +70°C, VSS = 0 V

Parameter Symbol Pins Conditions Ratings Unit

VDD [V] min typ max
Resolution 4.5 to 5.5 5 bit
Absolute precision (Note 3) 4.5 to 5.5 ±1/4 ±3/4 LSB
Conversion time tCAD 4.5 to 5.5 2 µs

Reference current I

REF

Analog input V
voltage range

Analog port input I
current

AINH

I

AINL

(Note 3) Absolute precision excepts quantizing error (±1/2 LSB).

From Vref selection to
when the result is
produced

AN0 to AN7

AIN

1 bit conversion time
= 2tCYC

(Regulate the ladder
resistor)

= V

V

AIN

DD

V

= V

AIN

SS

4.5 to 5.5 1.0 2.0 mA

4.5 to 5.5 V

SS

V

DD

4.5 to 5.5 1 µA

4.5 to 5.5 –1

V

No. 5583-13/20

LC86P4448

7. Current Drain Characteristics at Ta = –30°C to +70°C , VSS = 0 V

Parameter Symbol Pins Conditions Ratings

VDD [V] min typ max

Current drain I
during basic
operation
(Note 4)

(1) DVDD, AVDD 4.5 to 5.5 25 38 mA

DDOP

•FmCF = 12 MHz or
FmCF =12.08 MHz
when ceramic resonator
oscillation

•FsXtal = 32.768 kHz
when crystal oscillation

•FmLC = 14.11 MHz
LC oscillation

•System clock :
CF oscillation

•Internal RC oscillation stops

I

(2) 4.5 to 5.5 8 16

DDOP

•FmCF = 0 Hz
(when oscillation stops)

•FmLC = 0 Hz
(when oscillation stops)

•FsXtal = 32.768 kHz
when crystal oscillation

•System clock :
LC oscillation

•Internal RC oscillation stops

Current drain I
in HALT mode
(Note 4)

(1) DVDD, AVDD 4.5 to 5.5 5 10 mA

DDHALT

•HALT mode

•FmCF = 12 MHz or

FmCF =12.08 MHz
when ceramic resonator
oscillation

•FmLC = 0 Hz
(when oscillation stops)

•FsXtal = 32.768 kHz
when crystal oscillation

•System clock :
CF oscillation

•Internal RC oscillation stops.

I

(2) DVDD, AVDD 4.5 to 5.5 400 1600 µA

DDHALT

•HALT mode

•FmCF = 0 Hz

(when oscillation stops)

•FmLC = 0 Hz
(when oscillation stops)

•FsXtal = 32.768 kHz
when crystal oscillation

•System clock :
Internal RC

I

(3) DVDD, AVDD 4.5 to 5.5 25 100

DDHALT

•FmCF = 0 Hz
(when oscillation stops)

•FmLC = 0 Hz
(when oscillation stops)

•FsXtal = 32.768 kHz
when crystal oscillation

•System clock :
LC oscillation

•Internal RC oscillation stops

Current drain I
in HOLD mode

DDHOLD

DVDD, AVDD 4.5 to 5.5 0.05 30 µA

•HOLD mode

•All oscillation stops.

(Note 4)

Unit

(Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored.

No. 5583-14/20

LC86P4448

Oscillation types Manufacturer Oscillator C1 C2

12 MHz ceramic resonator Murata CSA12.0MTZ 33 pF 33 pF
oscillation

Kyocera KBR-12.0M 33 pF 33 pF

12 MHz ceramic resonator Murata CSA12.0MTZ021 33 pF 33 pF
oscillation

Kyocera KBR-12.08M 33 pF 33 pF

* Both C1 and C2 must use K rank (±10%) and SL characteristics.

Table 1. Ceramic Resonator Oscillation Guaranteed Constant (main-clock)

Oscillation types L C3 C4

14.11 MHz LC oscillation 4.7 µH 33 pF 45 pF (Trimmer)

4.7 µH±10% 33 pH 33 pH
(Variable)

* See Figures 11 and 12.

Table 2. LC oscillation Guaranteed Constant (OSD clock)

CST12.0MTW on chip

CST12.0MTW021 on chip

Oscillation types Manufacturer Oscillator C5 C6 Rd

32.768 MHz crystal oscillation Seiko Epson C-002RX 10 pF 10 pF 0 kΩ

* Both C5 and C6 must use a J rank (±5%) and CH characteristics.

For applications which do not require accurate oscillation, use K rank (±10%) with SL characteristics.

Table 3. Crystal Oscillation Guaranteed Constant (sub-clock)

(Notes) • Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation

pins as possible with the shortest possible pattern length.

• If you use other oscillators herein, we provide no guarantee for the characteristics.

• Adjust the voltage of monitor point in Figure 11 to 1/2V

±10% by the LC oscillation constant 'L' or 'C' to lock the PLL

DD

circuit.

CF1 CF2

CFC1 C2

main clock

Figure 1 Ceramic Resonator Oscillation

LC1 LC2

LC3 C4

OSD clock

Figure 2 LC Resonator Oscillation

LC1 LC2

LC3 C4

TX1 TX2

Rd

X'talC5 C6

main clock

Figure 3 Crystal Resonator Oscillation

No. 5583-15/20

Power supply

LC86P4448

V

DD

VDD lower limit
0 V

RES

Internal RC
resonator
oscillation

CF1, CF2

XT1, XT2

Operation mode

HOLD release signal

Reset time

t

msCF

t

ssXtal

Unfixed Reset Instruction execution mode

<Reset time and oscillation stable time.>

Valid

Internal RC
resonator
oscillation

CF1, CF2

XT1, XT2

Operation mode

RES

t

msCF

t

ssXtal

HOLD

Instruction execution mode

<HOLD release signal and oscillation stable time.>

Figure 4 Oscillation Stable Time

VDD

V

DD

RES

R

(Note) Set the values of C

C

RES

reset time is 200 µs or longer.

RES

, R

so that the

RES

Figure 5 Reset Circuit

No. 5583-16/20

LC86P4448

< AC timing point >

t

CKCY

t

CKL

0.5V

DD

t

CKH

V

DD

Serial
clock

Serial
input

Serial
output

t

PIL

(5)

t

CKI

t

CKO

t

ICK

< T iming >

Figure 6 Serial Input/output Test Condition

t

PIL

t

PIH

Figure 7 Pulse Input Timing Condition - 1

t

PIH

1 kΩ

50pF

< Test load >

(5)

HS

VS

0.75V

0.25V

DD
DD

t

PIL

(5)

t

TLH

HS

VS

0.75V

0.25V

t

THL

DD
DD

t

PIH

(5)

more than ±1tCYC more than ±1tCYC

(a) In case of active low (b) In case of active high

Figure 8 Pulse Input Timing Condition - 2

LC86P4448

10 kΩ

HS

HS

2S

C536

Figure 9 Recommended Interface Circuit

No. 5583-17/20

LC86P4448

Noise filter

470 Ω

C-Video

560 pF

2.2 µF

CVIN

Coupling capacitor

Figure 10 CVIN Recommended Circuit

Monitor point

22 kΩ

FILT

+

2.2 µF

1000 pF

-

Figure 11 FILT Recommended Circuit

(Note) • Place the parts connected FILT terminal as close to the FILT as possible with the shortest pattern length on the

board.

VDD = 5.0V

16

16

L = 4.7µH
C = C1 = C2
Ta = 25°C

15

15

14

14

13

13

LC oscillation frequency [MHz] →

012345

012345

FILT [V] →

C = 30pF

C = 30pF

C = 33pF

C = 33pF

C = 36pF

C = 36pF

C = 39pF

C = 39pF

16

15

14

13

LC oscillation frequency [MHz] →

VDD = 5.0V
C1 = C2 = 33pF
Ta = 25°C

012345

FILT [V] →

Figure 12 FILT-LC Oscillation Frequency(1) Figure 13 FILT-LC Oscillation Frequency(2)

L = 4.5µH
L = 4.7µH

L = 4.9µH
L = 5.1µH

No. 5583-18/20

LC86P4448

Requirements Prior to Mounting

Notes on Handling

• The construction of one-time microcontrollers in which the PROM is not programmed precludes Sanyo from fully testing them
before they are shipped. The screening procedure described below is recommended in order to attain higher reliability after
programming the PROM.

• The nature of one-time microcontrollers in which the PROM is not programmed precludes us from fully testing them by writing
all of the bits. Therefore, it is not possible for us to guarantee a write yield of 100%.

• Storage in moisture-proof packaging (unopened)
While they are still in the moisture-proof packaging, these devices should be stored at a temperature of 30˚C and a humidity of
no more than 70%.

• After opening the moisture-proof packaging
These devices should be mounted and soldered as soon as possible after the moisture-proof packaging is opened. Once the
moisture-proof packaging is opened, the devices should be stored at a temperature of 30˚C and a humidity of no more than 70%
for no more than 96 hours.

a. In the case of models that are programmed by the user (models that are shipped with the PROM not programmed)

DIP model

Programming/verification

Recommended screening procedure

Exposure to high temperature without power
150 ±5˚C, 24 hours

Confirmation that program can be read

b. Requirements prior to mounting for models that are programmed by Sanyo (models that are shipped with the PROM

already programmed)

DIP model

+1
–0

Mounting

Mounting

No. 5583-19/20

LC86P4448

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.

SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.

In the event that any or all SANYO products(including technical data,services) described or
contained herein are controlled under any of applicable local export control laws and regulations,
such products must not be exported without obtaining the export license from the authorities
concerned in accordance with the above law.

No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co. , Ltd.

Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.

Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.

This catalog provides information as of February, 1998. Specifications and information herein are subject to change without notice.

No. 5583-20/20

PS