3. Bank address output: Use normal I/O ports as bank address output by program control.
- External prog ram memory access fu nction
External program memory space: 64K bytes
Internal/external program can be switched by program. (at initial: internal program operation mode)
Enabling/ disabling of switching from external program to internal program is provided.
- External data memory access function
By LDC instruction execution:
External data memory space: 64K bytes
(Use normal I/O ports as bank address output by program control.)
1. When internal program is operating:
Access to the internal or external ROM data is selectable by program.
2. When external program is operating:
Only the external ROM data can be accessed.
(Only the external program memory space (64K bytes) can be referred.)
- External RAM memory access function (Able to be used when internal program is executed)
By LDX instruction/STX instruction execution:
External RAM space: 64K bytes (Use normal I/O ports as bank address output by program control.)
(When using the external RAM space in the external program operation mode, refer to the “LC868364 User’s Manual”
for details.)
- Graphic display
A maximum of 1,024 dots capability (without external segment driver)
32 × 80 dots display capability per each segment driver (LC868920A) can be expanded, when 1/32 duty is selected.
Note: If the display capability is expanded by the LC86920A when 1/16 du ty is selected, only S1-S32 of the LC868364 A can be
used, and S33-S48 can not be used. (Refer to the LC 868920A specification sheet.)
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LC868364A
- LCD contrast
LCD display contrast is changeable by program.
- LCD power supply (max. 6V): externally boosted output terminal
(assigned at P40 termina l, The terminal fu nction is selec table by program.)
- LCD driver
Following two kinds of combination can be switched by mask option.
Generates an overflow every 500ms for a clock application. (using a 32.768kHz crystal oscillation for the base timer
clock.)
Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler
output of Timer 0.
(9) Buzzer Output
- Built-in 4kHz and 2kHz buzzer generation function
(10) Remote Receiver Circuit (shares with P73/INT3/T0IN terminal)
- Noise re jection function
- Polarity switch function
(11) Watchdog Timer
- External RC circuit is required (connected to P70/INT0 terminal)
- Interrupt or system reset is activated when the timer overflows.
6. Timer T1L (lower 8 bits of Timer 1), Timer T1H (upper 8 bits of Timer 1)
7. Serial interface SIO0
8. Serial interface SIO1
9. Port 0 or Port 3
- Built-in Interrupt Priority Control
Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. Low or high
priori ty can be assig ned to the 11 inter rupt sour ces, fro m the extern al interr upt INT2 , Timer /Counter T0L (T imer 0,
lower 8 bits) to Port 0 or Port 3. For the external interrupt INT0 and INT1, low or highest priority can be set
regardless of the interrupt priority register.
(13) Sub-routine Stack Level
- A maximum of 128 levels: (sets stack inside RAM)
(14) Multiplication/Division Instru cti on
- 16 bits × 8-bit (7 instruction-cycle-times)
- 16 bits ÷ 8-bit (7 instruction-cycle-ti mes)
(15) Three Types of Oscillation Circuit
- Built-in/external RC oscillation circuit used for the system clock
- CF oscillation circuit used for the sy s tem clock
- Xtal oscillation circuit used for the clock, system clock and LCD
* Crystal oscillation clock is also used as LCD display base clock. T he current consumption of this microcontroller
becomes smaller than the Sanyo’s previous microcontrollers by this configuration.
Built-in/external RC oscillation circuit: switched by mask option
(16) Standby Function
- HALT mode
In this operation mode, the program execution is stopped. The mode can be released by a system reset or an
interrupt request.
- HOLD mode
The HOLD mode is used to stop the oscillations;
CF, RC, and Xtal oscillations. This mode can be released by the following conditions:
• System reset
• Feed the selected level to INT0 or INT1 terminals.