SANYO LC866528A, LC866524A, LC866548A Datasheet
Ordering number : ENN*6700
Preliminary
Overview
- CPU : Operable at a minimum bus cycle time of 0.5µs (microsecond)
- On-chip ROM maximum capacity : 48K bytes
- On-chip RAM capacity : 1152 bytes (LC866548A/40A/32A)
: 896 bytes (LC866528A/24A)
- VFD automatic display controller/driver
- 16-bit timer/counter (or tw o 8-bit tim ers )
- 16-bit timer/ PWM (or two 8-bit timers)
- 8-channels × 8 bit AD Converter
- Two 8-bit synchronous serial -interface circuits (1-channel × 16 bit, 1-channel × 8 bit)
- 14-sour ce 10-vec tored in terrupt s ystem
All of the above functions are fabricated on a single chip.
Features
(1) Read Only Memory (ROM) : LC866548A 49152 × 8 bits
: LC866540A 40960
: LC866532A 32768
: LC866528A 28672
: LC866524A 24576
CMOS IC
LC866548/40/32/28/24A
8-Bit Single Chip Microcontroller
8 bits
×
8 bits
×
8 bits
×
8 bits
×
Ver.1.05
71896
91400 RM (IM) SK No.6700-1/21
LC866548/40/32/28/24A
(2) Random Access Memory (RAM) : LC866548A/40A/32A 1152 × 8 bits
LC866528A/24A 896
8 bits
×
(3) Bus Cycle Time / Instruction Cycle Time
The bus cycle time indicates the speed to read ROM.
Bus cycle time Cycle time Cl ock divider System clock oscillation Oscillation Frequency Voltage
0.5µs 1µs 1/1 Ceramic resonator oscillation 6MHz 4.5 - 6.0V
2µs 4µs 1/2 Ceramic resonator oscillation 3MHz 4.5 - 6.0V
7.5µs 15µs 1/2 RC resonator oscillation 800MHz 4.5 - 6.0V
183µs 366µs 1/2 Crystal oscillation 32.768kHZ 4.5 - 6.0V
Note : External resisters (Rf, Rd) are required when X’ tal oscillation is used.
(4) Ports
- Input/output ports : 3 ports (16 terminals : port 1, 7, 8)
Input/output port programmable in a bit
- 15V withstand Input/output ports : 2 ports (16 terminals)
Input/output port programmable nibble unit : 1 port (8 terminals : port 0)
(When the N-channel open drain output is selected, the data in a bit can be inputted.)
Input/output port programmable in a bit : 1 port (8 terminals : port 3)
- Input port : 2 ports (6 terminals : port 7, 8)
- VFD output port : 52 terminals
Large current output for digit : 16 terminals
Pull-down resistor option available
- Other function
Input/output port : 2 ports (12 terminals : port F, G)
Input port : 3 ports (24 terminals : port C, D, E)
(5) VFD automatic display controller
- Segment/digit output pattern programmable
Any segment/digit combination available
VFD parallel-drive available
- 16-step dimmer function available
(6) AD converter
- 8-channels × 8-bit AD converter
(7) Serial interface
- 1-channel × 16-bit serial interface circuits
- 1-channel × 8-bit serial interface circuits
- LSB first/MSB first function available
- Internal 8-bit baud-rate generator in common with two serial interface circuits
- SIO automatic transmission available (2-32 byte data can be transmitted with program automatically and
continuously.)
No.6700-2/21
LC866548/40/32/28/24A
(8) Timers
- Timer 0 : 16-bit timer/counter with 2-bit prescaler + 8-bit programmable prescaler
Mode 0 : Two 8-bit timers with programmable prescaler
Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter
Mode 2 : 16-bit timer with a programmable prescaler
Mode 3 : 16-bit counter
CYC
The resolution of Timer is t
CYC : cycle time)
. (t
- Timer 1 : 16-bit timer/PWM with
Mode 0 : Two 8-bit timers
Mode 1 : 8-bit timer + 8-bit PWM
Mode 2 : 16-bit timer
Mode 3 : Variable-bit PWM (9-16 bits)
In Mode 0 and Mode 1, the resolution of Timer and PWM is t
In Mode 2 and Mode 3, the resolution of Timer and PWM selectable : t
CYC
.
or 1/2tCYC by prog ram
CYC
- Base timer
Every 500ms overflow system for a clock application (using 32.768kHz crystal oscillation for Base timer
clock)
Every 976
s, 3.9ms, 15.6ms, 62.5ms overflow system (using 32.768kHz crystal oscillation for Base timer
µ
clock)
The Base timer clock selectable ; 32.768kHz crystal oscillation, System clock, and programmable prescaler
output of Timer 0
(9) Buzzer output
- The Buzzer sound frequency selectable ; 4kHz, 2kHz (using 32.768kHz crystal oscillation for Base timer clock)
(10) Remote control receiver circuit (connected to the P73/INT3/T0IN terminal)
- Noise rejection function (the time constant of noise rejection filter : 1tCYC/16tCYC/64tCYC)
(tCYC : instruction cycle time)
- Polarity switching
(11) Watchdog timer
- The watchdog timer is taken on RC outside
- Watchdog timer operation selectable : interrupt system, system reset
(12) Interrupt system
- 14-sourc e 10-vectored inte rrupts :
1. External Interrupt INT0 (include watchdog timer)
2. External Interrupt INT1
3. External Interrupt INT2, Timer/counter T0L (Lower 8 bits)
4. External Interrupt INT3, base timer
5. Timer/counter T 0H (Upper 8 bits)
6. Timer T 1H / T1L
7. Serial interface SIO0
8. Serial interface SIO1
9. AD converter
10. VFD automatic display controller, Port 0
- Built-in Interrupt priority control register
Microcontroller allows 3 levels of interrupt ; low level, high level, and highest level of multiplex interrupt. It can
specify a low level or a high level interrupt priority from INT2/T0L through port 0 (i. e. the above interrupt
number fro m three thro ugh ten). I t can also spe cify a low leve l or the high est level in terrup t priori ty to INT 0 and
INT1.
(13) Subroutine stack levels
- 128 levels (Max.) : Stack area included in RAM area
No.6700-3/21
LC866548/40/32/28/24A
(14) Multiplication and division
- 16 bit × 8 bit (7 instruction cycle times)
- 16 bit ÷ 8 bit (7 instruction cycle times)
(15) Three oscillation circuits
- On-chip RC oscillation circuit used for the system clock
- On-chip CF oscillation circuit used for the system clock
- On-chip Crystal oscillation circuit used for the system clock and for time-base clock
Note : External resisters (Rf, Rd) are required
(16) Standby function
- HALT mode function
The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped.
This operation mode can be released by the interrupt request signals or the initial system reset request signal.
- HOLD mode function
The HOLD mode is used to stop all the oscillations ;
RC (internal), CF and Crystal oscillations. This mode can be released by the following operations.
• Reset terminal (
RES
) set to low level.
• Input a assigned level to P70/INT0/T0I N or P 71/INT1/T0IN terminal.
• Input a Port0 interrupt condition.
(17) Factory shipment
QFP100E delivery form
(18) Development Tools
- Evaluation chip : LC866094
- EPROM version : LC86E6548
- One time version : LC86P6548
- Emulator : EVA86000 + ECB866500 (Evaluation chip board) + POD866500 (P od)
• Notes for use
Follow the unde r table.
Frequency range of the system clock Voltage range Clock Divider Note
15kHz to 3MHz 1/1 Can no t use 1/2 divider
30kHz to 6MHz 1/1, 1/2
Internal RC oscillation
4.5V to 6.0V
1/1, 1/2
No.6700-4/21
Pin Assignment QIP100E
Z
N
N
S47/PF7
S46/PF6
S45/PF5
S48/PG0
S49/PG1
S50/PG2
S51/PG3
P00
P01
P02
P03
VSS2
VDD2
P04
P05
P06
P07
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
8079787776757473727170696867666564636261605958575655545352
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1 2 3 4 5 6 7 8 9
P30
P16/BUZ
P17/PWM0
Package Dimension
(unit : mm)
3151
LC866548/40/32/28/24A
S44/PF4
S43/PF3
S42/PF2
S41/PF1
S40/PF0
VDD4
S39/PE7
S38/PE6
S37/PE5
S36/PE4
S35/PE3
S34/PE2
S33/PE1
S32/PE0
S31/PD7
S30/PD6
S29/PD5
S28/PD4
S27/PD3
S26/PD2
S25/PD1
S24/PD0
S23/PC7
S22/PC6
S21/PC5
S20/PC4
VP
51
50
S19/PC3
49
S18/PC2
48
S17/PC1
47
S16/PC0
46
VDD3
45
S15/T15
44
S14/T14
43
S13/T13
42
S12/T12
41
S11/T11
40
S10/T10
39
S9/T9
38
S8/T8
37
S7/T7
36
S6/T6
35
S5/T5
34
S4/T4
33
S3/T3
32
S2/T2
31
S1/T1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P31
P32
P33
P34
P35
P36
P37
RES
P70/INT0
CF1
CF2
VSS1
XT1/P74
XT2/P75
VDD1
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
S0/T0
P71/INT1
P72/INT2/T0I
P72/INT3/T0I
SANYO : QIP-100E
No.6700-5/21
System Block Diagra m
LC866548/40/32/28/24A
Interrupt Control
IR
PLA
Base Timer
SIO0
SIO1
Timer 0
Standby Contr ol
CF
RC
X’tal
Clock
Generator
Bus Interface ACC
Port 1
Port 3
Port 7
ROM
PC
B Register
C Register
ALU
Timer 1
ADC
INT0 to 3
Noise Filtter
SI0 Automatic
transmission
RAM
128 bytes
VFD Controller
High Voltage Output
Port 8
PSW
RAR
RAM
Stack Pointer
Port 0
Watch dog Timer
No.6700-6/21
LC866548/40/32/28/24A
LC866548A/40A/32A/28A/24A Pin Description
Pin Name I/O Function Description Option
VSS1, 2 Power pin (-) *1
VDD1,2,3,4 Power pin (+) *1
VP Power pin (+) for the VFD output pull-down resist
Port 0
P00 - P07
Port 1 •8-bit Input/output port
P10 - P17
Port 3
P30 - P37
Port 7 •4-bit input/output port
P70 - P73
P74
- P75
Port 8
P80 - P83
P84 - P87
S0/T0 to
S6/T6
I/O •8-bit input/output port
Input/output in nibble units
•Input for port 0 interrupt
•Input for HOLD release
•15V withstand at N-channel open drain output
I/O
Input/output can be specified in bit unit.
•Other pin functions
P10
I/O •8-bit input/output port
Input/output in bit unit
•15V withstand at N-channel open drain output
I/O
Input/output in bit unit
I
•2-bit input port
•Other pin function
P70
•Interrupt recei ved form, vector address
rising falling rising/
INT0
INT1
INT2
INT3
•4-bit input/output port
I
Input/output in bit unit
I/O
•4-bit input port
•Other function
AD input port (8 port pins)
O Output for VF D display controller
segment/timing in common
SIO0 data output
P11
SIO0 data input/bus input/output
P12
SIO0 clock input/output
P13
SIO1 data output
P14
SIO1 data input/bus input/output
P15
SIO1 clock input/output
P16
Buzzer output
P17
Timer1 output (PWM0 output)
INT0 input/HOLD release /Nch-Tr.
output for watchdog timer
P71
INT1 input/HOLD release input
P72
INT2 input/timer 0 event input
P73
INT3 input with noise filter/timer 0
event input
P74
Input pin XT1 for 32.768kHz crystal
resonator oscillation
P75
Output pin XT2 for 32.768kHz
crystal resonator oscillation
enable
enable
enable
enable
enable
enable
enable
enable
falling
disable
disable
enable
enable
H level L level Vector
enable
enable
disable
disable
•Pull-up resistor :
Provided/Not provided (each nibble)
•Output form :
CMOS/N-channel open drain
(each bit)
•Output form :
CMOS/N-channel open drain
(each bit)
•Output form :
CMOS/N-channel open drain
(each bit)
enable
enable
disable
disable
Pull-down resistor :
Provided/Not provided (each bit)
03H
0BH
13H
1BH
(continue)
No.6700-7/21
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