SANYO LC866448B, LC866444B, LC866436B, LC866432B, LC866420B Datasheet

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Ordering number : ENN*6699

CMOS IC

LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B

8-Bit Single Chip Microcontroller

Preliminary Overview

The LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B microcontrollers are 8-bit single chip microcontrollers with the following on-chip functional blocks:

- CPU : Operable at a minimum bus cycle time of 0.5µs (microsecond)

- On-chip ROM Maximum Capacity : 48K bytes

- On-chip RAM Capacity : 1152/768/640/512 bytes (LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B)

- 16-bit timer /counter (or two 8-bit timers)

- 16-bit timer /PWM (or two 8-bit timers)

- 8-channel × 8-bit AD converter

- Two 8-bit synchronou s serial- interface circuits (1-channel × 16bit, 1-channel × 8bit)

- 14-sour ce 10-vectored interr upt system

All of the above functions are fabricated on a single chip.

Ver.1.05 O0499

91400 RM (IM) SK No.6699-1/21

LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B

Features

(1) Read-Only Memory (ROM) : LC866448B 49152 × 8 bits : LC866444B 45056 × 8 bits : LC866440B 40960 × 8 bits : LC866436B 36864 : LC866432B 32768 : LC866428B 28672 × 8 bits : LC866424B 24576 × 8 bits : LC866420B 20480 : LC866416B 16384 : LC866412B 12288 × 8 bits : LC866408B 8192 × 8 bits (2) Random Access Memory (RAM) : LC866448B/44B/40B/36B 1152 × 8 bits : LC866432B/28B/24B 768 : LC866420B/16B 640 × 8 bits : LC866412B/08B 512 × 8 bits (3) Bus Cycle Time/Instruction Cycle Time

The LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B are constructed to read ROM twice within one

instruction cycle. It has 1.7 times more performance capability within the same instruction cycle compared to our 4-bit microcomputers (LC66000 series). Bus cycle time indicates the speed to read ROM.

Bus cycle time Cycle time Clock divider System clock oscillation Oscillation Freq uency Voltage

0.5µs 1µs 1/1 Ceramic resonator oscillation 6MHz 4.5V to 6.0V 2µs 4µs 1/1 Ceramic resonator oscillation 3MHz 2.5V to 6.0V

7.5µs 15µs 1/1 RC resonator oscillation 800kHz 2.5V to 6.0V

183µs 366µs 1/2 Crystal oscillation 32.768kHz 2.5V to 6.0V

(4) Ports

- Input/output ports : 1 port (8 terminals : port 1) Input/output programmable in a bit

- 15V withstand Input/Output ports : 2 ports (12 terminals) Input/output port programmable in nibble unit : 1 port (8 terminals : port 0) (When the N-channel open drain output is selected, the data in a bit can be inputted.) Input/output port programmable in a bit : 1 port (4 terminals : port 3)

- Input port : 2 ports (14 terminals : port 7,8)

- VFD output port : 38 terminals Large current output for digit : 16 terminals Pull-down resistor option available

- Other function Input/output port : 1 port (6 terminals : port E) Input port : 2 ports (16 terminals : port C,D)

(5) VFD automatic dislay controller

-Segment/digit output pattern programmable

Any segment/digit combination available VFD parallel-drive available

- 16-step dimmer function available

(6) AD converter

- 8-channel × 8-bit AD converter

(7) Serial-interface

- 1 channel × 16-bit serial-interface circuits

- 1 channel × 8-bit serial-in terface circuits

- LSB first / MSB first function available

- Internal 8-bit baud-rate generator in common with two serial-interface circuits

8 bits

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LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B

(8) Timer

- Timer 0 16-bit timer/counter 2-bit prescaler + 8-bit programmable prescaler

Mode 0 : Two 8-bit timers with programmable prescaler Mode 1 : 8-bit timer with programmable prescaler + 8-bit counter Mode 2 : 16-bit timer with programmable prescaler Mode 3 : 16-bit counter

The resolution of Timer is tCYC. (tCYC: cycle tim e)

- Timer 1 16-bit timer/PWM

Mode 0 : Two 8-bit timers Mode 1 : 8-bit timer + 8-bit PWM Mode 2 : 16-bit timer Mode 3 : Variable-bit PWM (9-16 bits)

In Mode 0 and Mode 1,the resolution of Timer and PWM is tCYC. In Mode 2 and Mo de 3, the resolution of Ti mer and PWM se l e c table: tCYC or 1/2 tCYC by progra m

- Base timer Every 500ms overflow system for a clock application (using 32.768kHz crystal oscillation for Base timer clock) Every 976µs, 3.9ms, 15.6ms, 62.5ms overflow system (using 32.768kHz crystal oscillation for Base timer clock) The Base timer clock selectable; 32.768kHz crystal oscillation, System clock, and programmable prescaler output of Timer 0

(9) Buzzer output

- The Buzzer sound frequency selectable; 4KHz, 2KHz (using 32.768kHz crystal oscillation for Base

timer clock)

(10) Remote-control receiver circuit (Shares with the P73/INT3/T0IN terminal)

- Noise Rejection function (the time constant of noize rejection filter: 1tCYC/16tCYC/64tCYC)

(tCYC: instruction cycle time)

- Switch Polarity functi on

(11) Watchdog timer

- The watchdog timer is taken on RC outside

- Watchdog timer operation selectable: interrupt system, system reset

(12) Interrupt system

- 14-sourc e 10-vec tored in terrupts :

1. External interrupt INT0 (include watchdog timer)

2. External interrupt INT1

3. External interrupt INT2, Timer/counter T0L (Lower 8-bit)

4. External interrupt INT3, Base timer

5. Timer/counter T0H (Up p er 8-bit)

6. Timer T1L, Timer T1H

7. Serial-interface SIO0

8. Serial-interface SIO1

9. AD converter

10. VFD automatic display controller, Port 0

- Built-i n I nterrup t Priority control registe r Microcontroller allows 3 levels of interrupt; low level, high level, and highest level of multiplex interrupt. It can specify a low level or a high level interrupt priority from INT2/T0L through port 0

(i.e. the above interrupt number from three through ten). It can also specify a low level or the highest level interrupt priori ty to INT0 and INT1.

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LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B

(13) Real-time service operation

The Real-Time Service (RTS) functions the 4-byte data-transfer between the Special Function Registers at acknowledging the interrupt request. The RTS starts within 1 instruction cycle-time and completes within 5 instructions cycle-time after occurring the interrupt request.

(14) Subroutine stack levels

- 128 levels (Max.): Stack area included in RAM area

(15) Multiplication and division

16-bit × 8-bit (7 instruction cycle times) 16-bit / 8-bit (7 instruction cycle times)

(16) Three oscillation circuits

- On-chip RC oscillation circuit using for the system clock.

- On-chip CF oscillation circuit using for the system clock.

- On-chip crystal oscillation circuit using for the system clock and for time-base clock.

(17) Standby function

- HALT mode function The HALT mode is used to reduce power dissipation. In this operation mode, program execution is stopped. This operation mode can be released by interrupt request signals or the initial system reset request signal.

- HOLD mode function The HOLD mode is used to freeze all the oscillations; RC (internal), CF and Crystal oscillations. This mode can be released by the following operations.

• Reset terminal (

• P70/INT0/T0IN, P71/INT1/T0IN terminals set to assigned level (programmable)

• Input a Port 0 interrupt condition

(18) Factory shipment

• QFP80E delivery form

(19) Development support tools

Evaluation (EVA) chip : LC866097 EPROM version : LC86E6449 One time version : LC86P6449 Emulator : EVA-86000 + ECB866400 (Evaluation chip board) + POD866400 (P OD)

Notice for use

1. Set VDD=4.0V to 6.0V at using S16 to S37 as input port.

2. Follow the under table.

Frequency range of the system clock Voltage range Clock Divider

RES ) set to Low level

15kHz to 30kHz 1/1 Can not use 1/2 divider 30kHz to 6MHz 15kHz to 30kHz 1/1 Can not use 1/2 divider

30kHz to 1. 5MHz 1/1,1/2

1.5MHz to 3MHz

4.5V to 6.0V 1/1,1/2

2.5V to 6.0V

1/2 Can not use 1/1 divider

4.5V to 6.0V 1/1,1/2 Internal RC oscillation

2.5V to 6.0V 1/2 Can not use 1/1 divider

Note

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Pin Assignment

QIP80E

P00 P01 P02 P03 P04 P05 P06 P07

VSS2

P10/SO0

P11/SI0/SB0

P12/SCK0

P13/SO1

P14/SI1/SB1

P15/SCK1

P16/BUZ

Package Dimension

(unit : mm)

3174

LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B

S37/PE5

S36/PE4

S35/PE3

S34/PE2

S33/PE1

S32/PE0

S31/PD7

S30/PD6

S29/PD5

S28/PD4

S27/PD3

S26/PD2

S25/PD1

S24/PD0

S23/PC7

S22/PC6

S21/PC5

S20/PC4

S19/PC3

S18/PC2

S17/PC1

S16/PC0

VDD2

42 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

1 2 3 4 5 6 7 8 9

P30

P31

P32

P33

P17/PWM0

P70/INT0

15 1617

CF1

RES

XT1/P74

CF2

VSS1

XT2/P75

VDD1

P80/AN0

P81/AN1

P82/AN2

P83/AN3

P84/AN4

P85/AN5

P86/AN6

P87/AN7

P71/INT1

P73/INT3/T0I

P72/INT2/T0I

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

S15/T15 S14/T14 S13/T13 S12/T12 S11/T11 S10/T10 S9/T9 S8/T8 S7/T7 S6/T6 S5/T5 S4/T4 S3/T3 S2/T2 S1/T1 S0/T0

SANYO : QIP-80E

No.6699-5/21

LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B

System Bl ock Diagram

Base Timer

SIO0

SIO1

Timer 0

Timer 1

ADC

INT0 to 3

Noise Filtter

Real Time Service

RAM

(128 bytes)

VFD Controller

High voltage Output

Interrupt Control

Standby Control

X’tal

Clock

Generator

Bus Interface ACC

Port 1

Port 3

Port 7

Port 8

B Register

C Register

Stack Pointer

Watchdog T i mer

PLA

ROM

ALU

PSW

RAR

RAM

Port 0

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LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B

Pin descriptio n

Pin name I/O Function description Option VSS1,2 - Power pin (-) Short-circuit VSS1 to VSS2. VDD1,2 - Power pin (+) *1 Refer to Notes VP - Power pin (+) for the VFD output pull-down resistor PORT0

P00 to P07

PORT1 P10 to P17

PORT3 P30 to P33

PORT7

P70

P71 to P75

I/O •8-bit input/output port

•Input for port 0 interrupt

•Input/output in nibble units

•Input for HOLD release

•15V withstand at N-channel open drain output

I/O •8-bit input/output port

•Input/output can be specified in a bit unit

•Other pin fun c tion s P10 SIO0 data output P11 SIO0 data input/bus input/output P12 SIO0 clock input/output P13 SIO1 data output P14 SIO1 data input/bus input/output P15 SIO1 clock input/output P16 Buzzer output P17 Timer 1 output (PWM0 output)

I/O •4-bit input/output port

•Input/output in bit unit

•15V withstand at N-channel open drain output

•6-bit input port

•Other pin functions P70 : INT0 i nput/HOLD release/N-channel Tr.

I/O

output for watchdog timer P71 : INT1 input/HOLD release input P72 : INT2 input/timer 0 event input P73 : INT3 input with noise filter/timer 0 event input

P74

: 32.768kHz cry s ta l oscillation term inal XT1

P75 : 32.768kHz crystal oscillation terminal XT2

•Interrupt recei ved forms, the vector addresses

high

level

rising falling rising

falling INT0 enable enable disable enable enable 03H INT1 enable enable disable enable enable 0BH INT2 enable enable enable disable disable 13H INT3 enable enable enable disable disable 1BH

low

level

Continue.

•Pull-up resistor : Provided/Not provid ed (each nibble)

•Output form : CMOS/N-channel open drain (each bit)

Output form : CMOS/N-channel open drain (each bit)

Pull-up resistor : Provided/Not provided (P70,71,72,73)

P74

, P75 don’t have the pull-up

resistor option.

vector

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