SANYO LC8220 Datasheet
Overview
The LC8220 JPEG LSI implements digital still image
compression and decompression conforming to the JPEG
(Joint Photographic Expert Group) standard. The LC8220
includes the baseline system of the ISO 10918 (JPEG)
standard, and requires no external components to construct
an application that performs JPEG compliant
compression/decompression.
Features
• Conforms to the ISO 10918-1 baseline system
• Four quantization tables and four Huffman tables (two
for AC and two for DC) are built in.
• Hardware support for JPEG marker codes
• Built-in bidirectional YUV - RGB converter
• Many color component sampling ratios are supported.
(e.g., YUV 4:1:1 and YMCK 1:1:1:1, etc.)
• Level shift function that can be defined for each
component
• Built-in dual buffers for reduced data transfer load
• Bus sizing function that allows direct connection to 8-,
16-, and 32-bit busses
• Endian control function
• Three independent data buses
Package Dimensions
unit: mm
3153A-QFP160
CMOS LSI
32896HA (OT)/D1694TH (OT) No. 4909-1/13
Preliminaly
SANYO: QFP160
[LC8220]
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
JPEG Still Color Image
Compression/Decompression LSI
LC8220
Ordering number : EN*4909A
No. 4909-2/13
LC8220
Block Diagram
The LC8220 has three independent buses.
Pin Assignment
No. 4909-3/13
LC8220
Pin Functions
Pin No. Symbol I/O Function
1 V
SS
— Ground
2 CTLCS I Control bus chip select
*2
3 CTLRD I Control bus read request
*3
4 CTLWR I Control bus write request
*4
5 CTLRDY O Control bus ready for read/write requests
*5
6 CTLERR O Error interrupt request
7 CTLINT O Control bus interrupt request
8 CPUCTL I Connected CPU type setting for the control bus
*1
9 CTLSIZE I Bus width selection for the control bus (0: 8 bits, 1: 16 bits)
10 V
DD
— +5 V power supply
11 V
SS
— Ground
12 CTLA7 I
13 CTLA6 I
14 CTLA5 I
15 CTLA4 I
Control address bus
16 CTLA3 I
17 CTLA2 I
18 CTLA1 I
19 CTLA0 I
20 V
DD
— +5 V power supply
21 V
SS
— Ground
22 CTLD15 I/O
23 CTLD14 I/O
24 CTLD13 I/O
25 CTLD12 I/O
Control data bus (D15 to D8 are unused if an 8-bit CPU is used.
*7
)
26 CTLD11 I/O
27 CTLD10 I/O
28 CTLD9 I/O
29 CTLD8 I/O
30 V
DD
— +5 V power supply
31 V
SS
— Ground
32 CTLD7 I/O
33 CTLD6 I/O
34 CTLD5 I/O
35 CTLD4 I/O
Control data bus
36 CTLD3 I/O
37 CTLD2 I/O
38 CTLD1 I/O
39 CTLD0 I/O
40 V
DD
— +5 V power supply
41 V
SS
— Ground
42 CLK I System clock
43 CLKSEL I Clock divisor selection (0: no divisor, 1: divisor used)
*6
44 RESET I System reset
45 TEST I Test mode selection (0: normal operation, 1: test mode)
*6
46 TESTOUT O Test result output
*8
47 MDD10 I/O
48 MDD9 I/O Test mode data bus
*7
49 MDD8 I/O
50 V
DD
— +5 V power supply
51 V
SS
— Ground
52 MDD7 I/O
53 MDD6 I/O Test mode data bus
*7
54 MDD5 I/O
Continued on next page.
No. 4909-4/13
LC8220
Continued from preceding page.
Pin No. Symbol I/O Function
55 MDD4 I/O
56 MDD3 I/O
57 MDD2 I/O Test mode data bus
*7
58 MDD1 I/O
59 MDD0 I/O
60 V
DD
— +5 V power supply
61 V
SS
— Ground
62 TESTI1 I
63 TESTI2 I
64 TESTI3 I Test mode input pins
*9
65 TESTI4 I
66 TESTI5 I
67 TESTO1 O
Test mode output pins
*8
68 TESTO2 O
69 TESTI6 I Test mode input pin
*9
70 TESTO3 O Test mode output pin
*8
71 CPUPX I Connected CPU type setting for the pixel bus
*1
72 PXCS I Pixel bus chip select
*2
73 PXRD I Pixel bus read request
*3
74 PXWR I Pixel bus write request
*4
75 PXRDY O Pixel bus ready for read/write requests
*5
76 PXINT O Pixel bus interrupt request
77 PXRLS I Pixel bus interrupt release
78 PXEND O Pixel bus last data output indicator
79 (NC) —
80 V
DD
— +5 V power supply
81 V
SS
— Ground
82 PXD31 I/O
83 PXD30 I/O
84 PXD29 I/O
85 PXD28 I/O
Pixel data bus
86 PXD27 I/O
(D31 to D16 are unused if a 16-bit CPU is used and D31 to D8 are unused if an 8-bit CPU is used.
*7
)
87 PXD26 I/O
88 PXD25 I/O
89 PXD24 I/O
90 V
DD
— +5 V power supply
91 V
SS
— Ground
92 PXD23 I/O
93 PXD22 I/O
94 PXD21 I/O
95 PXD20 I/O
Pixel data bus
96 PXD19 I/O
(D31 to D16 are unused if a 16-bit CPU is used and D31 to D8 are unused if an 8-bit CPU is used.
*7
)
97 PXD18 I/O
98 PXD17 I/O
99 PXD16 I/O
100 V
DD
— +5 V power supply
101 V
SS
— Ground
102 PXD15 I/O
103 PXD14 I/O
104 PXD13 I/O
105 PXD12 I/O
Pixel data bus
106 PXD11 I/O
(D31 to D16 are unused if a 16-bit CPU is used and D31 to D8 are unused if an 8-bit CPU is used.
*7
)
107 PXD10 I/O
108 PXD9 I/O
109 PXD8 I/O
Continued on next page.
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