SANYO LC82151 Datasheet
CMOS LSI
No. *5601
Preliminary
Overview
The LC82151 is a facsimile controller that integrates the
main functions required by facsimile systems on a single
chip. The LC82151 includes a FAX modem with ADPCM
and HDLC functions, image processing functions that can
create high-quality binary image data without external
memory, a CODEC accelerator, a CPU and CPU
peripheral circuits, general-purpose I/O ports, and other
functions. A facsimile system with excellent costperformance characteristics can be created easily by
providing ROM and RAM.
Functions
• CPU and peripheral circuits
– High-speed 16-bit CPU (65C816) operating at
7.4 MHz
– 16-MB program address space
– CODEC accelerator
– Two-channel DMA controller
– Four 16-bit timers
– 16-bit watchdog timer
– TPH interface
– Serial I/O interface
– Parallel I/O: 10 to 43 pins
• Image processing
– Processes 2048 pixels per line
– Processing speed: 540 ns per pixel (maximum)
– Built-in 8-bit A/D converter (Includes a sensor signal
delay function.)
– Sensor drive circuit (Supports CCDs and all major
CIS devices.)
– Distortion correction (White distortion: 8-pixel
averaging correction, black correction: Allows the
black correction subtraction data to be set.)
– γ-correction (Supports user-defined correction curves.)
– Simple binary conversion processing (fixed threshold
and density-adaptive threshold)
– Halftone processing error diffusion method (64 levels)
– Image reduction (decimation, fine black line retention,
and fine white line retention)
LC82151
Single-Chip Facsimile Controller
• Modem
– Group 3 FAX modem
ITU-T V.29 (9600, 7200, and 4800 bps)
ITU-T V.27ter (4800 and 2400 bps)
ITU-T V.21ch2 (300 bps)
– Simultaneous high/low-speed wait function
– Short training function (ITU-T V.27ter only)
– HDLC function (for all transmission speeds)
– Synthesizer function
– Caller ID function
Bell 202 (1200 bps)
ITU-T V.23 (1200 bps)
– ADPCM function
Encoding: 2, 3, or 4 bits
Sampling frequencies: 9.6, 7.2, 4.8, and 3.6 kHz
– RTC low-voltage backup
– 5-V single-voltage power supply
Package Dimension
unit: mm
3214-SQFP144
[LC82151]
SANYO: SQFP144
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
43097 (OT) No. 5601-1/8
Block Diagram
Ø2, RES, R/W,
IRQ, VP, RDY,
BE, NMI, VPA,
VDA, ABCNT
CPU
65C816
LC82151
AIN, ATAP, TEMP, SH, RS, ACLK1,
ACLK2, ASAMP, DAREFH, DAREFL
Image
processing
PXD7 to PXD0
PDREQ, PDACK
RD, WR
ROMCS, RAMCS,
IOCS, MCS
BREQ, BACK, EXRDY
PA7 to PA0
PB2 to PB0
TO0
TO1
RTC, CTS,
DSR, DTR,
RI, DCD
TD, RD
CPU
interface
PIO
Timer
SIO
WDT
Modem
CODEC
accelerator
RTC
DMAC
Interrupt
controller
TXA, RXA,
PGCO, PGCI, V
RIN, VCOI, PHASEO,
EYED, EYECLK,
EYESYNC
ROSC1
ROSC2
INT2
INT8
REF
,
PCK/SCLK,
PDATA/TXD,
EXCLK,
LATCH/RXD,
STB0 to STB3,
HVON
PROTECT
XTAL1, XTAL2,
XOUT,CLKIN,
RESET,
BACKUP
TEST2 to TEST0
TESTOUT
TPH interface
D7 to D0
A19 to A0
DRAM
controller
RAS
CAS
No. 5601-2/8
LC82151
Pin Assignment
Type
I Input pins B
O Output pins P Power pins
Pin No. Pin I/O Pin function
1V
2
3 RDY O ICE ready signal
4 VPA I ICE valid program address signal
5 VDA I ICE valid data address signal
6 A19 O
7 A18 O
8 A17 O
9 A16 O
10 D7 B
11 D6 B
12 D5 B
13 D4 B
14 D3 B
15 D2 B
16 D1 B
17 D0 B
18 V
19 V
20 RD O Read signal from the CPU
21 WR O Write signal from the CPU
22 ROMCS O Program ROM chip select signal
23 RAMCS O Working RAM chip select signal
24 IOCS O External I/O chip select signal
25 MCS O External I/O chip select signal
26 RAS/PG1 B DRAM row address strobe/general-purpose port G
27 CAS/PG2 B DRAM column address strobe/general-purpose port G
28 PA7 B
29 PA6 B
30 PA5 B
31 PA4 B
32 PA3 B
33 PA2 B
34 PA1 B
35 PA0 B
36 V
37 V
38 RIN I PLL bias input
39 PHASEO O PLL phase detector output
40 VCOI I PLL voltage-controlled oscillator input
41 INT8/PB7 B
42 INT2/PB6 B
43 BACK/PB5 B CPU bus acknowledge signal/general-purpose port B
44 BREQ/PB4 B CPU bus request signal/general-purpose port B
45 EXRDY/PB3 B External ready input/general-purpose port B
46 PB2 B
47 PB1 B General-purpose port B
48 PB0 B
49 NMI I Non-maskable interrupt request signal
50 TEST2 I Test pin
SS
VP
DD
SS
SS
DD
P Ground
I ICE vector address signal
Address bus
Data bus
P Power supply
P Ground
General-purpose port A
P Ground
P Power supply
External interrupt request signal/general-purpose port B
Bidirectional pins
NC No connection
Continued on next page.
No. 5601-3/8
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