Sanyo LC7941YD Specifications

Ordering number: EN 6158

CMOS IC

LC7940YD,7941YD

Dot-matrix LCD Drivers

Overview

The LC7940YD and LC7941YD are segment driver ICs
for driving large, dot–matrix LCD displays. They read 4
bit parallel or serial input, display data from a controller
into an 80–bit latch, and then generate LCD drive signals
corresponding to that data.

The LC7940YD and LC7941YD feature mirror–image pin
assignments, allowing them to be used together to increase
component density. They are designed to be used with the
LC7942YD common driver to drive large LCD panels.

Features

• 80 built–in LCD display drive circuits

• 1/8 to l/128display duty cycle

• Serial or 4–bit parallel data input

• Chip disable for low power dissipation for large–sized
panels

• Bias supply voltags can be supplied externally

• Operating supply voltage and ambient temperature

- 2.7 to 5.5 V logic supply ( VDD) at Ta = –20 to +85°C

- 8 to 20V LCD supply (VDD – VEE ) at Ta = –20 to

+85 °C

• CMOS process

• 100–pin flat plastic package

Package Dimensions

unit: mm

–

3180–QIP100D

0.65

80

81

100

130

17.2

0.575

0.825

0.65

14.0

1.6

[LC7940YD, LC7941YD]

23.2

20.0

0.3

21.6

SANYO : QFP100D (QIP100D)

1.6

51

50

31

2.45max

0.8

0.15

2.15

15.6

0.8

Specifications

Absolute Maximum Ratings at Ta = 25 ± 2°C, V

Parameter Symbol Ratings Unit

Logic supply voltge VDD max –0.3 to +7.0
LCD supply voltage, See Note below. VDD – VEE max 0 to 22
Input voltage VI max –0.3 to VDD + 03

■ Any and all SANYO products described or contained herein do not have specifications that can handle

applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

■ SANYO assumes no responsibility for equipment failures that result from using products at values that

exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

SS

= 0 V

SANYO Electric Co., Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

V
V
V

63099RM (ID) No. 6158—1/11

Parameter Symbol Ratings Unit

Operating temperature range
Storage temperature range

Note

V

≥ V1> V3 > V4 > V

DD

EE

LC7940YD, LC7941YD

T

opr

T

stg

–20 to +85

–40 to +125

°C
°C

Recommended Operating Condltions at Ta =

Parameter Symbol Conditions

Logic supply voltage V
LCD supply voltage VDD – V

HIGH–level input voltage V

LOW–level inpvt voltage V

CP shift clock frequency f
CP pulsewidth t
LOAD pulsewidth t
DIn and SDI to CP setup time t
DIn and SDI to CP hold time t

CP to LOAD time

LOAD to CP time t
CP rise time t
CP fall time t
LOAD rise time t
LOAD fall time t

DD

IH

IL

CP
WC
WL

SETUP

HOLD

t

CL1

t

CL2

LC

R

F
RL
FL

EE

See Notes 1 and 2. 8 – 20
CP, CDl, DI1 to DI3, M,

SDl, P/S, DISPOFF and
LOAD

CP, CDI, Dl1 to DI3, M,
SDl, P/S,DISPOFF and
LOAD

–

20 to + 85°C, V

= 0V

SS

Ratings

min typ max

2.7 – 5.5

Unit

V
V

0.8V

DD

– – 0.2V

100––
100––

80––
80––

0––
100––
100––

––50

––50

––50

––50

––

DD

–3.3

V

V

MHz

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Notes

1. V

≥ Vl > V3 > V4 > V

DD

EE

2. At turn ON, the LCD supply should be energized after or simultaneously with the logic supply. At turn OFF, the logic supply
should be cut after or simultaneously with the LCD supply.

Electrlcai Characterfstlcs at Ta = 25 ± 2°C,V

Parameter Symbol Conditions

HIGH–level input current I

LOW–level input current I

CDO HIGH–level output voltage V
CDO LOW–levef output voltage V

O1 to O80 driver ON resistance RON

IH

IL

OH

OL

= 0V, VDD = 2.7 to 5.5 V

SS

Ratings

min typ max

VIN =VDD; LOAD, CP, CDI,
P/S, DI1 to DI3, SDl, M,

––1

and DISPOFF
VIN = VSS; LOAD, CP, CDl,

P/S, DI1 to DI3, SDI, M,

–––1

and DISPOFF
IOH = –400 µA VDD – 0.4 – –
IOL = 400 µA – – 0.4
VDD – VEE = 18 V,

|VDE – VO|= 0.25 V.

–24

See note

Unit

µA

µA

V
V

kΩ

No. 6158—2/11

LC7940YD, LC7941YD

Parameter Symbol Conditions

CDI = VDD,

VDD to VSS standby supply current I

ST

VDD – VEE = 18 V,
fCP = 3.3 MHz,
no output load ; V

SS

VDD – VEE = 18 V,

VDD to VSS operating supply current I

SS

fCP = 3.3 MHz,
I

= 5.156 kHz,

LOAD

fM = 52 Hz ;VSS
VDD – VEE = 18V,

VDD to VEE operating supply current I

CP input capacitance C

EE

I

fCP = 3.3 MHz,
f

= 5,156 kHz,

LOAD

= 52 Hz ; V

f

M

EE

fCP = 3.3 MHz ; CP – 5 –

Note

V

= V1 or V3, or V4 or VEE, V1 = VDD, V3 = 9/11 × (VDD – VEE), V4 = 2/11 × (VDD – VEE)

DD

Switching Characteristics at Ta = 25 ± 2°C,V

Parameter Symbol Conditions

CDO output delay time t

D

= 0 V, VDD = 2.7 to 5.5 V

SS

CL = 30 pF – – 200

Ratings

min typ max

– – 200

––1.0

––0.1

Ratings

min typ max

Unit

µA

mA

mA

pF

Unit

ns

Switching Characteristics Waveform

t

t

CP

SDI
DI1 to 3

LOAD

CDO

WC

R

t

SET

t

CL (1)

UP

t

t

t

RL

WC

F

t

HOLD

t

CL (2)

t

WL

t

D

t

FL

0.8V

DD

0.2VDD

t

LC

t

D

No. 6158—3/11

Pad Layout (Top view)

080

079

078

077

076

075

LC7940YD, LC7941YD

074

073

072

071

070

069

068

067

066

065

064

063

062

061

060

059

058

057

056

055

054

053

052

051

NC

CDO

NC

DISP OFF

P/S

V
VEE

V4

V3
NC
V

V1

DI1
DI2
DI3

SDI

LOAD

CDI

CP

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

81
82
83
84
85
86

SS

87
88
89
90
91

DD

92
93

M

94
95
96
97
98
99
100

123456789101112131415161718192021222324252627282930

010203040506070809

LC7940YD

010

011

012

013

014

015

016

017

018

019

020

021

022

023

024

025

026

027

028

029

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

030

050
049
048
047
046
045
044
043
042
041
040
039
038
037
036
035
034
033
032
031

CP

CDI

LOAD

SDI

DI3
DI2
DI1

V1

V

NC

V3

V4

V
VSS

P/S

DISP OFF

NC

CDO

NC

010203040506070809

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

81
82
83
84
85
86
87
88

M

89
90

DD

91
92
93
94

EE

95
96
97
98
99
100

123456789101112131415161718192021222324252627282930

080

079

078

077

076

075

074

073

072

010

011

012

013

LC7941YD

071

070

069

068

014

067

015

066

016

065

017

064

018

063

019

062

020

061

021

060

022

059

023

058

024

057

025

056

026

055

027

054

028

053

029

052

030

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

051

031
032
033
034
035
036
037
038
039
040
041
042
043
044
045
046
047
048
049
050

No. 6158—4/11

Block Diagram

LC7940YD, LC7941YD

01 02 03 079 080

V1
V3
V4

V

EE

M

4 Level LCD Drive Circuit

(80 bits)

80

Level Shifter (80 bits)

80

2nd Latch (80 bits)

80

1st Latch (80 bits)

VDD

SS

V

DISP OFF

SDI

DI3
DI2
DI1

P/S CDO

CDI

CP

LOAD

4 bits

Data Bus

Interface

SER/PAR

Control

CLK

204

Address Decoder

Address Counter

(7 bits)

Chip Disable &

Latch Control

Pin Functions

Pin No.

LC7940YD LC7941YD

91 90 V
86 95 V
87 94 V
92 89 V
89 92 V
88 93 V

l00 81 CP I Display data Input clock (falling–edge trigger).

99 82 CDI I

98 83 LOAD I

97 84 SDI I Serial data input.

Synbol I/O Functions

DD
SS
EE

Supply

1
3
4

Supply

V

– VSS is the logic supply.

DD

VDD – VEE is the LCD supply.

LCD panel drive voltage supplies
V1 and VEE are selected levels.
V3 and V4 are not–selected levels.

Chip disable.
Data is read in when LOW, and not road in when HIGH.

Display data latch clock (falling–edge trigger).
On the falling edge, the LCD drive signals set by the display data are output.

No. 6158—5/11

LC7940YD, LC7941YD

Pin No.

LC7940YD LC7941YD

96 85 DI3
95 86 DI2

Synbol I/O Functions

4–bit parallel data input pins.

Data input LCD driver outputs

SDI O4 O8

I

94 87 D11

DI3 O3 O7 O79
DI2 O2 O6 O78
DI1 O1 O5 O77

In serial data input mode, DI1 to DI3 should all be tied HIGH or LOW.
93 88 M I LCD panel drive voltage output alternation control signal.
85 96 P/S I Data input mode select. 4–bit parallel input when HIGH, and serial input when LOW

82 99 CDO O

Cascade connection pin for extension segment drivers. Data is read out when HIGH.

Goes LOW after data is read out. Connected to the CDI input of the next chip.

LCD drive outputs.

The output drive level is determined by the display data, M signal and DISP OFF

input as shown below.

M Q DISP OFF Output

LOW LOW HIGH V

1 to 80 80 to 1 Ol to O80 O

LOW HIGH HIGH V
HIGH LOW HIGH V
HIGH HIGH HIGH V

××

LOW V

Note

x = don’t care (tied HIGH or LOW)

84 97 DISPOFF

I

O1 to O80 output control input pin.
When LOW, V1 is output on the O1 to 080 outputs, See the truth table.

81 91 NC

– No connection.83 98 NC

90 100 NC

O80

3
1
4

EE

1

No. 6158—6/11

Application Notes

LCD Panel 1

4

CP

SDI

LOAD

V3V1M

CP

LOAD

OD1 ED1

2

CP

SDI

LOAD

V3V1M

CP

SDI

LOAD

V3V1M

CP

SDI

LOAD

V3V1M

LC7940YD, LC7941YD

CP

SDI

LOAD

CDI

EE

V

VEE

V3

V4

V1

V4

LC7941YD

VEE
V4

VEE
V4

VEE
V4

(LC7940YD)

CDOCDI

LC7941YD

(LC7940YD)

CDOCDI

LC7941YD

(LC7940YD)

CDOCDI

LC7941YD

(LC7940YD)

M

EE

V

V3

V4

V1

M

EE

V

V3

V4

V1

M

EE

V

V3

V4

V1

M

1

2

159
160

161

162

319
320

321

322

LCD panel (640 × 200 pixels)

479
480

481

482

639
640

100

641

642

799
800

801

802

959
960

961

962

1119
1120

1121

1122

1279
1280

LC7940YD

LC7940YD

LC7940YD

LC7940YD

(LC7941YD)

M

(LC7941YD)

M

(LC7941YD)

M

(LC7941YD)

M

EE

V3

V

V1

V4

LC7941YD

EE

V3

V

V1

V4

LC7941YD

EE

V3

V

V1

V4

LC7941YD

EE

V3

V

V1

V4

LC7941YD

4

CP

LOAD

OD2 ED2

M

EE

V

4

V1 V3

V4

OD1

ED1

FLM

01

DI01

M

M

controller

064CP

DI064

LC7942YD

CL1

V2
V1

CL2

01

036CP

DI01

EE

4

V
V5

ED2

OD2

LC7942YD

M

VDD

EE

V2

V

V1

V5

V146V2

LA5311M

R

4

V3

V4

V5

–

+

–

+

–

+

–

+

R

R7RR

VEE

–11 to –13V

No. 6158—7/11

LCD Panel 2

LC7940YD, LC7941YD

42

4

2 4

EE

V4 V

M V1 V3

4bit Data

CP LOAD

CDI

080 01

CDO

CDICDO

080 01

4bit Data

CP LOAD

LC7941YD-#1

EE

V3

V

V1

V4

M

24244

LC7941YD-#2 LC7941YD-#1

24

LC7941YD-#2

24

LCD panel (640 × 200 pixels)

2

LC7941YD-#8

24

LC7941YD-#8

4bit Data

100

DI01

01

M

036CP

LC7942YD-#1

VDD

EE

V2

V

V1

V5

V146V2

LA5311M

R

V3

–

+

–

+

R

100

01

064CP

4

4bit Data

FLM

DI01

M

controller M

LC7942YD-#1

CP

LOAD

EE

4

V

V1 V3

V4

EE

V

4

–11 to –13V

4

V4

V5

–

+

–

+

R

R

7R

No. 6158—8/11

LC7940YD, LC7941YD

100 × 240–pixel LCD Panel Application

A 100 × 240

pixel LCD panel requires the following

–

drivers.

•3 × LC7940YD (or LC7941YD) drivers

•2 × LC7942YD drivers
An example using l/l00 duty cycle is shown below.

Frame signel

DI01 01

RS/LS 02

LC7942YD

#1

CP
M

063
DI064 064

DI01 01

RS/LS 02

LC7942YD

#2

CP
M

036

DI064

O37 to O64
are open.

1,1
2,1

--- ---

63,1
64,1
65,1
66,1

100,1

01

1,2
2,2

--- ---

63,2
64,2
65,2
66,2

100,2

02

1,79

---

LCD panel (100 × 240 pixels)

---

---

---

100,79

1,80

64,80
65,80

100,80

079#1080

1,79

1,81

64,81
65,81

100,81

01 02

(m,n) : pixel address
Segment line (n)

Common line (m)

1,82

---

---

---

100,82

---

1,160

64,160
65,160

100,160

080

1,

161

--- ---

64,161
65,161

100,161

01

---

---

---

---

1,240
2,240

--- ---

64,240
65,240

100,240

080

Data latch clock

Alternating signal

Serial data

Data shift

clock

P/S

LC7940YD

(LC7941YD)

DI1

DI2

DI3

SDICPLOAD

CDOCDI

1. The LC7942YD chips are cascaded by connecting
DIO64 on chip I to DIO1 on chip 2. For a 100

bit shift

–

register, 037 to 064 on chip 2 are left open.

2. The LC7940YD (or LC7941YD) chips are cascaded
by connecting CDO on chip I to CDI on chip 2, and
CDO on chip 2 to CDI on chip 3. CDI on chip I is tied
to GND, and CDO on chip 3 is not used. This
configuration allows the input of 240

bit serial data.

–

LC7940YD

(LC7941YD)

M

P/S

DI1

DI2

#2

DI3

SDICPLOAD

CDOCDI

M

LC7940YD

(LC7941YD)

P/S

DI1

DI2

#2

DI3

SDICPLOAD

CDOCDI

M

No. 6158—9/11

LC7940YD, LC7941YD

100 x 240-pixel LCD Panel Timing Diagram

M

LOAD

CP

SDO

SDI

LOAD

CP

SDI

1,1

#1

#2

#3

M

1,1

M

1,2 1,79 1,80 1,81 ------

Chip 1 data read

1 line (240 bits)

1,2 1,239

1st line data read 2nd line data read

1 frame (100 × 240 bits)

1,240 2,240 3,1 100,2402,1---

Chip 2 data read Chip 3 data read

--- ---

---1,160 1,161 1,240

#1 DIO1

LOAD

#1

080

#2

080

#3

080

98,1 99,1 99,1100,1 100,11,1

01

02

01

--- ---

01

1,1 2,1

1,2 2,2

1,80 2,80

1,81 2,81

1,160 2,160

1,161 2,161

1,240 2,240

--- ---

98,2 99,2 99,2100,2 100,21,2--- ---

98,80 99,80 99,80100,80 100,801,80--- ---

98,81 99,81 99,81100,81 100,811,81--- ---

98,160 99,160 99,160100,160 100,1601,160--- ---

98,161 99,161 99,161100,161 100,1611,161--- ---

98,240 99,240 99,240100,240 100,2401,240--- ---

LCD drive output data

No. 6158—10/11

Segment Data Not Multiples of 4

Example.

LCD panel (100 × 230 pixels)

LC7940YD, LC7941YD

---

LOAD

SDI

01 080
LC7940YD

#1

m,1 m,2 ,228 m,229 m,230 m+1,1 m+1,2 m+1,229 m+1,230,228---

01 080
LC7940YD

#2

If this timing data is sent, data elements (m, 229), (m,

230), (m+1, 229), (m+1. 230)... will not appear in the

output (O69 and O70 on chip 3). This is because the
LC7940YD (or LC7941YD) converts serial/parallel data

LOAD

SDI

m,1 m,2 ,228 m,229 m,230 m,231 m,232

---

In this case, (m, 231) is output on O71 on chip 3, and (m,

232) on O72 on chip 3. However, these outputs are not

---

01 080
LC7940YD

#3

in 4–bit units, which also decreases power dissipation . For
data that is not a multiple of 4, like 230, the following
scheme is used.

Dummy dataVaild display data

Multiple of 4

connected to the panel and are, therefore, invalid.

■

Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.

SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all

■

semiconductor products fail with some probability. It is possible that these probabilistic failures could give
rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that
could cause damage to other property. When designing equipment, adopt safety measures so that these
kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits
and error prevention circuits for safe design, redundant design, and structural design.

■

In the event that any or all SANYO products(including technical data,services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products
must not be exported without obtaining the export license from the author ities concerned in accordance
with the above law.

No part of this publication may be reproduced or transmitted in any form or by any means, electronic or

■

mechanical, including photocopying and recording, or any information storage or retrieval system, or
otherwise, without the prior written permission of SANYO Electric Co. , Ltd.

■

Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for
the SANYO product that you intend to use.

■

Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no
guarantees are made or implied regarding its use or any infringements of intellectual proper ty rights or
other rights of third parties.

This catalog provides information as of June, 1999. Specifications and information herein are subject to
change without notice.

No. 6158—11/11