Sanyo LC78866V Specifications

Ordering number : EN*4450

O3098HA (OT)/92093JN No. 4450-1/7

LC78866V

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

16-Bit A/D Converter

CMOS LSI

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

Overview

The LC78866V is a 16-bit CMOS A/D converter with a
built-in 4-channel input multiplexer. The LC78866V is
optimal for use in low band digital sampling and uses a
charge redistribution successive approximation method as
its conversion technique.

Features

• A/D converter for use with 16-bit interface
microprocessors

• Charge redistribution successive approximation
conversion

• Built-in 4-channel input multiplexer

• LSB first, offset binary code output

• Built-in sample and hold circuit

• +5 V single voltage power supply

• Low power mode

• Miniature package (SSOP30)

Package Dimensions

unit: mm

3191-SSOP30

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V

Allowable Operating Ranges

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage V

DD

max –0.3 to +7.0 V

Maximum input voltage V

IN

max –0.3 to VDD+ 0.3 V

Maximum output voltage V

OUT

max –0.3 to VDD+ 0.3 V
Operating temperature Topr –20 to +75 °C
Storage temperature Tstg –40 to +125 °C

Parameter Symbol Conditions

Ratings

Unit

min typ max

Supply voltage V

DD

4.5 5.0 5.5 V

Reference voltage (high level) V

H

3.3 V

DD

V

Reference voltage (low level) V

L

0 1.2 V

Analog input voltage V

AIN

V

L

V

H

V

Operating temperature Topr –20 +75 °C

[LC78866V]

SANYO: SSOP30

DC Electrical Characteristics at Ta = –20 to +75°C, VDD= 4.5 to 5.5 V, VSS= 0 V

Note: Digital input pins other than SCK.

AC Electrical Characteristics at Ta = –20 to +75°C, VDD= 4.5 to 5.5 V, VSS= 0 V

Timing Diagram

Analog Characteristics at Ta = 25°C, AV

DD

= DVDD= 5.0 V, VL= 0 V

Note: The A/D converter performs one conversion every F

SCK

/288 period and loads the converted data into the output register in a single operation.
Therefore, when XCS is high, the output register is continually updated every 288 SCK clock cycles, and at the point XCS goes low, data update is
stopped and data output preparation is performed.

No. 4450-2/7

LC78866V

Parameter Symbol Conditions

Ratings

Unit

min typ max
Input high level voltage (note) 2.2 V
Input low level voltage (note) 0.8 V
Output high level voltage I

OH

= –1 µA VDD– 0.05 V

Output low level voltage I

OL

= 1 µA VSS+ 0.05 V

Clock input amplitude SCK pin 0.5 V

P-P

Parameter Symbol Conditions

Ratings

Unit

min typ max
A/D conversion frequency fs (note) 17.4 49.7 55.6 kHz
Linearity error LE (note) 0.025 %

Power dissipation Pd

Normal mode 50 80 mW
Standby mode 15 30 mW

Parameter Symbol Conditions

Ratings

Unit

min typ max
XCS setup time T

XCSS

1.5 µs

XCS hold time T

XCSH

1.5 µs

XCLK cycle time T

XCKC

1.0 µs

XCLK pulse width T

WH

300 ns

XCLK pulse width T

WL

300 ns

CNT setup time T

DS

50 ns

CNT hold time T

DH

50 ns

DATAO delay time T

DL

0 150 ns

SCK clock frequency F

SCK

5 14.32 16 MHz

Input Impedance at AVDD= DVDD= 5.0 V, VH= 5.0 V, VL= 0 V

Note: * Sampling frequency: 49.7 kHz

Power On Timing

AVDDand DVDDare completely independent.

AGND and DGND are connected through the IC substrate.

The optimal power on/off timing is to bring up (or down) the analog power supply (AV

DD

) and the digital power supply

(DV

DD

) voltages at the same time. If a time difference must be used, apply power first to the analog system and then to

the digital system, with a time difference (tV

DD

) of 2 to 3 ms or less. Power down the chip in the opposite order.

Block Diagram

No. 4450-3/7

LC78866V

Parameter Symbol Conditions

Ratings

Unit

min typ max

Input impedance A

DIN

DC input* 5 M Ω
AC 1 kHz input* 250 k Ω