Sanyo LC7871E Specifications

Ordering number : EN4861

CMOS LSI

LC7871E, 7871NE

CD Graphics Decoder

The

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addition

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SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

51795TH (OT) No. 4861-1/19

LC7871E, 7871NE

Block

Pin

Top view

No. 4861-2/19

LC7871E, 7871NE

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V

Unit

V

V

V

V

V

V

V

V

V

V

ns

ns

ns

Low

ns

DO

ns

MHz

MHz

MHz

MHz

MHz

MHz

CE

ns

CE

ns

CE

ns

Vp-p

ns

											Unit
											mA
											mA
											mA
			RESET,	SFSY, PW, SBSY, CE, DI, CL, MUTE, TEST,
Input high level current	IIH (1)		TEST1, TEST2, SON, M1/M2, N/P1, N/P2,			VRESET,				5	µA
			HRESET: VIN = VDD
	IIH (2)		CH0 to 15, DEN: VIN = VDD					30	100	200	µA

Continued on next page.

No. 4861-3/19

LC7871E, 7871NE

Continued from preceding page.

Parameter

Symbol

Conditions

min

typ

max

Unit

RESET,

SFSY, PW, SBSY, CE, DI, CL, MUTE, TEST,

Input

µA

µA

V

V

V

µA

Built

MΩ

6-

V

6-

Ω

8-

V

8-

Ω

8-

ns

Page

ns

RAS

ns

RAS

ns

ns

RAS

ns

RAS

ns

CAS

ns

CAS

CAS

ns

CAS

ns

Row

ns

Row

ns

ns

ns

ns

ns

ns

Write

ns

Write

ns

Write

ns

Write

ns

Write

ns

CAS

ns

ns

CAS

ns

RAS

ns

ns

ns

SBCK output delay time

tSD

Figure 8

NTSC mode

4.749

5.029

µs

PAL mode

4.793

5.075

µs

SBCK cycle frequency

fSC

Figure 8

NTSC mode

223.7

kHz

PAL mode

221.7

kHz

PW setup time

tPWS

Figure 8

100

ns

No. 4861-4/19

LC7871E, 7871NE

No. 4861-5/19

LC7871E, 7871NE

Figure 4 DRAM Page Mode Read Cycle

No. 4861-6/19