Sanyo LC7871E Specifications

Ordering number : EN4861

51795TH (OT) No. 4861-1/19

Overview

The LC7871E and LC7871NE are CMOS LSIs that
integrate the signal processing functions required for
compact disk extended graphics (CD-EG) decoding in a
single chip. These products accept the R to W subcode
signals output by CDP-DSP products such as the
LC7860KA, LC7867E, LC7868E, LC7869E, or
LC78681E, and perform de-interleaving, error detection
and correction, graphics instruction processing, and image
processing.

Functions

• The LC7871E and LC7871NE allow a CD-EG decoder
to be constructed with only three chips with the addition
of two external DRAMs (64k × 4). (An RGB encoder is
provided on chip.)

• The LC7871E and LC7871NE perform subcode
synchronization signal interpolation and protection.
They also perform R to W signal de-interleaving and
error detection and correction.

• These products include two crystal oscillator systems
(one for NTSC and one for PAL) which can be easily
switched from a control pin. These products generate the
reference clocks as well as all internal timings for these
two standards by using a 14.31818 MHz crystal for
NTSC and a 17.734476 MHz crystal for PAL.

• Control of image display using CD graphics instructions
and display processing.

• Composite video 8-bit D/A converter output as well as
“define-transparency” 6-bit D/A converter output.

• Support for superimposition

• Microprocessor interface function that supports end­product upgrades.

• External input pin for channel selection

• Built-in 6-bit RGB D/A converters

• The only difference between the LC7871E and the
LC7871NE is in the BGC to VRAM transfer.
The LC7871E uses a preset memory instruction for
transfer to VRAM, whereas the LC7871NE uses the
load CLUT instruction.

Features

• A CD-G decoder can be constructed from only two
chips, since no controller is required.

• A CD-EG decoder can be constructed with the addition
of two 256-kbit DRAMs since no controller is required.

• Silicon gate CMOS process for low power dissipation

• 5 V single voltage power supply

Package Dimensions

unit: mm

3151-QFP100E

SANYO: QIP100E

[LC7871E, 7871NE]

LC7871E, 7871NE

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

CD Graphics Decoder

CMOS LSI

Block Diagram

Pin Assignment

No. 4861-2/19

LC7871E, 7871NE

Top view

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V

Allowable Operating Ranges at Ta = 25°C, V

SS

= 0 V

Electrical Characteristics at Ta = 25°C, V

SS

= 0 V, VDD= 5 V

No. 4861-3/19

LC7871E, 7871NE

Parameter Symbol Ratings Unit

Maximum supply voltage V

DD

max VSS– 0.3 to +7.0 V

Maximum input voltage V

IN

max VSS– 0.3 to VDD+ 0.3 V

Maximum output voltage V

OUT

max VSS– 0.3 to VDD+ 0.3 V
Allowable power dissipation Pd max 500 mW
Operating temperature Topr –30 to +85 °C
Storage temperature Tstg –40 + 125 °C

Parameter Symbol Conditions min typ max Unit

Supply voltage V

DD

VDD1, VDD2, VDD3 4.5 5.5 V

V

IH

(1) RESET 0.7 V

DD

V

DD

V

SFSY, PW, SBSY, MUTE, TEST, TEST1, TEST2,

V

IH

(2) SON, M1/M2, N/P1, N/P2, PALID, HRESET, VRESET, 2.2 V

DD

V

Input high level voltage

1DB0 to 3, 2DB0 to 3

V

IH

(3) CH0 to 15, DEN, CL, CE, DI 0.8 V

DD

V

DD

V

V

IH

(4) S 0.9 V

DD

V

DD

V

V

IL

(1) RESET V

SS

0.3 V

DD

V

SFSY, PW, SBSY, MUTE, TEST, TEST1, TEST2,

V

IL

(2) SON, M1/M2, N/P1, N/P2, PALID, HRESET, VRESET, V

SS

0.8 V

Input low level voltage

1DB0 to 3, 2DB0 to 3

VIL(3) CH0 to 15, DEN, CL, CE, DI V

SS

0.2 V

DD

V

V

IL

(4) S V

SS

0.1 V

DD

V

Input middle level voltage V

IM

S 0.37 V

DD

0.43 V

DD

V

Data setup time t

DS

DI, CL: Figure 1 200 ns

Data hold time t

DH

DI, CL: Figure 1 200 ns

High level clock pulse width t

WøH

CL: Figure 1 400 ns

Low level clock pulse width t

WøL

CL: Figure 1 400 ns

DO setup time t

DOS

DO, CL: Figure 1 250 450 ns
fin (1) XIN1 14.31818 MHz
fin (2) XIN2 17.734476 MHz

Input frequency 4FSC2

NTSC mode 14.31818 MHz
PAL mode 17.734476 MHz

FSCIN

NTSC mode 3.58 MHz
PAL mode 4.43 MHz

CE wait time t

CP

CE, CL: Figure 1 400 ns

CE setup time t

CS

CE, CL: Figure 1 0 ns

CE hold time t

CH

CE, CL: Figure 1 400 ns

Input amplitude V

IN

XIN1, XIN2, 4FSC2, FSCIN:

0.3 5 Vp-p

Sine wave, capacitive coupling

Reset pulse width t

WRES

RESET 400 ns

Parameter Symbol Conditions min typ max Unit

I

DD

(1) VDD12640mA

Current drain I

DD

(2) VDD22640mA

I

DD

(3) VDD31115mA

RESET, SFSY, PW, SBSY, CE, DI, CL, MUTE, TEST,
I

IH

(1) TEST1, TEST2, SON, M1/M2, N/P1, N/P2, VRESET, 5 µA

Input high level current

HRESET: V

IN

= V

DD

IIH(2) CH0 to 15, DEN: VIN= V

DD

30 100 200 µA

Continued on next page.

Continued from preceding page.

No. 4861-4/19

LC7871E, 7871NE

Parameter Symbol Conditions min typ max Unit

RESET, SFSY, PW, SBSY, CE, DI, CL, MUTE, TEST,
IIL(1) TEST1, TEST2, SON, M1/M2, N/P1, N/P2, VRESET, –5µA

Input low level current

HRESET: V

IN

= V

SS

IIL(2) PALID: VIN= V

SS

–400 –200 –60 µA

SBCK, 1WE, RAS, 1A0 to 7, 2A0 to 7, CAS, OE, 2WE,

Output high level voltage V

OH

(1) CDGM, TRANS0 to 5, 2FSC, YS, CSYNC, VSYNC, VDD– 1V

DD

V

EFLG, FSX, FSC, 1DB0 to 3, 2DB0 to 3: I

O

= –0.5 mA

SBCK, 1WE, RAS, 1A0 to 7, 2A0 to 7, CAS, OE, 2WE,

V

OL

(1) CDGM, TRANS0 to 5, 2FSC, YS, CSYNC, VSYNC, V

SS

0.4 V

Output low level voltage

EFLG, FSX, FSC, 1DB0 to 3, 2DB0 to 3: I

O

= 2 mA

V

OL

(2) DO: IO= 5 mA V

SS

0.75 V

Output off leakage current I

OFF

DO, 1DB0 to 3, 2DB0 to 3 –5+5µA

Built-in feedback resistance RX XIN1, XIN2, 4FSC2, FSCIN 1 MΩ
6-bit D/A converter

V

REF

(1) ROUT, BOUT, GOUT, TRANS 3.95 4 4.05 V

reference voltage
6-bit D/A converter

R

DA

(1) ROUT, BOUT, GOUT, TRANS 150 Ω

output resistance
8-bit D/A converter

V

REF

(2) VIDEO 3.65 3.70 3.75 V

reference voltage
8-bit D/A converter

R

DA

(2) VIDEO 150 Ω

output resistance
8-bit D/A converter output level VDAC VIDEO: Figure 9
Random read/write cycle time t

RC

Figures 2 and 3 400 ns

Page mode cycle time t

PC

Figures 4 and 5 130 ns

RAS precharge time t

RP

Figures 2, 3, 4, 5 and 6 100 ns

RAS pulse width t

RAS

Figures 2, 3 and 6 120 ns

RAS pulse width (page mode) t

RASP

Figures 4 and 5 18000 ns

RAS hold time t

RSH

Figures 2, 3, 4 and 5 60 ns

CAS hold time t

CSH

Figures 2 and 3 120 ns

CAS pulse width t

CAS

Figures 2, 3, 4 and 5 60 ns

CAS precharge time t

CPN

Figure 6 50 ns

CAS precharge time (page mode) t

CP

Figures 4 and 5 50 ns

Row address setup time t

ASR

Figures 2, 3, 4 and 5 100 ns

Row address hold time t

RAH

Figures 2, 3, 4 and 5 50 ns

Column address setup time t

ASC

Figures 2, 3, 4 and 5 0 ns

Column address hold time t

CAH

Figures 2, 3, 4 and 5 50 ns

Read command setup time t

RCS

Figure 2 150 ns

Read command hold time

t

RCH

Figure 2 120 ns

(referenced to CAS)
Read command hold time

t

RRH

Figure 2 120 ns

(referenced to RAS)
Write command setup time t

WCS

Figure 3 100 ns

Write command hold time t

WCH

Figure 3 50 ns

Write command pulse width t

WP

Figure 3 150 ns

Write data setup time t

DS

Figure 3 100 ns

Write data hold time t

DH

Figure 3 100 ns

CAS setup time

t

CSR

Figure 6 50 ns

(CAS before RAS)
CAS hold time (CAS before RAS) t

CHR

Figure 6 50 ns

RAS precharge · CAS active time t

RPC

Figure 6 50 ns

Read data setup time t

RDS

Figures 2, 4 and 5 20 ns

Read data hold time t

RDH

Figures 2, 4 and 5 10 ns

VIDEO setup time t

VS

Superimposition: Figure 7 20 25 ns

SBCK output delay time t

SD

Figure 8

NTSC mode 4.749 5.029 µs
PAL mode 4.793 5.075 µs

SBCK cycle frequency f

SC

Figure 8

NTSC mode 223.7 kHz
PAL mode 221.7 kHz

PW setup time t

PWS

Figure 8 100 ns

Figure 1 Microcontroller Interface Timing

Figure 2 DRAM Read Cycle

No. 4861-5/19

LC7871E, 7871NE

Figure 3 DRAM Early Write Cycle

Figure 4 DRAM Page Mode Read Cycle

No. 4861-6/19

LC7871E, 7871NE