Sanyo LC7868KE Specifications

Ordering number : EN4882

N1594TH (OT) B8-1395 No. 4882-1/24

Overview

The LC7868KE is a CMOS LSI that implements the signal processing and servo control required by compact disk players, laser disks, CD-V, CD-I and related products. The LC7868KE provides several types of signal processing to reduce the cost of CD player units, including demodulation of the optical pickup EFM signal, deinterleaving and error detection and correction. It also processes a rich set of servo system commands sent from the control microprocessor. It can directly interface to the dedicated serial inputs provided by the Sanyo LC78815 and LC78816 D/A converters.

Functions

• Input signal processing: The LC7868KE takes an HF signal as input, digitizes (slices) that signal at a precise level, converts that signal to an EFM signal, and generates a PLL clock with an average frequency of

4.3218 MHz by comparing the phases of that signal and a VCO output.

• Precise reference clock and necessary internal timing generation using an external 16.9344 MHz crystal oscillator

• Disk motor speed control using a frame phase difference signal generated from the playback clock and the reference clock

• Frame synchronization signal detection, protection and interpolation to assure stable data readout

• EFM signal demodulation and conversion to 8-bit symbol data

• Subcode data separation from the EFM demodulated signal and output of that data to an external microprocessor

• Subcode Q signal output to a microprocessor over the serial interface after performing a CRC error check (An

LSB first output format can be selected.)

• Demodulated EFM signal buffering in internal RAM to handle up to ±4 frames of disk rotational jitter

• Demodulated EFM signal reordering in the prescribed order for data unscrambling and de-interleaving

• Error detection, correction, and flag processing (error correction scheme: dual C1 plus dual C2 correction)

• The LC7868KE sets the C2 flags based on the C1 flags and a C2 check, and then performs signal interpolation or previous value hold depending on the C2 flags. The interpolation circuit uses a quadruple interpolation scheme. The output value is locked at zero when four or more consecutive C2 flags occur.

• Support for command input from a control microprocessor: commands include track jump, focus start, disk motor start/stop, muting on/off and track count (8-bit serial input)

• Built-in digital output circuits.

• Arbitrary track counting to support high-speed data access

• Zero cross muting

• D/A converter input signal outputs with output data continuity improved by 4× oversampling and digital filtering

• Supports most D/A converters

• Built-in digital de-emphasis

• Built-in digital level and peak meter functions

• Support for bilingual applications

Features

• 64-pin QIP (miniature, reduced space package)

• Silicon gate CMOS process (low power)

• Single 5 V power supply (for application in portable end products)

• Provision of a DEMO pin eases the manufacturing processes associated with adjustment steps.

LC7868KE

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Digital Signal Processor for

Compact Disc Players

CMOS LSI

Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.

Equivalent Circuit Block Diagram

No. 4882-2/24

LC7868KE

Package Dimensions

unit: mm

3159-QFP64E

SANYO: QFP64E

[LC7868KE]

Pin Assignment

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V

No. 4882-3/24

LC7868KE

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage V

max VSS– 0.3 to +7.0 V

Maximum input voltage V

max VSS– 0.3 to VDD+ 0.3 V

Maximum output voltage V

OUT

max VSS– 0.3 to VDD+ 0.3 V Allowable power dissipation Pd max 300 mW Operating temperature Topr –30 to +75 °C Storage temperature Tstg –40 to +125 °C

Top view

Allowable Operating Ranges at Ta = 25°C, VSS= 0 V

Electrical Characteristics at Ta = 25°C, V

= 0 V, VDD= 5 V

No. 4882-4/24

LC7868KE

Parameter Symbol Conditions min typ max Unit

Supply voltage V

4.5 5.5 V

(1) TEST1 to 5, AI, FZD, HFL, DEMO, DFOFF, M/L, RES 0.7 V

Input high level voltage

(2) SBCK, RWC, COIN, CQCK, CS 2.2 V

(3) EFMIN 0.6 V

(4) TES 0.8 V

(1) TEST1 to 5, AI, FZD, HFL, DEMO, DFOFF, M/L, RES V

0.3 V

Input low level voltage

(2) SBCK, RWC, COIN, CQCK, CS V

0.8 V

(3) EFMIN V

0.4 V

(4) TES V

0.2 V

Data setup time t

setup

COIN, RWC: Figure 1 400 ns

Data hold time t

hold

RWC: Figure 1 400 ns

High level clock pulse width t

WøH

SBCK, CQCK: Figures 1, 2 and 3 400 ns

Low level clock pulse width t

WøL

SBCK, CQCK: Figures 1, 2 and 3 400 ns

Data read access time t

RAC

Figures 2 and 3 0 400 ns

Command transfer time t

RWC

RWC: Figure 1 1000 ns

Subcode Q read enable time t

SQE

Figure 2, with no RWC signal 11.2 ms Subcode read cycle t sc Figure 3 136 µs Subcode read enable time t se Figure 3 400 ns Crystal oscillator frequency fX’tal XIN, XOUT 16.9344 MHz

Operating frequency range

fop (1) AI 2.0 20 MHz fop (2) EFMIN: V

≥ 1 Vp-p 10 MHz

Parameter Symbol Conditions min typ max Unit

Supply current I

17 30 mA

(1)

AI, EFMIN, FZD, TES, SBCK, COIN, CQCK, RES,

5µA

Input high level current

HFL, RWC, M/L: V

= V

IIH(2) TEST1 to 5, DEMO, CS: VIN= VDD= 5.5 V 25 75 µA

Input low level current I

(1)

AI, EFMIN, FZD, TES, SBCK, COIN, CQCK, RES,

–5µA

HFL, RWC, M/L: V

= V

AO, PDO,EFMO, EFMO, CLV+, CLV–, FOCS, FSEQ,

(1) PCK, TOFF, TGL, THLD, JP+, JP–, EMPH, EFLG, VDD– 1V

FSX, V/P: I

= –1 mA

Output high level voltage

(2) DOUT: IOH= –12 mA VDD– 0.5 V

LASER, SQOUT, 16M, 4.2M, CONT, LRCLK, WRQ,

(3)

C2F, DACLK, SFSY, LRSY, SBSY, CK2, PW, ROMOUT,

VDD– 1V

C2FCLK, DFOUT, TEST9, TEST8, WCLK, DFIN:

= –0.5 mA

AO, PDO, EFMO, EFMO, CLV

, CLV–, FOCS, FSEQ,

(1) PCK, TOFF, TGL, THLD, JP+, JP–, EMPH, EFLG, 1 V

FSX, V/P: I

= 1 mA

(2) DOUT: IOL= 12 mA 0.5 V

Output low level voltage LASER, SQOUT, 16M, 4.2M, CONT, LRCLK, WRQ,

(3)

C2F, DACLK, SFSY, LRSY, SBSY, CK2, PW, ROMOUT,

0.4 V

C2FCLK, DFOUT, TEST9, TEST8, WCLK, DFIN:

= 2 mA

(4) FST: IOL= 5 mA 0.75 V

Output off leakage current

OFF

(1) PDO, FST: VOH= V

5µA

OFF

(2) PDO, FST: VOL= V

–5µA

Wave Form

Figure 1 Command Input

Figure 2 Subcode Q Output

Figure 3 Subcode Output

No. 4882-5/24

LC7868KE

Pin Functions

No. 4882-6/24

LC7868KE

No. Name I/O Description

1 TEST1 I LSI test pin. Normally left open. 2AO O 3AI I 4 PDO O 5V

— GND 6 EFMO O 7 EFMO O 8 EFMIN I 9 TEST2 I LSI test pin. Normally left open.

10 CLV

Disk motor control output.

11 CLV

–

Three-state output is also possible when specified by microprocessor command.

12 V/P O Outputs a high level during CLV rough servo and a low level during phase control. 13 FOCS O 14 FST O 15 FZD I 16 HFL I 17 TES I 18 PCK O PCK is the 4.3218 MHz monitor pin.

19 FSEQ O

FSEQ outputs a high level when the synchronization (positive FS) detected from the EFM signal matches the counter

synchronization (interpolation FS). (The output is latched for a single frame.) 20 TOFF O 21 TGL O 22 THLD O 23 TEST3 I LSI test pin. Normally left open. 24 V

— +5 V

25 JP

26 JP

–

O 27 DEMO I Sound output function for end product adjustment manufacturing steps. 28 TEST4 I LSI test pin. Normally left open. 29 EMPH O De-emphasis is required when high. 30 DFOFF I Digital filter on/off switch. Filtering is turned off on a high level input. 31 WCLK O 32 TEST8 O 33 LRCLK O 34 TEST9 O 35 DFOUT O 36 DACLK O 37 DFIN O LSI test pin. Normally left open. 38 LRSY O 39 CK2 O 40 ROMOUT O CD-ROM application output signals 41 C2FCLK O 42 C2F O 43 DOUT O Digital output 44 SBSY O Subcode block synchronization signal 45 EFLG O C1, C2, single and double error correction monitor pin 46 PW O 47 SFSY O 48 SBCK I 49 FSX O 7.35 kHz synchronization signal output

Inputs for the LA9210 internal VCO output. (8.6436 MHz) Set up PDO so that the frequency increases when the EFM signal and the phase output are positive.

Supply an HF signal with a 1 to 2 Vp-p level to EFMIN. EFMO and EFMO output EFM signals with opposite phases that passed through an amplitude limiter circuit. These are used for slice level control.

FOCS outputs a high level when the focus servo is off. The lens is lowered by FST, and when FOCS is high the lens is raised gradually. FOCS is reset when an FZD input occurs. These are used for focus pull-in.

The LC7868KE outputs a kick pulse from JP

and JP–in response to a track jump command. A track jump of the

specified number of tracks (1, 2, 4, 16, 32, 64, and 128) is performed.

The LC7868KE outputs a kick pulse from JP

and JP–in response to a track jump command. A track jump of the

specified number of tracks (1, 2, 4, 16, 32, 64, and 128) is performed.

The LC7868KE outputs a kick pulse from JP

and JP–in response to a track jump command. A track jump of the specified number of tracks (1, 2, 4, 16, 32, 64, and 128) is performed. Three-state output is also possible when specified by microprocessor command.

Outputs for an external D/A converter. These include a latch signal, an L/R switching signal, and a sample and hold signal.

SFSY is the subcode frame synchronization signal. The P, Q, R, S, T, U, V and W subcodes can be read out by applying 8 clock cycles to SBCK.

Continued on next page.

Continued from preceding page.

Pin Applications

1. HF signal input circuit; Pin 8: EFMIN, pin 7: EFMO, pin 6: EFMO An EFM signal (NRZ) with an optimal slice level can be acquired by inputting the HF signal to EFMIN.

2. PLL clock generation circuit; Pin 4: PDO, Pin 3: AI, Pin 2: AO

A VCO can be constructed by combining the LC7868KE with the Sanyo LA9210. The PDO pin swings in the positive direction when the VCO phase lags.

No. 4882-7/24

LC7868KE

No. Name I/O Description

50 WRQ O 51 RWC I 52 SQOUT O 53 COIN I 54 CQCK I 55 RES I This pin must be set low briefly after power is first applied. 56 M/L I Similar to pins number 50, 51, 52, 53 and 54 described above. 57 LASER O Output pin controllable by serial data sent from the microprocessor. 58 16M O 16.9344 MHz output pin 59 4.2M O 4.2336 MHz output pin 60 CONT O Output pin controllable by serial data sent from the microprocessor. 61 TEST5 I LSI test pin. Normally left open. 62 CS I Chip select pin. The LC7868KE becomes active when this pin is low. (A pull-down resistor is built-in.) 63 X

Connections for a 16.9344 MHz crystal oscillator

64 X

OUT

WRQ goes high when the subcode Q data passes the CRC check. An external controller can read out data from SQOUT by monitoring this pin and applying a CQCK signal. Set M/L to low when data is required LSB first. The control microprocessor can send commands to the LC7868KE by setting RWC high and then sending command data synchronized with CQCK.

3. 1/2 VCO; Pin 18: PCK PCK is a monitor pin that outputs an average frequency of 4.3218 MHz, which is the VCO frequency divided by two.

4. Synchronization detection monitor; Pin 19: FSEQ Pin 19 goes high when the frame synchronization (a positive polarity synchronization signal) from the EFM signal read in by PCK and the timing generated by the counter (the interpolation synchronization signal) agree. This pin is a synchronization detection monitor. (It is held high for a single frame.)

5. Servo command function; Pin 51: RWC, pin 53: COIN, pin 54: CQCK, pin 62: CS Commands are input to the LC7868KE by setting RWC high and sending commands to the COIN pin in synchronization with the CQCK clock.

Focus start Track jump Mute control 1-byte commands Disc motor control Other control commands

Track count 2-byte command

• One-byte commands

• Two-byte commands

Command execution starts on the falling edge of the RWC signal.

• Command noise exclusion

This command allows the noise on the CQCK clock signal to be excluded.

No. 4882-8/24

LC7868KE

MSB LSB Command RES = low

11101111 COMMAND INPUT NOISE EXCLUSION MODE 11101110 RESET NOISE EXCLUSION MODE

○

+ 16 hidden pages