Sanyo LC78626KE Specifications

Overview

The LC78626KE is a monolithic compact disk player signal processing and servo control CMOS IC equipped with an internal anti-shock control function. Designed for total functionality including support for EFM-PLL, and one-bit D/A converter, and containing analog low-pass filter, the LC78626KE provides optimal cost-performance for low-end CD players that provide anti-shock systems by eliminating as many unnecessary features as possible. The basic functions provided by this IC include modulation of the EFM signal from the optical pick-up, deinterleaving, detection and correction of signal errors, prevention of a maximum of approximately 38 seconds of skipping, signal processing such as digital filtering (which is useful in reducing the cost of the player), and processing of a variety of servo-related commands from the microprocessor. The LC78626KE is an improved version of the LC78626E. It provides 8× oversampling digital filters and supports up to 16M of DRAM.

Functions

• When an HF signal is input, it is sliced to precise levels and converted to an EFM signal. The phase is compared with the internal VCO and a PLL clock is reproduced at an average frequency of 4.3218 MHz.

• Precise timing for a variety of required internal timing needs (including the generation of the reference clock) is produced by the attachment of an external 16.9344 MHz crystal oscillator.

• The speed of revolution of the disk motor is controlled by the frame phase difference signal generated by the playback clock and the reference clock.

• The frame synchronizing signal is detected, stored, and interpolated to insure stable data read back.

• The EFM signal is demodulated and converted to 8-bit symbolic data.

• The demodulated EFM signal is divided into subcodes and output to the external microprocessor. (Three general I/O ports are shared [exclusively] for this purpose.)

• After the subcode Q signal passes the CRC check, it is output to the microprocessor through a serial transmission (LSB first).

• The demodulated EFM signal is buffered in the internal RAM, which is able to absorb ±4 frame’s worth of jitter resulting from variations in the disk rotation speed.

• The demodulated EFM signal is unscrambled to a specific sequence, and deinterleaving is performed.

Package Dimensions

unit: mm

3151-QFP100E

21.6

0.8

3.0max

1.6

17.2

0.825

130

80 81

1.6

0.575

0.15

2.7

15.6

0.3

20.0

23.2

14.0

0.65

0.825

100

0.8

0.65

0.1

CMOS IC

21099RM(OT) No. 5995-1/34

SANYO: QFP100E (QIP100E)

[LC78626KE]

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN

DSP for Compact Disk Players

LC78626KE

Ordering number : EN5995

Continued on next page.

Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.

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Continued from preceding page.

• Error detection and correction is performed, as is a flag process. (C1: two error/C2: two error correction method.)

• The C2 flag is set after referencing the C1 flag and the results of the C2 check, where the signal from the C2 flag is interpolated or held at its previous level. The interpolation circuit uses double interpolation. When there are two or more C2 flags in a row, the previous value is held.

• Command (such as track jump, start focus, disk motor start/stop, muting on/off, track count, etc.) is are executed after they are entered from the microprocessor. (An 8-bit serial input is used.)

• The digital output is equipped internally.

• High speed access is supported through discretionary track counting.

• Using the 8× oversampling digital filter, D/A converter signals with improved continuity of output data are produced.

• A ∆∑-type D/A converter using a 3-order noise shaper is

equipped internally. (An analog low-pass filter is equipped internally.)

• Internal digital attenuator (8-bit-α; 239 steps.)

• Internal digital deemphasis

• Uses 0 cross mute.

• Bilingual compatibility

• General I/O ports: 4. (Three of these are shared, exclusively, with the subcode output function.)

• Up to 38 seconds of skip prevention (when using 16M of DRAM) through 5-bit ADPCM compression/ expansion processing. 1M/4M/4M × 2/16Μ bits DRAM can be selected.

• Memory overflow detection output

• Free memory output

Features

• 100-pin QIP

• A single 3.2 V power supply

Pin Assignment

Top view

Equivalent Circuit Block Diagram

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Digital out

RAM address

generator

Interpolation mute

Shock

detector

Contact

detector

ADPCM

encoder

Data width

changer

2K × 8-bit RAM

Digital

attenuator

4 × oversampling digital filter

C1, C2 error detection and

correction flag process

VCO clock production

clock control

Slice level control

Sync detect

EFM

demodulation

CLV digital servo

Subcode partition

QCRC

Microprocessor

interface

Servo commands

General ports

Disable

Crystal oscillator-system

timing generator

One-bit DAC

Low-pass

filter

ADPCM

decoder

DRAM control

Overflow process

initiation control

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Parameter Symbol Conditions Ratings Unit

Maximum power supply voltage V

max VSS– 0.3 to VSS+ 4.0 V

Input voltage V

VSS– 0.3 to VDD+ 0.3 V

Output voltage V

OUT

VSS– 0.3 to VDD+ 0.3 V Allowable power dissipation Pd max 400 mW Operating temperature range Topr –20 to +75 °C Storage temperature range Tstg –40 to +125 °C

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS= 0V

Parameter Symbol Conditions

Ratings

Unit

min typ max

, XVDD, LVDD, RVDD, VVDD:

3.0 3.6 V

Power supply voltage

ATT/DF/DAC to the normal speed

, XVDD, LVDD, RVDD, VVDD:

3.6 3.6 V

All functions guaranteed to 2× speed

I/O and input pins with the exception of

0.7 V

Input high-level voltage

EFMI and DRAM0 to DRAM3

2 EFMI 0.6 V

3 DRAM0 to DRAM3 0.45 V

I/O and input pins with the exception of

0 0.3 V

Input low-level voltage

EFMI and DRAM0 to DRAM3

2 EFMI 0 0.4 V

2 DRAM0 to DRAM3 0 0.2 V

Data setup time t

COIN, RWC: Figure 1 400 ns

Data hold time t

COIN, RWC: Figure 1 400 ns

High level clock pulse width t

SBCK, CQCK: Figures 1 to 3 400 ns

Low level clock pulse width t

SBCK, CQCK: Figures 1 to 3 400 ns

Data read access time t

RAC

SQOUT, PW: Figures 2 and 3 0 400 ns

Command transfer time t

RWC

RWC: Figure 1 1000 ns

Subcode Q read enable time t

SQE

WRQ: Figure 2, no RWC signal 11.2 ms

Subcode ready cycle time t

SFSY: Figure 3 136 µs

Subcode read enable time t

SFSY: Figure 3 400 ns

Port input data setup time t

CSU

CONT2 to CONT5, RWC: Figure 4 400 ns

Port input data hold time t

CHD

CONT2 to CONT5, RWC: Figure 4 400 ns

Port input clock setup time t

RCQ

RWC, CQCK: Figure 4 100 ns

Port output data delay time t

CDD

CONT2 to CONT5, RWC: Figure 5 1200 ns

Input level

1 EFMI: slice level control, VDD= 3.0 V 0.8 Vp-p

2 XIN: C coupling input 1.0 Vp-p

Range of operating frequencies f

EFMI 10 MHz

Crystal oscillator frequency f

XIN, XOUT 16.9344 MHz

Allowable Operating Range at Ta = 25°C, VSS= 0V

Parameter Symbol Conditions

Ratings

Unit

min typ max

Current drain I

VDD, XVDD, LVDD, RVDD, VVDD:

14 20 mA

= 3.0 to 3.4 V with normal playback

DEFI, EFMI, HFL, TES, RWC, COIN, CQCK,

FMT, MR1, MR2, RES, TESD, WOK,

5 µA

PAUSE IN, SHOCK, TESCLK, TESA, TESB,

Input high-level current

TESC, TESGB, TEST1: V

= V

IIH2

TAI, TEST2 to TEST5, CS

15 55 µA

= VDD= 3.6 V

Electrical Characteristics at Ta = 25°C, VDD= 3.2 V, VSS= 0V

Continued on next page.

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Continued from preceding page.

Parameter Symbol Conditions

Ratings

Unit

min typ max

DEFI, EFMI, HFL, TES, RWC, COIN, CQCK, FMT, MR1, MR2, RES, TESD, WOK,

Input low-level current I

PAUSE IN, SHOCK, TESCLK, TESA, TESB, –5 µA TESC, TESGB, TAI, TEST1 to TEST5, CS : V

= 0 V

EFMO, CLV

, CLV–, V/P, TOFF, TGL, JP+,

1 JP–, PCK, FSEQ, EFLG, FSX, EMPH : 2.56 V

= –1 mA

CONT2 to CONT5, SBSY, MUTEL, MUTER,

Output high-level current

VOH2 C2F, WRQ, SQOUT, 16M/NGJ, 4.2M, EMPP, 2.56 V

OVF, CNTOK, NGJ : I

= –0.5 mA

3 DOUT : IOH= –12 mA 2.72 V

OE, WE, CAS, RAS, AD10/CAS2, AD9 to AD0,

2.56 V

DRAM3 to DRAM0 : I

= –0.5 mA

5 MMC0 to MMC3 : IOH= –2 mA 2.24 V

EFMO, CLV

, CLV–, V/P, TOFF, JP+, JP–,

0.64 V

PCK, FSEQ, EFLG, FSX, EMPH : I

= 1 mA

CONT2 to CONT5, SBSY, MUTEL, MUTER,

2 C2F, WRQ, SQOUT, 16M/NGJ, 4.2M, EMPP, 0.32 V

Output low-level current

OVF, CNTOK : I

= 2 mA

3 DOUT : IOL= 12 mA 0.48 V

OE, WE, CAS, RAS, AD10/CAS2, AD9 to AD0,

0.44 V

DRAM3 to DRAM0 : I

= 0.5 mA

5 MMC0 to MMC3 : IOL= 2 mA 0.96 V

PDO, CLV

, CLV–, JP+, JP–,

OFF

1 CONT2 to CONT5, DRAM0 to DRAM3, 5 µA

Output off leakage current

ASRES : V

OUT

= V

PDO, CLV+, CLV–, JP+, JP–,

OFF

2 CONT2 to CONT5, DRAM0 to DRAM3, –5 µA

ASRES : V

OUT

= 0 V

Charge pump output current

PDOH

PDO : R

ISET

= 68 kΩ 30 42 54 µA

PDOL

PDO : R

ISET

= 68 kΩ –54 –42 –30 µA

Parameter Symbol Conditions

Ratings

Unit

min typ max

Total harmonic distortion rate TRD+N

LCHO, RCHO; 1 kHz: Uses the 0 dB data

0.035 0.038 %

input and the 20 kHz-LPF (in the AD725D) LCHO, RCHO; 1 kHz: Uses the –60 dB data

Dynamic range DR input, the 20 kHz-LPF (in the AD725D), and 81 84 dB

the A filter LCHO, RCHO; 1 kHz: Uses the 0 dB data

Signal to noise ratio S/N input, the 20 kHz-LPF (in the AD725D), and 87 92 dB

the A filter

Cross talk CT

LCHO, RCHO; 1 kHz: Uses the 0 dB data

79 82 dB

input and the 20 kHz-LPF (in the AD725D)

One-bit D/A Converter Analog Characteristics at

Ta = 25°C, VDD= LVDD= RVDD= 3.2 V, VSS= L/RVSS= 0 V

Note: Measured with the normal-speed playback mode in the Sanyo one-bit D/A converter block reference digital attenuator circuit.

Figure 1 Command Input

Figure 2 Subcode Q Output

Figure 3 Subcode Output

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Figure 4 General Port Input Timing

Figure 5 General Port Output Timing

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Description of Pins

Pin Pin

I/O Function

Output pin states

No. Name

during reset 1 DEFI I Defect detection signal (DEF) input. When not used, must be connected to 0 V. — 2 TAI I Test input. Equipped with internal pull-down resistor. Must be connected to 0V. — 3 PDO O Internal VCO control phase comparator output — 4 VV

For the PLL

Internal VCO ground. Must be connected to 0 V. — 5 ISET AI PDO output current adjustment resistor connection — 6 VV

P Internal VCO power supply — 7 FR AI VCO frequency range adjustment — 8 V

P Digital system ground. Must be connected to 0 V. — 9 TESCLK I Test clock input. Must be connected to V

. —

10 TESA I Test operation mode control input. Must be connected to V

. —

11 TESB I Test operation mode control input. Must be connected to V

. —

12 TESC I Test operation mode control input. Must be connected to V

. —

13 TESGB I Test operation mode control input. Must be connected to V

. — 14 TEST5 I Test input. Equipped with internal pull-down resistor. Must be connected to 0 V. — 15 CS I Chip select input. Equipped with internal pull-down resistor. When not controlled, must be connected to 0 V. — 16 TEST1 I Test input. Must be connected to 0 V. — 17 EFMO O For slice EFM signal output Undefined 18 EFMI I level control EFM signal input — 19 TEST2 I Test input. Equipped with internal pull-down resistor. Must be connected to 0 V. — 20 CLV

Disk motor control output. Can have a 3-state output depending on the command.

Low-level output

21 CLV

–

22 V/P O

Low-level output

23 HFL I Track detect signal input. Schmidt input. — 24 TES I Tracking error signal input. Schmidt input. — 25 TOFF O Tracking off output

High-level output 26 TGL O Tracking gain switch output. Gain is increased with low level. Undefined 27 JP

Track jump control output. Can be 3-state output depending on the command.

Low-level output 28 JP

–

29 PCK O EFM data playback clock monitor. 4.3218 MHz during phase lock.

Low-level output 30 FSEQ O Undefined

31 V

P Digital system power supply —

32 ASRES I(I/O) Input mode

33 CONT2 I/O Input mode

Continued on next page.

Rough servo/phase control automatic switching monitor output. If a high level then rough servo mode. If a low level then phase control mode.

Sync signal detect output. A high level when the sync signal detected from the EFM signal matches the internally generated sync signal.

Reset signal input for initializing only the anti-shock control part (i.e. excluding the DSP part). Resets when this pin is low level, and release the reset when this pin is high level. Tie this pin to the low level (i.e., connected to 0 V) if when using software control on the anti-shock part alone through the anti-shock part only reset disable/release command ($F4) or the anti-shock only reset enable/inrush command ($F5). Note: This pin is assigned as the least significant bit of the general I/O port however, use as a general I/O pin is disabled. When the port I/O set command ($DB) is executed, the least significant bit is always “0,” and the output driver is not turned ON.

General I/O pin 2. This controls the commands from the microcontroller. When not used, either set this as an input port and connect to 0 V, or set this as an output port and leave it open.

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Continued from preceding page.

Pin Pin

I/O Description

Output pin states

No. Name

during reset

CONT3/SBCK

I/O Input mode

CONT4/SFSY

I/O Input mode

CONT5/PW

I/O Input mode

37 SBSY O Subcode block sync signal output Undefined 38 TEST3 I Test input. Equipped with an internal pull-down resistor. Must be connected to 0 V. — 39 DOUT O Digital output. EIAJ format. Undefined 40 TEST4 I Test input. Equipped with an internal pull-down resistor. Must be connected to 0 V. —

41 16M/NGJ O Clock output

42 4.2M O 4.2336 MHz output Clock output 43 EFLG O C1, C2, one error, two error error correction monitor output Undefined 44 FSX O 7.35 kHz sync signal output (frequency divided from the crystal oscillator). Undefined 45 EMPH O Deemphasis monitor output. When high level, a deemphasis disk is being played back.

Low-level output 46 C2F O C2 flag output Undefined 47 TOUT O Test output. Under normal operation, this should be left open. Undefined 48 MR1 I

DRAM switch: high : 1M, low : 4M

—

49 MR2 I

1 M: high, low 4 M: low, low 16 M: low, high 4 M X 2: high, high (MR1, MR2)

50 TESD I Test input. Must be connected to 0V. — 51 MUTESL O L channel mute output

High-level output 52 LV

P L channel power supply — 53 LCHO AO L channel output — 54 L/RV

For the one-bit D/A

L/R channel ground. Must be connected to 0 V. —

55 RCHO AO

converter

R channel output —

56 RV

P R channel power supply — 57 MUTER O R channel mute output

High-level output

58 XV

P Crystal oscillator power supply — 59 XOUT O

16.9344 MHz crystal oscillator connection

—

60 XIN I 61 XV

P Crystal oscillator ground. Must be connected to 0 V. — 62 RWC I Read/write control input. Schmidt input. — 63 COIN I Microcontroller command input — 64 CQCK I Input pin for the command input latch clock and the subcode readout clock. Schmitt input. — 65 SQOUT O Subcode Q output Undefined 66 WRQ O Subcode Q output standby output Undefined 67 FMT I Operating mode switch: high: shock proof, low: through. — 68 EMPP O DRAM empty (an RZP pulse is output when the DRAM is empty).

Low-level output

69 RES I External reset input: low reset (all internal blocks are reinitialized). —

Continued on next page.

General I/O pin 3. This controls the commands from the microcontroller. This pin is shared exclusively with the subcode read clock input (SBCK). When not used, either set this as an input port and connect to 0 V, or set this as an output port and leave it open.

General I/O pin 4. This controls the commands from the microcontroller. This pin is shared exclusively with the subcode frame sync signal output (SFSY). When not used, either set this as an input port and connect to 0 V, or set this as an output port and leave it open.

General I/O pin 5. This controls the commands from the microcontroller. This pin is shared, exclusively, with the subcode P, Q, R, S, T, U, V, W output (PW). When not used, either set this as an input port and connect to 0 V, or set this as an output port and leave it open.

Shared function pin that functions either as the 16.9344 MHz output (16M) or as the C2 flag data continuity check start signal (detection start is indicated by a low to high transition). Controlled by microcontroller commands.

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Continued from preceding page.

Pin Pin

I/O Description

Output pin states

No. Name

during reset

70 MMC0 O Remaining DRAM output

Low-level output

71 MMC1 O Remaining DRAM output

Low-level output

72 MMC2 O Remaining DRAM output

Low-level output

73 MMC3 O Remaining DRAM output

Low-level output

74 OVF O DRAM write terminated. (An RZP pulse is output when there is an overflow or a shock.)

Low-level output

75 CNTOK O Data contact point detection complete signal: low→ high: detection complete. (DRAM write start).

High-level output 76 WOK I DRAM write enable signal input: high: write enable. — 77 PAUSE IN I Pause signal input: high: pause. —

AD10/CAS2

O Undefined

79 EMPN O Remaining DRAM alarm output: low: memory low.

Low-level output 80 SHOCK I C2F shock detect pause signal input: low: pause shock detection. — 81 DRAM3 I/O DRAM data bus Input mode 82 DRAM2 I/O DRAM data bus Input mode 83 DRAM1 I/O DRAM data bus Input mode 84 DRAM0 I/O DRAM data bus Input mode 85 OE O DRAM control signal

Low-level output 86 WE O DRAM control signal

High-level output 87 CAS O DRAM control signal Undefined 88 RAS O DRAM control signal Undefined 89 AD9 O DRAM address bus

Low-level output 90 AD8 O DRAM address bus

Low-level output 91 AD7 O DRAM address bus

Low-level output 92 AD6 O DRAM address bus

Low-level output 93 AD5 O DRAM address bus

Low-level output 94 V

P Digital system ground. Must be connected to 0 V. —

95 AD4 O DRAM address bus

Low-level output 96 AD3 O DRAM address bus

Low-level output 97 AD2 O DRAM address bus

Low-level output 98 AD1 O DRAM address bus Undefined 99 AD0 O DRAM address bus Undefined

100 V

P Digital system power supply —

Shared function pin that functions either as a 16M DRAM address output (AD10) or as a DRAM control signal (CAS2) used when 8M of DRAM (two 4M DRAM chips) is used. The function is switched by the DRAM selection pins MR1 and MR2.

Pin Applications

The HF Signal Input Circuit Pin 18: EFMI, Pin 17: EFMO, Pin 1: DEFI, and Pin 20: CLV

When an HF signal is input to the EFMI, an EFM signal (NRZ), sliced at the optimal levels, is obtained. As a countermeasure against defects, when the DEFI pin (Pin 1) is high, the slice level control output EFMO pin (Pin 17) goes to a high impedance state, and the slice level is held. However, this is only enabled when the CLV is in phase-control mode, or in other words, when the V/P pin (Pin 22) is low. This can be structured from a combination with the DEF pin of LA9230/ 40/50 series ICs. * When the EFMI and CLV+signal lines are close to each other

then the error rate due to unnecessary radiation may increase. It is recommended that these two lines be separated by a ground line or by a VDDline as a shield line.

The PLL Clock Playback Circuit Pin 3: PDO, Pin 5: ISET and Pin 7: FR

The VCO circuit is equipped internally, and the PLL circuit is structured using external resistors and external capacitors. The ISET is the reference current for the charge pump. The PDO is the loop filter for the VCO circuit, and the FR is the resistor that determines the frequency range of the VCO. Reference Values

R1 = 68 kΩ C1 = 0.1 µF (standard speed)

C1 = 0.047 µF (2× speed) R2 = 680 Ω C2 = 0.1 µF R3 = 1.2 kΩ

* It is recommended that a carbon coated resistor with a

tolerance of ±5.0% be used for R3.

The VCO Monitor Pin 29: PCK

This is the monitor pin with an average frequency of 4.3218 MHz, which is a 1/2 frequency division from VCO.

The Sync Detect Monitor Pin 30: FSEQ

The EFM signal goes high when the frame sync signal (the true sync signal) from the PCK matches the timing (the interpolated sync signal) generated by the counter. This serves as the sync detect monitor (holding the high level over a single frame).

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HF Signal

Frequency and phase

comparator

Charge pump

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