Sanyo LC78622NE Specifications

Ordering number : EN6015

11999RM (OT) No. 6015-1/31

Overview

The LC78622NE is a CMOS IC that implements the signal processing and servo control required by compact disc players. At the same time as providing an EFM PLL circuit, a 1-bit D/A converter, and an analog low-pass filter the LC78622NE realizes an optimal costperformance tradeoff for low-end players by strictly limiting functionality to basic signal-processing and servo system functionality. The LC78622NE signal-processing system provides demodulation of the EFM signal from the pickup, de-interleaving, error detection and correction, and digital filters that can prove useful in reducing the cost of end products. The LC78622NE servo control system processes servo commands sent from the control microprocessor.

The LC78622NE is an improved version of the LC78622E that adds 8× oversampling digital filters, three generalpurpose output ports (that also have specific shared functions) and the PCCL pin (pin 34). However, some handling of general-purpose ports differ from that of the LC78622E, therefore care must be taken.(Refer to pages 16 and 21).

Functions

• Input signal processing: The LC78622NE takes an HF signal as input, digitizes (slices) that signal at a precise level, converts that signal to an EFM signal, and generates a PLL clock with an average frequency of

4.3218 MHz by comparing the phases of that signal and an internal VCO.

• Precise reference clock and necessary internal timing generation using an external 16.9344 MHz crystal oscillator

• Disk motor speed control using a frame phase difference

signal generated from the playback clock and the reference clock

• Frame synchronization signal detection, protection and interpolation to assure stable data readout

• EFM signal demodulation and conversion to 8-bit symbol data

• Subcode data separation from the EFM demodulated signal and output of that data to an external microprocessor

• Subcode Q signal output to a microprocessor over the serial I/O interface after performing a CRC error check (LSB first)

• Demodulated EFM signal buffering in internal RAM to handle up to ±4 frames of disk rotational jitter

• Demodulated EFM signal reordering in the prescribed order for data unscrambling and de-interleaving

• Error detection, correction, and flag processing (error correction scheme: dual C1 plus dual C2 correction)

• Sets the C2 flags based on the C1 flags and a C2 check, and then performs signal interpolation or muting depending on the C2 flags. The interpolation circuit uses a dual-interpolation scheme. The previous value is held if the C2 flags indicate errors two or more times consecutively.

• Support for command input from a control microprocessor: commands include track jump, focus start, disk motor start/stop, muting on/off and track count (8 bit serial input)

• Built-in digital output circuits.

• Arbitrary track counting to support high-speed data access

• D/A converter outputs with data continuity improved by 8× oversampling digital filters.

• Built-in third-order ∑∆ D/A converters (An analog lowpass filter is built in.)

LC78622NE

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Compact Disc Player DSP

CMOS IC

Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.

• Built-in digital attenuator (8 bits – alpha, 239 steps)

• Built-in digital de-emphasis

• Zero cross muting

• Supports the implementation of a double-speed dubbing function.

• Support for bilingual applications.

• General-purpose I/O ports: 5 pins

Features

• 5 V single-voltage power supply

Package Dimensions

unit: mm

3159-QFP64E

No. 6015-2/31

LC78622NE

14.0

17.2

1.0

1.6

0.15

0.35

0.1

15.6

0.8

3.0max

2.7

14.0

17.2

1.0

1.6

0.8

SANYO: QFP64E (QIP64E)

[LC78622NE]

Equivalent Circuit Block Diagram

No. 6015-3/31

LC78622NE

Pin Assignment

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage V

max VSS– 0.3 to VSS+ 7.0 V

Input voltage V

VSS– 0.3 to VDD+ 0.3 V

Output voltage V

OUT

VSS– 0.3 to VDD+ 0.3 V Allowable power dissipation Pd max 300 mW Operating temperature Topr –20 to +75 °C Storage temperature Tstg –40 to +125 °C

No. 6015-4/31

LC78622NE

Allowable Operating Ranges at Ta = 25°C, VSS= 0 V

Parameter Symbol Conditions min typ max Unit

(1)

, XVDD, LVDD, RVDD, VVDD:

3.6 5.5 V

During normal-speed playback

Supply voltage

(2)

, XVDD, LVDD, RVDD, VVDD:

3.6 5.5 V

During double-speed playback

(1)

DEFI, COIN, RES, HFL, TES, SBCK, RWC, CQCK,

Input high level voltage

TAI, TEST1 to TEST5, CS, CONT1 to CONT5, PCCL

0.7 V

(2) EFMIN 0.6 V

(1)

DEFI, COIN, RES, HFL, TES, SBCK, RWC, CQCK,

Input low level voltage

TAI, TEST1 to TEST5, CS, CONT1 to CONT5, PCCL

0 0.3 V

VIL(2) EFMIN 0 0.4 V

Data setup time t

COIN, RWC: Figure 1 400 ns

Data hold time t

COIN, RWC: Figure 1 400 ns

High level clock pulse width t

SBCK, CQCK: Figures 1, 2 and 3 400 ns

Low level clock pulse width t

SBCK, CQCK: Figures 1, 2 and 3 400 ns

Data read access time t

RAC

SQOUT, PW: Figures 2 and 3 0 400 ns

Command transfer time t

RWC

RWC: Figure 1 1000 ns

Subcode Q read enable time t

SQE

WRQ: Figure 2, with no RWC signal 11.2 ms

Subcode read cycle time t

SFSY: Figure 3 136 µs

Subcode read enable time t

SFSY: Figure 3 400 ns

Port input data setup time t

CSU

CONT1 to CONT5, RWC: Figure 4 400 ns

Port input data hold time t

CHD

CONT1 to CONT5, RWC: Figure 4 400 ns

Port input clock setup time t

RCQ

RWC, CQCK: Figure 4 100 ns

Port output data delay time t

CDD

CONT1 to CONT8, RWC: Figure 5 1200 ns

Input level

(1) EFMIN: Slice level control 1.0 Vp-p

(2) XIN: Capacitor-coupled input 1.0 Vp-p Operating frequency range fop EFMIN 10 MHz Crystal oscillator frequency f

XIN, X

OUT

16.9344 MHz

Electrical Characteristics at Ta = 25°C, VDD= 5 V, VSS= 0 V

Parameter Symbol Conditions min typ max Unit

Current drain I

VDD, XVDD, LVDD, RVDD, VV

25 35 mA

DEFI, EFMIN, COIN, RES, HFL, TES, SBCK,

Input high level current

(1)

RWC, CQCK: TEST1: V

= V

5 µA

(2) TAI, TEST2 to TEST5, CS, PCCL: VIN= VDD= 5.5 V 25 75 µA

DEFI, EFMIN, COIN, RES, HFL, TES, SBCK, RWC,

Input low level current I

CQCK: TAI, TEST1 to TEST5, CS, PCCL: VIN= 0 V

–5 µA

EFMO, CLV

, CLV–, V/P, PCK, FSEQ, TOFF,

(1)

TGL, JP

, JP–, EMPH/CONT6, EFLG, FSX: IOH= –1 mA

4 V

MUTEL/CONT7, MUTER/CONT8, C2F, SBSY, PW,

Output high level voltage

(2) SFSY, WRQ, SQOUT, TST11, 16M, 4.2M, CONT1 to 4 V

CONT5: I

= –0.5 mA

(3) DOUT: IOH= –12 mA 4.5 V

EFMO, CLV

, CLV–, V/P, PCK, FSEQ,

(1) TOFF, TGL, JP+, JP–, EMPH/CONT6, EFLG, FSX: 1 V

= 1 mA

Output low level voltage

MUTEL/CONT7, MUTER/CONT8,

(2)

C2F, SBSY, PW, SFSY, WRQ, SQOUT,

0.4 V

TST11, 16M, 4.2M, CONT1 to CONT5: I

= 2 mA

(3) DOUT: IOH= 12 mA 0.5 V

OFF

(1)

PDO, CLV

, CLV–, JP+, JP–, CONT1 to CONT5:

5 µA

OUT

= V

Output off leakage current

OFF

(2)

PDO, CLV

, CLV–, JP+, JP–, CONT1 to CONT5:

–5 µA

OUT

= 0 V

Charge pump output current

PDOH

PDO: R

ISET

= 68 kΩ 64 80 96 µA

PDOL

PDO: R

ISET

= 68 kΩ –96 –80 –64 µA

No. 6015-5/31

LC78622NE

One-Bit D/A Converter Analog Characteristics

at Ta = 25°C, VDD= LVDD= RVDD= 5 V, VSS= LVSS= RVSS= 0 V

Note: Measured with the normal-speed playback mode in the Sanyo one-bit D/A converter block reference digital attenuator circuit set to EE (hexadecimal).

Parameter Symbol Conditions min typ max Unit

Total harmonic distortion THD + N

LCHO, RCHO; 1 kHz: 0 dB data input,

0.009 0.012 %

using the 20 kHz low-pass filter (AD725D built in) LCHO, RCHO; 1 kHz: –60 dB data input,

Dynamic range DR using the 20 kHz low-pass filter and the A filter 87 90 dB

(AD725D built in) LCHO, RCHO; 1 kHz: 0 dB data input,

Signal-to-noise ratio S/N using the 20 kHz low-pass filter and the A filter 93 95 dB

(AD725D built in)

Crosstalk CT

LCHO, RCHO; 1 kHz: 0 dB data input,

82 84 dB

using the 20 kHz low-pass filter (AD725D built in)

Figure 1 Command Input

No. 6015-6/31

LC78622NE

Figure 2 Subcode Q Output

Figure 4 General-Purpose Port Input Timing

Figure 5 General-Purpose Port Output Timing

Figure 3 Subcode Output

No. 6015-7/31

LC78622NE

Pin Functions

Pin No. Symbol I/O Function

Output pin states

during a reset 1 DEFI I Defect detection signal (DEF) input. (Must be connected to 0 V when unused.) — 2 TAI I Test input. A pull-down resistor is built in. Must be connected to 0 V. — 3 PDO O Internal VCO control phase comparator output — 4 VV

–

PLL pins

Internal VCO ground. Must be connected to 0 V. — 5 ISET AI PDO output current adjustment resistor connection — 6 VV

– Internal VCO power supply — 7 FR AI VCO frequency range adjustment — 8 V

– Digital system ground. Must be connected to 0 V. — 9 EFMO O

Slice level control

EFM signal output Undefined 10 EFMIN I EFM signal input — 11 TEST2 I Test input. A pull-down resistor is built in. Must be connected to 0 V. — 12 CLV

Disc motor control output.

Low-level output

13 CLV

–

O Three-value output is also possible when specified by microprocessor command.

Low-level output

14 V/P O

Rough servo/phase control automatic switching monitor output. Outputs a high level during rough servo and

Low-level output

a low level during phase control. 15 HFL I Track detection signal input. This is a Schmitt input. — 16 TES I Tracking error signal input. This is a Schmitt input. — 17 TOFF O Tracking off output

High-level output 18 TGL O Tracking gain switching output. Increase the gain when low. Undefined 19 JP

Track jump output.

Low-level output

20 JP

–

O Three-value output is also possible when specified by microprocessor command.

Low-level output

21 PCK O EFM data playback clock monitor. Outputs 4.3218 MHz when the phase is locked.

Low-level output

22 FSEQ O

Synchronization signal detection output. Outputs a high level when the synchronization signal detected from

Undefined

the EFM signal and the internally generated synchronization signal agree.

23 V

– Digital system power supply. — 24 CONT1 I/O General-purpose I/O pin 1 Input 25 CONT2 I/O General-purpose I/O pin 2

Controlled by serial data commands from the microprocessor. Any of these

Input 26 CONT3 I/O General-purpose I/O pin 3 that are unused must be either set up as input ports and connected to 0 V, Input 27 CONT4 I/O General-purpose I/O pin 4

output ports and set up as left open.

Input 28 CONT5 I/O General-purpose I/O pin 5 Input 29 EMPH/CONT6 O De-emphasis monitor pin. A high level indicates playback of a emphasis disk./general-purpose I/O port 6

Low-level output 30 C2F O C2 flag output Undefined 31 DOUT O Digital output. (EIAJ format) Undefined 32 TEST3 I Test input. A pull-down resistor is built in. Must be connected to 0 V. — 33 TEST4 I Test input. A pull-down resistor is built in. Must be connected to 0 V. —

General-purpose I/O command identification pin. A pull-down resistor is built in. If only the same functions as those provided by the LC78622E are used, this pin must be left open or

34 PCCL I connected to 0 V. —

High: Only the general-purpose I/O port commands are allowed. Low: All commands are allowed.

MUTEL/CONT7

O Left channel mute output/general-purpose I/O port 7

High-level output

36 LV

–

Left channel

Left channel power supply — 37 LCHO O one-bit D/A converter Left channel output — 38 LV

– Left channel ground. Must be connected to 0 V. —

39 RV

– Right channel ground. Must be connected to 0 V. —

40 RCHO O

Right channel

Right channel output — 41 RV

– one-bit D/A converter Right channel power supply —

MUTER/CONT8

O Right channel mute output/general-purpose I/O port 8

High-level output

43 XV

– Crystal oscillator power supply. —

44 X

OUT

Connections for a 16.9344 MHz crystal oscillator element

—

45 X

I —

46 XV

– Crystal oscillator ground. Must be connected to 0 V. — 47 SBSY O Subcode block synchronization signal output Undefined 48 EFLG O C1, C2, single and double error correction monitor pin Undefined 49 PW O Subcode P, Q, R, S, T, U, V and W output Undefined 50 SFSY O Subcode frame synchronization signal output. This signal falls when the subcodes are in the standby state. Undefined

Continued on next page.

No. 6015-8/31

LC78622NE

Continued from preceding page.

Note: The same potential must be supplied to all power supply pins, i.e., VDD, VVDD, LVDD, RVDD, and XVDD.

Pin Applications

1. HF Signal Input Circuit; Pin 10: EFMIN, pin 9: EFMO, pin 1: DEFI, pin 12: CLV

An EFM signal (NRZ) sliced at an optimal level can be acquired by inputting the HF signal to EFMIN. The LC78622NE handles defects as follows. When a high level is input to the DEFI pin (pin 1), EFMO (pin 9) pins (the slice level control outputs) go to the high-impedance state, and the slice level is held. However, note that this function is only valid in CLV phase control mode, that is, when the V/P pin (pin 14) is low. This function can be used in combination with the LA9240M and LA9241M DEF pins. Note: If the EFMIN and CLV+signal lines are too close to each

other, unwanted radiation can result in error rate degradation. We recommend laying a ground or V

shield line between these two lines.

2. PLL Clock Generation Circuit; Pin 3: PDO, pin 5: ISET, pin 7: FR, pin 21: PCK Since the LC78622NE includes a VCO circuit, a PLL circuit can be formed by connecting an external RC circuit. ISET is the charge pump reference current, PDO is the VCO circuit loop filter, and FR is a resistor that determines the VCO frequency range. (Reference values) R1 = 68 kΩ, C1 = 0.1 µF R2 = 680 Ω, C2 = 0.1 µF R3 = 1.2 kΩ

Pin No. Symbol I/O Function

Output pin states

during a reset 51 SBCK I Subcode readout clock input. This is a Schmitt input. (Must be connected to 0 V when unused.) — 52 FSX O Output for the 7.35 kHz synchronization signal divided from the crystal oscillator Undefined 53 WRQ O Subcode Q output standby output Undefined 54 RWC I Read/write control input. This is a Schmitt input. — 55 SQOUT O Subcode Q output Undefined 56 COIN I Command input from the control microprocessor — 57 CQCK I Input for both the command input clock and the subcode readout clock. This is a Schmitt input. — 58 RES I Chip reset input. This pin must be set low briefly after power is first applied. — 59 TST11 O Test output. Leave open. (Normally outputs a low level.)

Low-level output 60 16M O 16.9344 MHz output. Clock output 61 4.2M O 4.2336 MHz output Clock output 62 TEST5 I Test input. A pull-down resistor is built in. Must be connected to 0 V. — 63 CS I Chip select input. A pull-down resistor is built in. Must be connected to 0 V if not controlled. — 64 TEST1 I Test input. No pull-down resistor. Must be connected to 0 V. —

No. 6015-9/31

LC78622NE

3. VCO Monitor; Pin 21: PCK PCK is a monitor pin that outputs an average frequency of 4.3218 MHz, which is divided from the VCO frequency.

4. Synchronization Detection Monitor; Pin 22: FSEQ Pin 22 goes high when the frame synchronization (a positive polarity synchronization signal) from the EFM signal read in by PCK and the timing generated by the counter (the interpolation synchronization signal) agree. This pin is thus a synchronization detection monitor. (It is held high for a single frame.)

5. Servo Command Function; Pin 54: RWC, pin 56: COIN, pin 57: CQCK Commands can be executed by setting RWC high and inputting commands to the COIN pin in synchronization with the CQCKclock. Note that commands are executed on the falling edge of RWC.

Focus start Track jump Muting control One-byte commands Disk motor control Miscellaneous control

Track check Two-byte command (RWC set twice)

Digital attenuator General-purpose I/O, E/D

Two-byte commands (RWC set once)

• One-byte commands

• Two-byte commands (RWC set twice: For track checking)

No. 6015-10/31

LC78622NE

• Two-byte commands (RWC set once: Sets up the digital attenuation and the general-purpose I/O ports)

• Command noise rejection

This command reduces the noise on the CQCK clock signal. While this is effective for noise pulses shorter than 500 ns, the CQCK timings tWL, tWH, and tSU, must be set for at least 1 µs.

6. CLV Servo Circuit; Pin 12: CLV+, pin 13: CLV–, pin 14: V/P

The CLV+pin provides the signal that accelerates the disk in the forward direction and the CLV–pin provides the signal that decelerates the disk. Commands from the control microprocessor select one of four modes; accelerate, decelerate, CLV and stop. The table below lists the CLV+and CLV–outputs in each of these modes.

Note: CLV servo control commands can set the TOFF pin low only in CLV mode. That pin will be at the high level

at all other times. Control of the TOFF pin by microprocessor command is only valid in CLV mode.

MSB LSB Command RES = low

1 1 1 0 1 1 1 1 COMMAND INPUT NOISE REDUCTION MODE 1 1 1 0 1 1 1 0 RESET NOISE EXCLUSION MODE

●●

MSB LSB Command RES = low

0 0 0 0 0 1 0 0 DISC MOTOR START (accelerate) 0 0 0 0 0 1 0 1 DISC MOTOR CLV (CLV) 0 0 0 0 0 1 1 0 DISC MOTOR BRAKE (decelerate) 0 0 0 0 0 1 1 1 DISC MOTOR STOP (stop)

●●

Mode CLV

CLV

–

Accelerate High Low Decelerate Low High CLV

Pulse output Pulse output

Stop Low Low

+ 21 hidden pages