Ordering number : EN*4818
93098HA (OT) / N1594TH (OT) No. 4818-1/18
LC7861KE
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
Digital Signal Processor for
Compact Disc Players
CMOS LSI
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
Overview
The LC7861KE is a CMOS LSI that implements the signal
processing and servo control required by compact disk
players, laser disks, CD-V, CD-I and related products.
The LC7861KE provides several types of signal
processing to reduce the cost of CD player units, including
demodulation of the optical pickup EFM signal, deinterleaving and error detection and correction. It also
processes a rich set of servo system commands sent from
the control microprocessor. It can directly interface to the
dedicated serial inputs provided by the Sanyo LC78815
and LC78816 D/A converters.
Functions
• Input signal processing: The LC7861KE takes an HF
signal as input, digitizes (slices) that signal at a precise
level, converts that signal to an EFM signal, and
generates a PLL clock with an average frequency of
4.3218 MHz by comparing the phases of that signal and
a VCO output.
• Precise reference clock and necessary internal timing
generation using an external 16.9344 MHz crystal
oscillator
• Disk motor speed control using a frame phase difference
signal generated from the playback clock and the
reference clock
• Frame synchronization signal detection, protection and
interpolation to assure stable data readout
• EFM signal demodulation and conversion to 8-bit
symbol data
• Subcode data separation from the EFM demodulated
signal and output of that data to an external
microprocessor
• Subcode Q signal output to a microprocessor over the
serial interface after performing a CRC error check
• Demodulated EFM signal buffering in internal RAM to
handle up to ±4 frames of disk rotational jitter
• Demodulated EFM signal reordering in the prescribed
order for data unscrambling and de-interleaving
• Error detection, correction, and flag processing (dual
error correction scheme: C1 plus dual C2 correction)
• The LC7861KE sets the C2 flags based on the C1 flag
and a C2 check, and then performs signal interpolation
or previous value hold depending on the C2 flag. The
interpolation circuit uses a quadruple interpolation
scheme. The circuit holds the previous value for up to
four consecutive C2 flags.
• Support for command input from a control microprocessor: commands include track jump, focus start,
disk motor start/stop, muting on/off and track count
(8-bit serial input)
• Built-in digital output circuits
• Arbitrary track counting to support high-speed data
access
• Zero cross muting
• Support for double speed dubbing
• Complete support for CD-ROM products. The
LC7861KE directly interfaces with the Sanyo LC89510
and can also handle CD-ROM XA applications.
• Output signals for use by external D/A converters to
improve the output data continuity by oversampling and
digital filtering
Features
• Compact and space-saving 64-pin QIP package
• Silicon-gate CMOS design (low power dissipation)
• Single 5 V power supply (suitable for portable sets)
• DEMO pin for improved operability in adjustment
Preliminary
Equivalent Circuit Block Diagram
Pin Assignment
No. 4818-2/18
LC7861KE
SANYO: QFP64E
[LC7861KE]
Package Dimensions
unit: mm
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V
Allowable Operating Ranges at Ta = 25°C, V
SS
= 0 V
Electrical Characteristics at Ta = 25°C, V
SS
= 0 V, VDD= 5 V
No. 4818-3/18
LC7861KE
Parameter Symbol Conditions Ratings Unit
Maximum supply voltage V
DD
max VSS– 0.3 to +7.0 V
Input voltage V
IN
VSS– 0.3 to VDD+ 0.3 V
Output voltage V
OUT
VSS– 0.3 to VDD+ 0.3 V
Allowable power dissipation Pd max 300 mW
Operating temperature Topr –30 to +75 °C
Storage temperature Tstg –40 to +125 °C
Parameter Symbol Conditions
Ratings
Unit
min typ max
Supply voltage V
DD
V
DD
4.5 5.5 V
V
IH
(1) TEST1 to 5, AI, FZD, HFL, DEMO, DFOFF, M/L, RES 0.7 V
DD
V
DD
V
Input high level voltage
V
IH
(2) SBCK, RWC, COIN, CQCK, CS 2.2 V
DD
V
V
IH
(3) EFMIN 0.6 V
DD
V
DD
V
V
IH
(4) TES 0.8 V
DD
V
DD
V
V
IL
(1) TEST1 to 5, AI, FZD, HFL, DEMO, DFOFF, M/L, RES V
SS
0.3 V
DD
V
Input low level voltage
V
IL
(2) SBCK, RWC, COIN, CQCK, CS V
SS
0.8 V
V
IL
(3) EFMIN V
SS
0.4 V
DD
V
V
IL
(4) TES V
SS
0.2 V
DD
V
Data setup time t
set up
COIN, RWC: Figure 1 400 ns
Data hold time t
hold
RWC: Figure 1 400 ns
High level clock pulse width t
WøH
SBCK, CQCK: Figures 1, 2 and 3 400 ns
Low level clock pulse width t
WøL
SBCK, CQCK: Figures 1, 2 and 3 400 ns
Data read access time t
RAC
Figures 2 and 3 0 400 ns
Command output time t
RWC
RWC: Figure 1 1000 ns
Sub-Q read enable time t
SQE
Figure 2, no RWC signal 11.2 ms
Subcode read cycle t
sc
Figure 3 136 µs
Subcode read enable t
se
Figure 3 400 ns
Crystal oscillator frequency fX’tal X
IN
, X
OUT
16.9344 MHz
Operating frequency range
fop (1) AI 2.0 20 MHz
fop (2) EFMIN: V
IN
≥ 1 Vp-p 10 MHz
Parameter Symbol Conditions
Ratings
Unit
min typ max
Supply current I
DD
17 30 mA
I
IH
(1)
AI, EFMIN, FZD, TES, SBCK, COIN, CQCK, RES,
5µA
Input high level current
HFL, RWC, M/L: V
IN
= V
DD
IIH(2) TEST1 to 5, DEMO, TESTA, CS: VIN= VDD= 5.5 V 25 75 µA
Input low level current I
IL
AI, EFMIN, FZD, TES, SBCK, COIN, CQCK, RES,
–5µA
HFL, RWC, M/L: V
IN
= V
SS
AO, PDO, EFMO, EFMO, CLV+, CLV–, FOCS, FSEQ,
V
OH
(1) PCK, TOFF, TGL, THLD, JP+, JP–, EMPH, EFLG, VDD– 1V
FSX, V/P: I
OH
= –1 mA
Output high level voltage
V
OH
(2) DOUT: IOH= –12 mA VDD– 0.5 V
LASER, SQOUT, 16M, 4.2M, CONT, SMP, SMP1,
V
OH
(3)
SMP2, LRCLK, WRQ, C2F, DFOUT, DACLK, SFSY,
VDD– 1V
LRSY, SBSY, CK2, PW, ROMOUT, C2FCLK:
I
OH
= –0.5 mA
Continued on next page.
Continued from preceding page.
Wave Form
Figure 1 Command Input
Figure 2 Subcode Q Output
Figure 3 Subcode Output
No. 4818-4/18
LC7861KE
Parameter Symbol Conditions
Ratings
min typ max
Unit
AO, PDO, EFMO, EFMO, CLV
+
, CLV–, FOCS, FSEQ,
V
OL
(1) PCK, TOFF, TGL, THLD, JP+, JP–, EMPH, EFLG, 1 V
FSX, V/P: I
OL
= 1 mA
V
OL
(2) DOUT: IOL= 12 mA 0.5 V
Output low level voltage LASER, SQOUT, 16M, 4.2M, CONT, SMP, SMP1,
V
OL
(3)
SMP2, LRCLK, WRQ, DFOUT, DACLK, SFSY, CK2,
0.4 V
PW, ROMOUT, C2FCLK, CF2, LRSY, SBSY:
I
OL
= 2 mA
V
OL
(4) FST: IOL= 5 mA 0.75 V
Output off leakage current
I
OFF
(1) PDO, FST: VOH= V
DD
5µA
I
OFF
(2) PDO, FST: VOL= V
SS
–5µA
Pin Functions
No. 4818-5/18
LC7861KE
No. Name I/O Description
1 TEST1 I LSI test pin. Normally left open.
2AO O
3AI I
4 PDO O
5V
SS
— GND
6 EFMO O
7 EFMO O
8 EFMIN I
9 TEST2 I LSI test pin. Normally left open.
10 CLV
+
O
Disk motor control output.
11 CLV
–
O
12 V/P O Outputs a high level during CLV rough servo and a low level during phase control.
13 FOCS O
14 FST O
15 FZD I
16 HFL I
17 TES I
18 PCK O
19 FSEQ O
20 TOFF O
21 TGL O
22 THLD O
23 TEST3 I LSI test pin. Normally left open.
24 V
DD
— +5 V
25 JP
+
O
26 JP
–
O
27 DEMO I Sound output function for end product adjustment manufacturing steps.
28 TEST4 I LSI test pin. Normally left open.
29 EMPH O De-emphasis is required when high.
30 DFOFF I Digital filter on/off switch. Filtering is turned off on a high level input.
31 SMP2 O
32 SMP1 O
33 LRCLK O
34 SMP O
35 DFOUT O
36 DACLK O
37 DFIN O LSI test pin. Normally left open.
38 LRSY O
39 CK2 O
40 ROMOUT O CD-ROM application output signals
41 C2FCLK O
42 C2F O
43 DOUT O Digital output
44 SBSY O Subcode block synchronization signal
45 EFLG O C1, C2, single and double error correction monitor pin
46 PW O
47 SFSY O
48 SBCK I
49 FSX O 7.35 kHz synchronization signal output
50 WRQ O
51 RWC I
52 SQOUT O
Inputs for the LA9210 internal VCO output. (8.6436 MHz)
Set up PDO so that the frequency increases when the EFM signal and the phase output are positive.
Supply an HF signal with a 1 to 2 Vp-p level to EFMIN. EFMO and EFMO output EFM signals with opposite phases
that passed through an amplitude limiter circuit. These are used for slice level control.
FOCS outputs a high level when the focus servo is off. The lens is lowered by FST, and when FOCS is high the lens is
raised gradually. FOCS is reset when an FZD input occurs. These are used for focus pull-in.
PCK is the 4.3218 monitor pin.
It outputs a high level when the synchronization (positive FS) detected from the EFM signal matches the counter
synchronization (interpolation FS). (The output is latched for a single frame.)
The LC7861KE outputs a kick pulse from JP
+
and JP–in response to a track jump command. A track jump of the
specified number of tracks (1, 4, 16, 32, 64, and 128) is performed.
Outputs for an external D/A converter. These include a latch signal, an L/R switching signal, and a sample and hold
signal.
SFSY is the subcode frame synchronization signal. The P, Q, R, S, T, U, V and W subcodes can be read out by
applying 8 clock cycles to SBCK.
WRQ goes high when the subcode Q data passes the CRC check. An external controller can read out data from
SQOUT by monitoring this pin and applying a CQCK signal. Set M/L to low when data is required LSB first.
Continued on next page.
Continued from preceding page.
Pin Applications
1. HF signal input circuit; Pin 8: EFMIN, pin 7: EFMO, pin 6: EFMO
An EFM signal (NRZ) with an optimal slice level can be acquired by inputting the HF signal to EFMIN.
2. PLL clock generation circuit; Pin 4: PDO, Pin 3: AI, Pin 2: AO
A VCO can be constructed by combining the LC7861KE with the Sanyo LA9210M. The PDO pin swings in the
positive direction when the VCO phase lags.
No. 4818-6/18
LC7861KE
No. Name I/O Description
53 COIN I
54 CQCK I
55 RES I This pin must be set low briefly after power is first applied.
56 M/L I
57 LASER O Output pin controllable by serial data sent from the microprocessor.
58 16M O 16.9344 MHz output pin
59 4.2M O 4.2336 MHz output pin
60 CONT O Output pin controllable by serial data sent from the microprocessor.
61 TEST5 I LSI test pin. Normally left open.
62 CS I Chip select pin. The LC7861KE becomes active when this pin is low. (A pull-down resistor is built-in.)
63 X
IN
I
Connections for a 16.9344 MHz crystal oscillator
64 X
OUT
O
The control microprocessor can send commands to the LC7861KE by setting RWC high and then sending command
data synchronized with CQCK. It is also possible to read out the TOC memory data by sending CQCK from the
SQOUT pin by command switching.
3. 1/2 VCO; Pin 18: PCK
PCK is a monitor pin that outputs an average frequency of 4.3218 MHz, which is the VCO frequency divided by two.
4. Synchronization detection monitor; Pin 19: FSEQ
Pin 19 goes high when the frame synchronization (a positive polarity synchronization signal) from the EFM signal
read in by PCK and the timing generated by the counter (the interpolation synchronization signal) agree. This pin is a
synchronization detection monitor. (It is held high for a single frame.)
5. CLV servo circuit; Pin 10: CLV
+
, pin 11: CLV–, pin 12: V/P
The CLV
+
pin provides the signal that accelerates the disk in the forward direction and the CLV–pin provides the
signal that decelerates the disk. Commands from the control microprocessor select one of four modes; accelerate,
decelerate, CLV and stop. The table below lists the CLV
+
and CLV–outputs in each of these modes.
Note: *In CLV mode the LC7861KE detects the disk speed from the HF signal and provides proper linear speed
using several different control schemes by switching the DSP internal modes. The PWM period is 7.35 kHz,
the 1/64 duty period is 1.114s, and V/P outputs a high level during rough servo and a low level during phase
control.
Note: After a CLV servo control command, the TOFF pin will be at the low level only for CLV mode, and will be
high for all other modes. Controlling the TOFF pin by microprocessor command is only possible in CLV mode.
No. 4818-7/18
LC7861KE
MSB LSB Command RES = low
00000100 DISC MOTOR START (accelerate)
00000101 DISC MOTOR CLV (CLV)
00000110 DISC MOTOR BRAKE (decelerate)
00000111 DISC MOTOR STOP (stop)
o
Mode CLV
+
CLV
–
Accelerate High Low
Decelerate Low High
CLV **
Stop Low Low
Internal mode CLV
+
CLV
–
V/P
Rough servo (velocity too low) High Low High
Rough servo (velocity too high) Low High High
Phase control (PCK locked) PWM PWM Low
Low speed (no HF signal) 1/64 duty Low High
6. Subcode P, Q, and R to W output circuit; Pin 46: PW, pin 44: SBSY, pin 47: SFSY, pin 48: SBCK
PW is the subcode signal output pin, and all the codes, P, Q, and R to W can be read out by sending eight clocks to
the SBCK pin within 136 µs after the fall of SFSY. The signal that appears on the PW pin changes on the falling
edge of SBCK. If a clock is not applied to SBCK, the P code will be output from PW. SFSY is a signal that is output
for each subcode frame cycle, and the rising edge of this signal indicates standby for the output of the subcode
symbol (P to W). Subcode data P is output on the fall of this signal.
SBSY is a signal output for each subcode block. This signal goes high for the S0 and S1 synchronization signals. The
fall of this signal indicates the end of the subcode synchronization signals and the start of the data in the subcode
block. (EIAJ format)
7. Subcode Q output circuit; Pin 50: WRQ, pin 51: RWC, pin 52: SQOUT, pin 54: CQCK, pin 56: M/L, pin 62: CS
Subcode Q can be read from the SQOUT pin by applying a clock to the CQCK pin.
Of the eight bits in the subcode, the Q signal is used for song (track) access and display. The WRQ will be high only
if the data passed the CRC error check and the subcode Q format internal address is 1*. The control microprocessor
can read out data from SQOUT in the order shown below by detecting this high level and applying CQCK. When
CQCK is applied the DSP disables register update internally. The microprocessor should give update permission by
setting RWC high briefly after reading has completed. WRQ will fall to low at this time. Since WRQ falls to low
11.2 ms after going high, CQCK must be applied during the high period. Data can be read out in an LSB first format
if the M/L pin is set low, and in an MSB first format if that pin is set low.
Note: * That state will be ignored if an address free command is sent. This is provided to handle CDV applications.
No. 4818-8/18
LC7861KE
MSB LSB Command RES = low
00001001 ADDRESS FREE
10001001 ADDRESS 1
o
10001110 OSC ON
o
10001101 OSC OFF
Note: 1. Normally, the WRQ pin indicates the subcode Q standby state. However, it is used for a different
monitoring purpose in track count mode. (See the item on track counting for details.)
2. The LC7861KE becomes active when the CS pin is low, and data is output from the SQOUT pin. When
the CS pin is high, the SQOUT pin goes to the high impedance state.
3. The “OSC OFF” command turns off the VCO and the crystal oscillator.
8. Servo command function; Pin 51: RWC, pin 53:COIN, pin 54: CQCK, pin 62: CS
Instructions can be input to the LC7861KE by setting RWC high and sending commands in synchronization with the
CQCK. The LC7861KE is basically upwardly compatible with the earlier LC7860K and LC7863K with respect to
the control microprocessor. The commands can be classified as follows. New commands not supported by the earlier
LC7860K and LC7863K are marked with a “
o
” in the command table.
Focus start
Track jump
Mute control 1-byte commands
Disc motor control
Other control commands
Track count 2-byte command
• One-byte commands
• Two-byte commands
Commands are executed starting at the fall of the RWC signal.
No. 4818-9/18
LC7861KE
9. Focus servo circuit; Pin 13: FOCS, pin 14: FST, pin 15: FZD, pin 57: LASER
Commands
When a focus start instruction (either FOCUS START #1 or FOCUS START #2) is input as a servo command, first
the charge on capacitor C1 is discharged by FST and the objective lens is lowered. Next, the capacitor is charged by
FOCS, and the lens is slowly raised. FZD falls when the lens reaches the focus point. When this signal is received,
FOCS is reset and the focus servo turns on. After sending the command, the microprocessor should check DRF to
confirm focus before proceeding to the next part of the program. If focus is not achieved by the time C1 is fully
charged, the microprocessor should issue another focus command and iterate the focus servo operation.
• LASER control
• Focus start (Values in parentheses are for the LASER START #2 command. The only difference is in the FST low
period.)
— An FZD falling edge will not be accepted during the period that FST is low.
— After issuing a focus start command, initialization will be performed if RWC is set high. Therefore, do not
issue the next command during focus start until the focus coil drive S curve has completed.
— When focus cannot be achieved (i.e., when FZD does not go low) the FOCS signal will remain in the high
state, so the microprocessor should initialize the system by issuing a NOTHING command.
— When the RESET pin is set low, the LASER pin is set high directly.
— Focus start using the DEMO coil executes a mode #1 focus start.
No. 4818-10/18
LC7861KE
MSB LSB Command RES = low
00001000 FOCUS START #1
10100010 FOCUS START #2
00001010 LASER ON
10001010 LASER OFF
o
00000000 NOTHING
10. Track jump circuit; Pin 16: HFL, pin 17: TES, pin 20: TOFF, pin 21: TGL, pin 22: THLD, pin 25: JP+, pin 26: JP
–
When the LC7861KE receives a track jump instruction as a servo command, it first generates accelerating pulses
(period a) and next generates deceleration pulses (period b). The passage of the braking period (period c) completes
the specified jump. During the braking period, the LC7861KE detects the beam slip direction from the TES and HFL
inputs. TOFF is used to cut the components in the TE signal that aggravate slip. The jump destination track is
captured by increasing the servo gain with TGL. In all the disk motor control operations, the TOFF pin only goes low
during CLV mode, and will be high during the start, stop, and brake operations. Note that the TOFF pin can be
turned on and off independently by microprocessor issued commands. However, this function is only valid when disk
motor control is in CLV mode. The table lists the relationships between accelerating pulses, deceleration pulses and
the braking period.
No. 4818-11/18
LC7861KE
MSB LSB Command RES = low
10100000 TRACK JUMP(earlier version)
o
10100001 TRACK JUMP(new command)
10001100 TRACK JUMP BRAKE
00001111 TOFF
10001111 TON
o
00010001 1 TRACK JUMP IN #1
00010010 1 TRACK JUMP IN #2
00110001 1 TRACK JUMP IN #3
00010011 4 TRACK JUMP IN
00010100 16 TRACK JUMP IN
00110000 32 TRACK JUMP IN
00010101 64 TRACK JUMP IN
00010111 128 TRACK JUMP IN
00011001 1 TRACK JUMP OUT #1
00011010 1 TRACK JUMP OUT #2
00111001 1 TRACK JUMP OUT #3
00011011 4 TRACK JUMP OUT
00011100 16 TRACK JUMP OUT
00111000 32 TRACK JUMP OUT
00011101 64 TRACK JUMP OUT
00011111 128 TRACK JUMP OUT
00010110 256 TRACK CHECK
Note: 1. As indicated in the table, actuator signals are not output during the 256 TRACK CHECK function. This is
a mode in which the TES signal is counted in the TRACKING LOOP OFF state. Therefore, feed motor
forwarding is required.
2. The servo command register is automatically reset after the track jump sequence (a, b, c) completes.
3. If another track jump command is issued during a track jump operation, the content of that new command
will be executed starting immediately.
4. The maximum braking time (period c) has been changed from the 17 ms of the earlier LC7861NE to 100 ms
in the LC7861KE.
11. Track counting circuit; Pin 16: HFL, pin 17: TES, pin 20: TOFF
The LC7861KE will count the specified number of tracks when the microprocessor sends an arbitrary binary value in
the range 16 to 254 after issuing either a track count in or a track count out command. The TOFF pin will output a
high level during the track count operation and the tracking loop will be turned off. Therefore, feed motor forwarding
is required.
No. 4818-12/18
LC7861KE
Standard track jump mode New track jump mode
Command
abcabc
1 TRACK JUMP IN (OUT) #1 233 µs 233 µs 100 ms 233 µs 233 µs 100 ms
1 TRACK JUMP IN (OUT) #2 0.5-track jump 233 µs 100 ms 0.5-track jump a period 100 ms
1 TRACK JUMP IN (OUT) #3 0.5-track jump 233 µs Does not occur 0.5-track jump a period Does not occur
4 TRACK JUMP IN (OUT) 2-track jump 466 µs 100 ms 2-track jump a period 100 ms
16 TRACK JUMP IN (OUT) 9-track jump 7-track jump 100 ms 9-track jump a period 100 ms
32 TRACK JUMP IN (OUT) 18-track jump 14-track jump 100 ms 18-track jump 14-track jump 100 ms
64 TRACK JUMP IN (OUT) 36-track jump 28-track jump 100 ms 36-track jump 28-track jump 100 ms
128 TRACK JUMP IN (OUT) 72-track jump 56-track jump 100 ms 72-track jump 56-track jump 100 ms
TOFF goes high after 256 tracks are TOFF goes high after 256 tracks are
256 TRACK CHECK jumped. The a and b pulses are not 100 ms jumped. The a and b pulses are not 100 ms
output. output.
TRACK JUMP BRAKE There are no a or b periods. 100ms There are no a or b periods. 100 ms
MSB LSB Command RES = low
11110000 TRACK COUNT IN
11111000 TRACK COUNT OUT
11111111 TWO-BYTE COMMAND RESET
o
10001100 TRACK JUMP BRAKE
Note: 1. When the desired track count is input in binary, the track count operation is started by the fall of RWC.
2. When a track count in/out command is issued the function of the WRQ signal switches from the normal
mode subcode Q standby monitor function to a track count monitor function. This signal goes high when
the track count is half completed, and goes low when the count finishes. The control microprocessor should
monitor this signal to determine when the track count completes.
3. If a two-byte command reset command is not issued, the track count operation will be repeated. That is, to
skip over 20,000 tracks, issue a track count 200 command once, and then count the WRQ signal 100 times.
4. After performing a track count operation, use the brake command to have the pickup lock onto the track.
The track count operations in items 10 and 11 basically count the TES signal from the LA9210. The following two
clocks are provided internally in the LC7861KE as track counting clocks. To use the earlier track count function,
initialize the LC7861KE with a 23H command when power is first applied.
The earlier track count function uses the TES signal directly as the internal track counter clock.
To reduce counting errors resulting from noise on the rising and falling edges of the TES signal, the new track count
function prevents noise induced errors by using the combination of the TES and HFL signals, and implements a more
reliable track count function. However, dirt and scratches on the disk can result in HFL signal dropouts that may
result in missing track count pulses. Thus care is required when using this function.
12. Adjustment process sound output function; Pin 27: DEMO
By setting this pin high, muting can be set to 0 dB, the disk motor can be set to CLV, and a focus start operation can
be performed, even without issuing any commands from the control microprocessor. Also, since the LASER pin
becomes active, if the mechanism and servo systems are complete, sound can be produced without the presence of a
microprocessor.
No. 4818-13/18
LC7861KE
MSB LSB Command RES = low
00100010
NEW TRACK COUNT FUNCTION
o
(using the TES/HFL combination)
00100011
EARLIER TRACK COUNT FUNCTION
(directly counts the TES signal)
13. Reset circuit; Pin 55: RES
When power is first applied, this pin should be briefly set low and then set high. This will set the muting to –∞ dB
and stop the disk motor.
14. De-emphasis ON/OFF; Pin 29: EMPH
The preemphasis on/off bit in subcode Q control information is output from the EMPH pin. De-emphasis should be
performed when this signal is high.
15. Error flag output; Pin 45: EFLG, pin 49: FSX
The FSX signal is generated by dividing the crystal oscillator clock, and is a 7.35 kHz frame synchronization signal.
The error correction state for each frame is output from EFLG. The playback OK/NG state can be easily determined
from the extent of the high level that appears here.
16. Crystal clock oscillator; Pin 63: X
IN
, pin 64: X
OUT
No. 4818-14/18
LC7861KE
Constant linear velocity servo START BRAKE CLV
Muting control 0 dB –12 dB
Q subcode address conditions Address free
Laser control ON (low) (high)
Track jump mode New
Track count mode Standard
New
Standard
OFF
Address 1
∞
STOP
MSB LSB Command RES = low
10001110 OSC ON
o
10001101 OSCOFF
11000001 DOUBLE SPEED MODE
11000010 NORMAL MODE
o
01100000 VCO 8M
o
01100001 VCO 16M
The clock that is used as the time base is
generated by connecting a 16.9344 MHz crystal
oscillator between these pins. This oscillator can
be turned on and off under command control.
(The OSC OFF command turns off both the VCO
and crystal oscillators.)
Also, the LC7861KE can be set up to handle
double speed operation under command control.
The table lists the relationships between the
crystal and VCO oscillators.
Crystal Clock Oscillator Recommended Values
Note: Since the conditions on the circuit board actually used will vary, the values of the load capacitances Cin and Cout must be verified on the circuit
board actually used.a
17. D/A converter interface; Pin 30: DFOFF, pin 34: SMP, pin 33: LRCLCK, pin 35: DFOUT, pin 36: DACLK, pin 32:
SMP1, pin 31: SMP2
Data for the D/A converter is output MSB first from DFOUT synchronized with the falling edge of DACLK.
Note: DACLK = 4.2336 MHz (when DFOFF is low)
DACLK = 2.1168 MHz (when DFOFF is high)
No. 4818-15/18
LC7861KE
VCO playback speed Mode 8M Mode 16M
Normal speed mode Double speed mode Normal speed mode Double speed mode
After reset
o
———
AI pin external input (8M VCO) 8.6436 MHz
AI pin external input (17M VCO) 17.2872 MHz 17.2872 MHz
AI pin external input (LA9210) 8.6436 MHz 17.2872 MHz
PCK monitor output 4.3218 MHz 8.6436 MHz 4.3218 MHz 8.6436 MHz
Manufacturer Oscillator Cin/Cout
CITIZEN WATCH CO., LTD.
CSA-309
5 pF to 12 pF
(Crystal)
HC-49/U-S
(Cin = Cout)
(16.9344 MHz)
FCR16.93M2G
Rd = 100 Ω (±20%)
TDK CO., LTD
Cin = Cout = 15 pF (±20%)
(Ceramic resonator)
FCR16.93MCG
Rd = 47 Ω (±20%)
Cin = Cout = 30 pF (built in)
Ceramic resonator
16.93 MHz
Rd
6463
CoutCin
When a CD-ROM XA command is issued, data that is neither interpolated nor muted will be output from the
DFOUT and DOUT pins. (This command is used for CD-ROM XA application.) The CD-ROM XA reset command
also functions as a pin 60 CONT reset, so caution is required.
18. CD-ROM outputs; Pin 39: CK2, pin 37: LRSY, pin 40: ROMOUT, pin 42: C2F, pin 41: C2FCLK
Data is output MSB first from the ROM OUT pin in synchronization with the LRSY signal. This data is appropriate
for input to a CD-ROM LSI, since it is not interpolated, previous value held, or processed by the digital filter circuits.
CK2 is a 2.1168 MHz clock, and data is output on the CK2 rising edge. C2F is the flag information for data in 8-bit
units. C2FCLK is the synchronization signal for that flag.
LC8951 and LC7861 Interface
19. Mute control circuit
An attenuation of 12 dB (MUTE –12 dB) or full muting (MUTE ∞ dB) can be applied by issuing the appropriate
command from the table. Since zero cross muting is used, there is no noise associated with this function. Zero cross
is defined for this function as the top seven bits being all ones or all zeros.
20. 4.2M and 16M pins; Pin 59: 4.2M, pin 58: 16M
The 16.9344 MHz external crystal oscillator 16.9344 MHz buffer output signal is output from the 16M pin. That
frequency divided by four (a 4.2336 MHz frequency) is output from the 4.2M pin. When the oscillator is turned off
both these pins will be fixed at either high or low. These frequencies do not change when a double speed command is
issued.
21. Digital output circuit; Pin 43: DOUT
This is an output pin for use with a digital audio interface. Data is output in the EIAJ format. This signal is a signal
that has passed through the interpolation and muting circuits. This pin has a built-in driver circuit and can directly
drive a transformer.
No. 4818-16/18
LC7861KE
MSB LSB Command RES = low
00000001 MUTE: 0 dB
00000010 MUTE: –12 dB
00000011 MUTE: ∞ dB
o
MSB LSB Command RES = low
01100010 IIS ON
01100011 IIS OFF
o
10001000 CDROM XA
10001011 CONT AND CD-ROM XA RESET
o
22. CD-ROM XA; Pin 60: CONT
The LC7861KE switches to CD-ROM XA mode when an 88H command is issued and data that has not passed
through the interpolation circuit is output from the DFOUT pin. The LC7861KE returns to normal mode when an
8BH command is issued, and interpolated data is output. Note that the 8BH command also functions as a CONT pin
(pin 60) reset.
23. CONT pin; Pin 60: CONT
Pin 60 will goes high when this command is issued.
24. Other pins; Pin 1: TEST1, pin 9: TEST2, pin 23: TEST3, pin 28: TEST4, pin 37: TEST6, pin 61: TEST5
These pins are used for testing the LSI’s internal circuits. Since the pins TEST1 to TEST 5 have built-in pull-down
resistors, they can be left open in normal operation.
Circuit Block Operating Descriptions
1. RAM address control
The LC7861KE incorporates an 8-bit × 2k-word RAM on chip. This RAM is used as a buffer memory, and has an
EFM demodulated data jitter handling capacity of ±4 frames. The LC7861KE continuously checks the remaining
buffer capacity and controls the data write address to fall in the center of the buffer capacity by making fine
adjustments to the PCK side of the CLV servo circuit and the frequency divisor. If the ±4 frame buffer capacity is
exceeded, the LC7861KE forcibly sets the write address to the ±0 position. However, since the errors that occur due to
this operation cannot be handled with error flag processing, the IC applies muting to the output for a 128 frame period.
2. C1 and C2 error correction
The EFM demodulated data is written to internal RAM to compensate for jitter, and the LC7861KE performs the
following processing with a constant timing based on the crystal oscillator clock. First, the LC7861KE performs C1
error checking and correction in the C1 block, determines the C1 flags, and writes the C1 flag register. Next, the
LC7861KE performs C2 error checking and correction in the C2 block, determines the C2 flags, and writes data to
internal RAM.
No. 4818-17/18
LC7861KE
MSB LSB Command RES = low
00001110 CONT Low
10001011 CONT AND CD-ROM XA RESET
o
Position Division ratio or processing
–4 or less Force to ±0
–3 589
–2 589 Increase ratio
–1 589
±0 588 Standard ratio
+1 587
+2 587 Decrease ratio
+3 587
+4 or more Force to ±0
C1 flag Error correction and flag processing
No errors No correction required · Flag reset
1 error Correction · Flag reset
2 errors Correction · Flag set
3 errors or more Correction not possible · Flag set
MSB LSB Command RES = low
10001000 CD-ROM XA ON
o
10001011 CD-ROM XA OFF
PS No. 4818-18/18
LC7861KE
Note: 1. If the positions of the errors determined by the C2 check agree with the those specified by the C1 flags, the correction is performed and the
flags are cleared. However, if the number of C1 flags is 7 or higher, C2 correction may fail. In this case correction is not performed and the C1
flags are taken as the C2 flags without change. Error correction is not possible if one error position agrees and the other does not.
Furthermore, if the number of C1 flags is 5 or under, the C1 check result can be seen as unreliable. Accordingly, the flags will be set in this
case. Cases where the number of C1 flags is 6 or more are handled in the same way, and the C1 flags are taken as the C2 flags without
change. When there is not even one agreement between the error positions, error correction is, of course, impossible. Here, if the number of
C1 flags was 2 or under, data that was seen as correct after C1 correction is now seen as incorrect data. The flags are set in this case. The
other C1 flags are taken as the C2 flags without change.
2. When data is determined to have three or more errors and be uncorrectable, correction is, of course, impossible. Here, if the number of C1
flags was 2 or under, data that was seen as correct after C1 correction is now seen as incorrect data. The flag is set in this case. The other C1
flags are taken as the C2 flags without change.
This catalog provides information as of September, 1998. Specifications and information herein are
subject to change without notice.
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
C2 flag Error correction and flag processing
No errors No correction required · Flag reset
1 error Correction · Flag reset
2 errors Depends on C1 flags
*1
3 errors or more Depends on C1 flags
*2
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