Ordering number : EN6020
CMOS IC
LC78601E
Compact Disc Player DSP with
Built-in Microcontroller
Overview
The LC78601E CMOS IC implements compact disc player signal processing, servo control, LCD display, key input acquisition, and remote controller processing without requiring control by a separate microcontroller. The basic functions provided include demodulation of the EFM signal from the optical pickup, deinterleaving, error detection and correction, 8× oversampling digital filters, D/A converter (with built-in analog low-pass filter), LCD driver, remote controller processing, key acquisition, and control processing. Thus this IC can provide excellent cost/performance characteristics when implementing a low-end CD player.
Functions
•Implements CD play/pause, disc stop, track selection, fast forward, reverse, repeat mode playback of 1 track or the whole disc, programmed play (setup, play, and clear) of up to 16 tracks, and random repeat play under the control of key input or remote controller input.
<Signal-Processing Block>
•Slices an input high-frequency signal at an accurate level, converts the EFM signal, and generates a clock with an average frequency of 4.3218 MHz using a PLL circuit that performs a phase comparison with an internal VCO.
•Accurately generates not only the reference clock but also all necessary internal timings using an external 16.9344MHz crystal.
•Controls the disc motor speed using a frame difference signal created based on the reproduced clock signal and a reference clock.
•Performs detection, protection, and interpolation for the frame synchronizing signal to assure stable data readout.
•Demodulates the EFM signal, converting it to 8-bit symbol data.
•Separates the subcode data from the EFM signal and outputs that data to the internal control processing block.
•After applying a CRC check to the subcode Q signal, outputs that signal to the internal control processing block.
•Buffers the demodulated EFM signal data in internal RAM and compensates for ±4 frames of jitter due to disc speed fluctuations.
•Performs unscrambling and deinterleaving by reordering the demodulated EFM signal data to the stipulated order.
•Performs error detection and correction and flag processing (C1: dual errors, C2: dual errors)
•The C2 flags are set based on the C1 flags and the result of the C2 processing, and the signal is interpolated or previous value hold is applied based on the C2 flags. Dual interpolation is adopted in the interpolation circuit. Previous value hold is applied if two or more consecutive errors are indicated by the C2 flags.
•Performs track jump, focus start, disc motor start/stop, muting on/off, track count, and other operations under control of the internal control processing block.
•Provides digital outputs.
•Generates D/A converter input signals with continuity improved by 8× oversampling digital filters.
•Includes on-chip third-order noise shaper delta-sigma D/A converters with built-in analog low-pass filter.
•Digital deemphasis circuit
•Adopts zero-cross muting.
<Display Block>
•On-chip LCD drivers for 2-digit display plus play, program, repeat, and random indicators
•On-chip bias voltage generator
<Control Processing Block>
•Key matrix circuit with 4 inputs and 2 outputs for an 8-key matrix
•Supports remote controller input.
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
D1898RM (OT) No. 6020-1/11
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LC78601E |
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Features |
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Package Dimensions |
• Package: 64-pin QFP |
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unit: mm |
• 5-V single-voltage power supply |
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3159-QFP64E |
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[LC78601E] |
SANYO: QFP64E(QIP64E)
Equivalent Circuit Block Diagram
Slice level |
VCO clock |
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oscillator |
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control |
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Clock control |
Synchronization detection
EFM demodulation
CLV digital servo
Subcode separator QCRC
Servo commander
C1 and C2 error detection and correction
Flag processing
8 × oversampling digital filters
RAM address generator
Interpolation
and muting
Bilingual support circuit
Digital output circuit
Digital attenuator
Crystal oscillator circuit
Timing generator
System control
LCD driver
No. 6020-2/11
LC78601E
Pin Assignment
Top view
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter |
Symbol |
Conditions |
Ratings |
Unit |
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Maximum supply voltage |
VDD max |
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VSS – 0.3 to VSS + 7.0 |
V |
Input voltage |
VIN |
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VSS – 0.3 to VSS + 0.3 |
V |
Output voltage |
VOUT |
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VSS – 0.3 to VSS + 0.3 |
V |
Allowable power dissipation |
Pd max |
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300 |
mW |
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Operating temperature |
Topr |
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–20 to +75 |
°C |
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Storage temperature |
Tstg |
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–40 to +125 |
°C |
Allowable Operating Ranges at Ta = –20 to +75°C, VDD = 4.5 to 5.5 V, VSS = 0 V
Parameter |
Symbol |
Conditions |
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Ratings |
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Unit |
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min |
typ |
max |
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Supply voltage |
VDD |
VDD, XVDD, L/RVDD, VVDD |
4.5 |
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5.5 |
V |
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Normal speed playback |
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VIH1 |
DEFI, 3 V/*5 V, TMOD, *RES, HFL, TES |
0.7 VDD |
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VDD |
V |
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High-level input voltage |
VIH2 |
*KEYI1 to 4 |
0.8 VDD |
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VDD |
V |
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VIH3 |
EFMIN |
0.6 VDD |
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VDD |
V |
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VIH4 |
PUIN, RMTSL1 to 3, REMOTE, CLOSE, DRF |
0.8 VDD |
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VDD |
V |
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VIL1 |
DEFI, 3 V/*5 V, TMOD, *RES, HFL, TES |
0 |
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0.3 VDD |
V |
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Low-level input voltage |
VIL2 |
*KEYI1 to 4 |
0 |
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0.5 VDD |
V |
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VIL3 |
EFMIN |
0 |
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0.4 VDD |
V |
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VIL4 |
PUIN, RMTSL1 to 3, REMOTE, CLOSE, DRF |
0 |
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0.2 VDD |
V |
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Input level |
VIN1 |
EFMIN: Slice level control |
1.0 |
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Vp-p |
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VIN2 |
XIN: Capacitor coupled input |
1.0 |
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Vp-p |
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Operating frequency range |
fOP |
EFMIN |
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10 |
MHz |
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Crystal oscillator frequency |
fX |
XIN, XOUT |
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16.9344 |
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MHz |
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Input voltage |
VLCD1 |
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0.5 VDD |
VDD |
V |
No. 6020-3/11
LC78601E
Electrical Characteristics at Ta = –20 to +75°C, VDD = 4.5 to 5.5 V, VSS = 0 V
Parameter |
Symbol |
Applicable pins |
Conditions |
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Ratings |
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Unit |
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min |
typ |
max |
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Current drain |
IDD |
VDD, XVDD, L/RVDD, VVDD |
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35 |
55 |
mA |
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DEFI, 3 V/*5 V, EFMIN, TMOD, HFL, |
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High-level input current |
IIH1 |
TES, PUIN, *KEYI1 to 4, RMTSL1 to 3, |
VIN = VDD |
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5 |
µA |
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REMOTE, CLOSE, *RES, DRF |
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IIH2 |
LASER, FSTA, EFBAL, SP8 |
VIN = VDD |
250 |
500 |
1000 |
µA |
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DEFI, 3 V/*5 V, EFMIN, TMOD, HFL, |
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Low-level input current |
IIL1 |
TES, RMTSL2 to 3, REMOTE, *RES, |
VIN = 0 V |
–5 |
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µA |
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DRF |
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IIL2 |
PUIN, *KEYI1 to 4, RMTSL1, CLOSE |
VIN = 0 V |
–25 |
–50 |
–100 |
µA |
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EFMO, CLV, TOFF, TGL, JP, LASER, |
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VOH1 |
FSTA, EFBAL, SP8, FSEQ, PCK, |
IOH = –1 mA |
0.8 VDD |
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V |
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SLOF, SLED+, SLED–, EFLG, FSX, |
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High-level output voltage |
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*AMUTE |
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VOH2 |
S1 to 6 |
IOH = –0.02 mA |
0.8 VDD |
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V |
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VOH3 |
COM1 to 3 |
IOH = – 0.1 mA |
0.8 VDD |
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V |
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VOH4 |
DOUT |
IOH = –12 mA |
0.9 VDD |
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V |
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EFMO, CLV, TOFF, TGL, JP, FSEQ, |
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VOL1 |
PCK, SLOF, SLED+, SLED–, |
IOL = 1 mA |
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0.2 VDD |
V |
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*KEYO1 to 2, EFLG, FSX, |
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RMTSL2 to 3, *AMUTE |
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Low-level output voltage |
VOL2 |
*RANDOM |
IOL = 8 mA |
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0.2 VDD |
V |
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VOL3 |
S1 to 6 |
IOL = 0.02 mA |
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0.2 VDD |
V |
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VOL4 |
COM1 to 3 |
IOL = 0.1 mA |
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0.2 VDD |
V |
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VOL5 |
DOUT |
IOL = 12 mA |
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0.1 VDD |
V |
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IOFFH |
PDO, CLV, JP, *KEY01 to 2, |
VOUT = VDD |
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5 |
µA |
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Output off leakage current |
*RANDOM |
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IOFFL |
PDO, CLV, JP, *KEY01 to 2, |
VOUT = 0 V |
–5 |
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µA |
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*RANDOM |
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Pull-up resistance |
RPU |
PUIN, *KEYI1 to 4, RMTSL1, CLOSE, |
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100 |
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kΩ |
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*RES |
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Pull-down resistance |
RPD |
LASER, FSTA, EFBAL, SP8 |
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10 |
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kΩ |
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Charge pump output current |
IPDOH |
PDO |
RISET = 68 kΩ |
64 |
80 |
96 |
µA |
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IPDOL |
PDO |
RISET = 68 kΩ |
–96 |
–80 |
–64 |
µA |
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1-Bit D/A Converter Analog Characteristics at Ta = 25°C, VDD = L/RVDD = 5 V, VSS = L/RVSS = 0 V
Parameter |
Symbol |
Applicable pins |
Conditions |
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Ratings |
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Unit |
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min |
typ |
max |
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Total harmonic distortion |
THD+N |
LCHO, RCHO |
1 kHz: 0dB data input |
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0.02 |
0.035 |
% |
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20kHz low-pass filter used (built-in AD725D) |
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Dynamic range |
DR |
LCHO, RCHO |
1 kHz: –60dB data input |
86 |
88 |
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dB |
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20kHz low-pass filter and A filter used (built-in AD725D) |
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Signal-to-noise ratio |
S/N |
LCHO, RCHO |
1 kHz: 0dB data input |
96 |
98 |
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dB |
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20kHz low-pass filter and A filter used (built-in AD725D) |
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Crosstalk |
CT |
LCHO, RCHO |
1 kHz: 0dB data input |
80 |
82 |
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dB |
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20kHz low-pass filter used (built-in AD725D) |
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Note: Measure in normal speed playback mode with the Sanyo 1-bit D/A converter block reference circuit.
No. 6020-4/11