Sanyo LC75854W Specifications

Overview

The LC75854E and LC75854W are 1/4 duty LCD display
drivers that can directly drive up to 164 segments and can
control up to four general-purpose output ports. These
products also incorporate a key scan circuit that accepts
input from up to 30 keys to reduce printed circuit board
wiring.

Features

• Key input function for up to 30 keys (A key scan is
performed only when a key is pressed.)

• 1/4 duty - 1/2 bias and 1/4 duty - 1/3 bias drive schemes
can be controlled from serial data (up to 164 segments).

• Sleep mode and all segments off functions that are
controlled from serial data

• Segment output port/general-purpose output port
function switching that is controlled from serial data

• Serial data I/O supports CCB format communication
with the system controller.

• Direct display of display data without the use of a
decoder provides high generality.

• Provision of an on-chip voltage-detection type reset
circuit prevents incorrect displays.

• RC oscillator circuit

Package Dimensions

unit: mm

3159-QFP64E

Ordering number : ENN5066B

O3099TH (OT)/N3095HA (OT)/52295TH (OT) No. 5066-1/25

LC75854E, 75854W

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

1/4 Duty LCD Display Drivers

with Key Input Function

CMOS IC

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

unit: mm

3190-SQFP64

10.0

12.0

1.25

0.5

1.25

1.25 0.5 1.250.18

12.0

116

17

32

33

48

49

64

10.0

0.5

1.7max

0.5

0.1

0.15

SANYO: SQFP64

[LC75854W]

• CCB is a trademark of SANYO ELECTRIC CO., LTD.

• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.

[LC75854E]

SANYO: QFP64E

17.2

14.0

0.8

0.35

15.6

1.6

14.0

17.2

1.0

0.8

1.0

1.0

48

49

64

1

1.6

1.0

33

32

17

16

0.8

0.15

0.1

3.0max

2.7

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V

Allowable Operating Ranges at Ta = –40 to +85°C, VSS= 0 V

No. 5066-2/25

LC75854E, 75854W

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage V

DD

max V

DD

–0.3 to +7.0 V

Input voltage

V

IN

1 CE, CL, DI –0.3 to +7.0 V

V

IN

2 OSC, KI1 to KI5, TEST, VDD1, VDD2 –0.3 to VDD+ 0.3 V

Output voltage

V

OUT

1 DO –0.3 to +7.0 V

V

OUT

2 OSC, S1 to S41, COM1 to COM4, KS1 to KS6, P1 to P4 –0.3 to VDD+ 0.3 V

I

OUT

1 S1 to S41 300 µA

Output current

I

OUT

2 COM1 to COM4 3 mA

I

OUT

3 KS1 to KS6 1 mA

I

OUT

4 P1 to P4 5 mA
Allowable power dissipation Pd max Ta = 85°C 200 mW
Operating temperature Topr –40 to +85 °C
Storage temperature Tstg –55 to +125 °C

Parameter Symbol Conditions

Ratings

Unit

min typ max

Supply voltage V

DD

V

DD

4.5 6.0 V

Input voltage

V

DD

1VDD1 2/3 V

DD

V

DD

V

V

DD

2VDD2 1/3 V

DD

V

DD

V

Input high level voltage

V

IH

1 CE, CL, DI 0.8 V

DD

6.0 V

V

IH

2 KI1 to KI5 0.6 V

DD

V

DD

V

Input low level voltage V

IL

CE, CL, DI, KI1 to KI5 0 0.2 V

DD

V

Recommended external

R

OSC

OSC 62 kΩ

resistance
Recommended external

C

OSC

OSC 680 pF

capacitance
Guaranteed oscillation range f

OSC

OSC 25 50 100 kHz

Data setup time t

ds

CL, DI: Figure 2 160 ns

Data hold time t

dh

CL, DI: Figure 2 160 ns

CE wait time t

cp

CE, CL: Figure 2 160 ns

CE setup time t

cs

CE, CL: Figure 2 160 ns

CE hold time t

ch

CE, CL: Figure 2 160 ns

High level clock pulse width t

øH

CL: Figure 2 160 ns

Low level clock pulse width t

øL

CL: Figure 2 160 ns

Rise time t

r

CE, CL, DI: Figure 2 160 ns

Fall time t

f

CE, CL, DI: Figure 2 160 ns

DO output delay time t

dc

DO, RPU= 4.7 kΩ, CL= 10 pF*1: Figure 2 1.5 µs

DO rise time t

dr

DO, RPU= 4.7 kΩ, CL= 10 pF*1: Figure 2 1.5 µs

Note: *1. Since DO is an open-drain output, these values depend on the resistance of the pull-up resistor RPUand the load capacitance CL.

Electrical Characteristics for the Allowable Operating Ranges

No. 5066-3/25

LC75854E, 75854W

Parameter Symbol Conditions

Ratings

Unit

min typ max

Hysteresis V

H

CE, CL, DI 0.1 V

DD

V

Power-down detection voltage V

DET

2.7 3.0 3.3 V

Input high level current I

IH

CE, CL, DI: VI= 6.0 V 5.0 µA

Input low level current I

IL

CE, CL, DI: VI= 0 V –5.0 µA

Input floating voltage V

IF

KI1 to KI5 0.05 V

DD

V

Pull-down resistance R

PD

KI1 to KI5: VDD= 5.0 V 50 100 250 kΩ

Output off leakage current I

OFFH

DO: VO= 6.0 V 6.0 µA

V

OH

1 KS1 to KS6: IO= –500 µA VDD– 1.2 VDD– 0.5 VDD– 0.2 V

Output high level voltage

V

OH

2 P1 to P4: IO= –1 mA VDD– 1.0 V

V

OH

3 S1 to S41: IO= –20 µA VDD– 1.0 V

V

OH

4 COM1 to COM4: IO= –100 µA VDD– 1.0 V

V

OL

1 KS1 to KS6: IO= 25 µA 0.2 0.5 1.5 V

V

OL

2 P1 to P4: IO= 1 mA 1.0 V

Output low level voltage V

OL

3 S1 to S41: IO= 20 µA 1.0 V

V

OL

4 COM1 to COM4: IO= 100 µA 1.0 V

V

OL

5 DO: IO= 1 mA 0.1 0.5 V

V

MID

1 COM1 to COM4: 1/2 bias, IO= ±100 µA

1/2 V

DD

– 1/2 VDD+

V

1.0 1.0

V

MID

2 S1 to S41: 1/3 bias, IO= ±20 µA

2/3 V

DD

– 2/3 VDD+

V

1.0 1.0

Output middle level voltage

*2

V

MID

3 S1 to S41: 1/3 bias, IO= ±20 µA

1/3 V

DD

– 1/3 VDD+

V

1.0 1.0

V

MID

4 COM1 to COM4: 1/3 bias, IO= ±100 µA

2/3 V

DD

– 2/3 VDD+

V

1.0 1.0

V

MID

5 COM1 to COM4: 1/3 bias, IO= ±100 µA

1/3 V

DD

– 1/3 VDD+

V

1.0 1.0

Oscillator frequency f

OSC

OSC: R = 62 kΩ, C = 680 pF 40 50 60 kHz

I

DD

1 Sleep mode 100 µA

Current drain I

DD

2VDD= 6.0 V, output open, 1/2 bias, f

OSC

= 50 kHz 250 500 µA

I

DD

3VDD= 6.0 V, output open, 1/3 bias, f

OSC

= 50 kHz 200 400 µA

Note: *2. Excluding the bias voltage generation divider resistor built into VDD1 and VDD2. (See Figure 1.)

Figure 1

To the common segment driver

Excluding these resistors.

1. When CL is stopped at the low level

No. 5066-4/25

LC75854E, 75854W

2. When CL is stopped at the high level

Figure 2

Block Diagram

No. 5066-5/25

LC75854E, 75854W

Pin Assignment

Pin Functions

No. 5066-6/25

LC75854E, 75854W

Pin Pin No. Function Active I/O

Handling

when unused

S1/P1 to S4/P4

S5 to S39

COM1
COM2
COM3
COM4

KS1/S40,
KS2/S41,

KS3 to KS6

KI1 to KI5

OSC

CE

CL

DI

DO

TEST

V

DD

1

V

DD

2

V

DD

V

SS

1 to 4

5 to 39

40
41
42
43

44
45

46 to 49

50 to 54

60

62
63
64
61

55

57

58

56
59

Segment outputs for displaying the display data transferred by serial data
input.

The S1/P1 to S4/P4 pins can be used as general-purpose output ports
under serial data control.

Common driver outputs
The frame frequency f

O

is given by: fO= (f

OSC

/512) Hz.

Key scan outputs
Although normal key scan timing lines require diodes to be inserted in the
timing lines to prevent shorts, since these outputs are unbalanced CMOS
transistor outputs, these outputs will not be damaged by shorting when
these outputs are used to form a key matrix. The KS1/S40 and KS2/S41
pins can be used as segment outputs when so specified by the control data.

Key scan inputs
These pins have built-in pull-down resistors.

Oscillator connection
An oscillator circuit is formed by connecting an external resistor and
capacitor at this pin.

Serial data interface connections to the controller. Note that DO, being an
open-drain output, requires a pull-up resistor.

CE: Chip enable
CL: Synchronization clock
DI: Transfer data
DO: Output data

This pin must be connected to ground.

Used for applying the LCD drive 2/3 bias voltage externally. Must be
connected to V

DD

2 when a 1/2 bias drive scheme is used.

Used for applying the LCD drive 1/3 bias voltage externally. Must be
connected to V

DD

1 when a 1/2 bias drive scheme is used.

Power supply connection. Provide a voltage of between 4.5 and 6.0 V.
Power supply connection. Connect to ground.

—

—

—

H

—

H

—
—
—

—

—

—
—

O

O

O

I

I/O

I
I
I

O

I

I

I

—
—

Open

Open

Open

GND

V

DD

GND

Open

—

Open

Open

—
—

Serial Data Input

1. When CL is stopped at the low level

No. 5066-7/25

LC75854E, 75854W

Note: DD: Direction data

Display data

Display data

Display data

Display data

Control data

Fixed data

Fixed data

Fixed data

Note: DD: Direction data

• CCB address......42H

• D1 to D164........Display data

• S0, S1................Sleep control data

• K0, K1...............Key scan output/segment output selection data

• P0, P1................Segment output port/general-purpose output port selection data

• SC......................Segment on/off control data

• DR.....................1/2 bias or 1/3 bias drive selection data

No. 5066-8/25

LC75854E, 75854W

2. When CL is stopped at the high level

Display data

Display data

Display data

Display data

Control data

Fixed data

Fixed data

Fixed data