Sanyo LC75824W Specifications

93098HA (OT)/N3095HA (OT) No.5252-1/17

Overview

The LC75824E and LC75824W are 1/4 duty general­purpose LCD display drivers that can be used for
frequency display in electronic tuners under the control of
a microcontroller. In addition to being able to directly
drive up to 204 LCD segments, the LC75824E and
LC75824W can also control up to 12 general-purpose
output ports.

Features

• Support for 1/4 duty 1/2 bias or 1/4 duty 1/3 bias drive
of up to 204 segments under serial data control

• Serial data input supports CCB* format communication
with the system controller.

• Serial data control of the power-saving mode based
backup function and all the segments forced off function

• Serial data control of switching between the segment
output port and general-purpose output port functions

• Serial data control of the normal mode current drain

• High generality since display data is displayed directly
without decoder intervention.

• The INH pin can force the display to the off state.

• RC oscillator circuit

Package Dimensions

unit: mm

3159-QFP64E

SANYO: QFP64E

[LC75824E]

unit: mm

3190-SQFP64

SANYO: SQFP64

[LC75824W]

• CCB is a trademark of SANYO ELECTRIC CO., LTD.

• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.

CMOS LSI

Ordering number : EN5252A

1/4 Duty General-Purpose LCD Display Driver

LC75824E, 75824W

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

Pin Assignment

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V

No.5252-2/17

LC75824E, 75824W

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage V

DD

max V

DD

–0.3 to +7.0 V

Input voltage

V

IN

1 CE, CL, DI, INH –0.3 to +7.0

V

V

IN

2 OSC, VDD1, VDD2 –0.3 to VDD+ 0.3

Output voltage V

OUT

OSC, S1 to S51, COM1 to COM4, P1 to P12 –0.3 to VDD+ 0.3 V

I

OUT

1 S1 to S51 300 µA

Output current I

OUT

2 COM1 to COM4 3

mA

I

OUT

3 P1 to P12 5
Allowable power dissipation Pd max Ta = 85°C 200 mW
Operating temperature Topr –40 to +85 °C
Storage temperature Tstg –55 to +125 °C

Top view

Allowable Operating Ranges at Ta = –40 to 85°C, VSS= 0 V

Electrical Characteristics for the Allowable Operating Ranges

Note: * Excluding the bias voltage generation divider resistors built into the VDD1 and VDD2. (See Figure 1)

No.5252-3/17

LC75824E, 75824W

Parameter Symbol Conditions min typ max Unit

Supply voltage V

DD

V

DD

3.0 6.0 V

Input voltage

V

DD

1 VDD1 2/3 V

DD

V

DD

V

V

DD

2 VDD2 1/3 V

DD

V

DD

Input high-level voltage V

IH

CE, CL, DI, INH 0.8 V

DD

6.0 V

Input low-level voltage V

IL

CE, CL, DI, INH 0 0.2 V

DD

V

Recommended external

R

OSC

OSC 270 kΩ

resistance
Recommended external

C

OSC

OSC 100 pF

capacitance
Guaranteed oscillation range f

OSC

OSC 25 50 100 kHz

Data setup time t

ds

CL, DI: Figure 2 160 ns

Data hold time t

dh

CL, DI: Figure 2 160 ns

CE wait time t

cp

CE, CL: Figure 2 160 ns

CE setup time t

cs

CE, CL: Figure 2 160 ns

CE hold time t

ch

CE, CL: Figure 2 160 ns

High-level clock pulse width t

øH

CL: Figure 2 160 ns

Low-level clock pulse width t

øL

CL: Figure 2 160 ns

Rise time t

r

CE, CL, DI: Figure 2 160 ns

Fall time t

f

CE, CL, DI: Figure 2 160 ns

INH switching time t

c

INH, CE: Figure 3 10 µs

Parameter Symbol Conditions min typ max Unit

Hysteresis V

H

CE, CL, DI, INH 0.1 V

DD

V

Input high-level current I

IH

CE, CL, DI, INH: VI= 6.0 V 5.0 µA

Input low-level current I

IL

CE, CL, DI, INH: VI= 0 V –5.0 µA

V

OH

1 S1 to S51: IO= –20 µA VDD– 1.0

Output high-level voltage V

OH

2 COM1 to COM4: IO= –100 µA VDD– 1.0 V

V

OH

3 P1 to P12: IO= –1 mA VDD– 1.0

V

OL

1 S1 to S51: IO= 20 µA 1.0

Output low-level voltage V

OL

2 COM1 to COM4: IO= 100 µA 1.0 V

V

OL

3 P1 to P12: IO= 1 mA 1.0

V

MID

1 COM1 to COM4: 1/2 bias, IO= ±100 µA

1/2 VDD– 1.0 1/2 VDD+ 1.0

V

MID

2 S1 to S51: 1/3 bias, IO= ±20 µA

2/3 VDD– 1.0 2/3 VDD+ 1.0

Output middle-level voltage* V

MID

3 S1 to S51: 1/3 bias, IO= ±20 µA

1/3 VDD– 1.0 1/3 VDD+ 1.0

V

V

MID

4 COM1 to COM4: 1/3 bias, IO= ±100 µA

2/3 VDD– 1.0 2/3 VDD+ 1.0

V

MID

5 COM1 to COM4: 1/3 bias, IO= ±100 µA

1/3 VDD– 1.0 1/3 VDD+ 1.0

Oscillator frequency f

OSC

OSC: R

OSC

= 270 kΩ, C

OSC

= 100 pF 40 50 60 kHz

I

DD

1 Power-saving mode 5

I

DD

2

V

DD

= 3.0 V, outputs open, 1/2 bias, f

OSC

= 50 kHz,

70 140

control data CU = 0

I

DD

3

V

DD

= 6.0 V, outputs open, 1/2 bias, f

OSC

= 50 kHz,

200 400

control data CU = 0

I

DD

4

V

DD

= 3.0 V, outputs open, 1/3 bias, f

OSC

= 50 kHz,

80 160

control data CU = 0

I

DD

5

V

DD

= 6.0 V, outputs open, 1/3 bias, f

OSC

= 50 kHz,

250 500

Current drain

control data CU = 0

µA

I

DD

6

V

DD

= 3.0 V, outputs open, 1/2 bias, f

OSC

= 50 kHz,

30 60

control data CU = 1

I

DD

7

V

DD

= 6.0 V, outputs open, 1/2 bias, f

OSC

= 50 kHz,

130 260

control data CU = 1

I

DD

8

V

DD

= 3.0 V, outputs open, 1/3 bias, f

OSC

= 50 kHz,

40 80

control data CU = 1

I

DD

9

V

DD

= 6.0 V, outputs open, 1/3 bias, f

OSC

= 50 kHz,

150 300

control data CU = 1

Figure 1

1. When CL is stopped at the low level

2. When CL is stopped at the high level

Figure 2

No.5252-4/17

LC75824E, 75824W

Block Diagram

Pin Functions

No.5252-5/17

LC75824E, 75824W

Pin Pin No. Function Active I/O

Handling when
unused

S1/P1 to S12/P12,
S13 to S51

COM1 to COM4

OSC

CE

CL

DI

INH

V

DD

1

V

DD

2

V

DD

V

SS

1 to 12,

13 to 51

52 to 55

60

62

63

64

61

57

58

56

59

Segment outputs for displaying the display data transferred by serial data
input. Pins S1/P1 to S12/P12 can be used as general-purpose output ports
when so specified by the control data.

Common driver outputs.
The frame frequency f

O

is given by: fO = (f

OSC

/512) Hz.

Oscillator connection. An oscillator circuit is formed by connecting an external
resistor and capacitor to this pin.

CE: Chip enable
CL: Synchronization clock
DI: Transfer data

Serial data transfer inputs.
These pins are connected to the
microcontroller.

Display off control input

• INH = low (V

SS

) .......Display forced off

Pins S1/P1 to S12/P12 = low (These pins are forced to

the segment output port

function and held low.)
S13 to S51 = low
COM1 to COM4 = low

• INH = high (V

DD

)......Display on

Note that serial data transfers can be performed when the display is forced off.

Used to apply the LCD drive 2/3 bias voltage. Short this pin to V

DD

2 if a

1/2-bias drive scheme is used.

Used to apply the LCD drive 1/3 bias voltage. Short this pin to V

DD

1 if a

1/2-bias drive scheme is used.

Power supply. Provide a voltage of between 3.0 and 6.0 V.

Ground. Connect this pin to the system ground.

—

—

—

H

—

L

—

—

—

—

O

O

I/O

I

I

I

I

I

I

—

—

Open

Open

GND

GND

GND

Open

Open

—

—

Serial Data Input

1. When CL is stopped at the low level

Note: DD is the direction data.

No.5252-6/17

LC75824E, 75824W

CCB address

8 bits

Display data

52 bits

Control data

10 bits

DD

CCB address

8 bits

Display data

52 bits

Fixed data

10 bits

DD

CCB address

8 bits

Display data

52 bits

Fixed data

10 bits

DD

CCB address

8 bits

Display data

48 bits

Fixed data

14 bits

DD