Sanyo LC75813T Specifications
Overview
The LC75813E and LC75813T are 1/3 duty and 1/4 duty
general-purpose LCD drivers that can be used for
frequency display in electronic tuners under the control of
a microcontroller. The LC75813E and LC75813T can
drive an LCD with up to 344 segments directly. The
LC75813E and LC75813T can also control up to 8
general-purpose output ports. Since the LC75813E and
LC75813T use separate power supply systems for the
LCD drive block and the logic block, the LCD driver
block power-supply voltage can be set to any voltage in
the range 2.7 to 6.0 volts, regardless of the logic block
power-supply voltage.
Features
• Switching between 1/3 duty and 1/4 duty drive
techniques under serial data control.
• Switching between 1/2 bias and 1/3 bias drive
techniques under serial data control.
• Up to 261 segments for 1/3 duty drive and 344 segments
for 1/4 duty drive can be displayed.
• Serial data input supports CCB format communication
with the system controller.
• Serial data control of the power-saving mode based
backup function and all the segments forced off
function.
• Serial data control of switching between the segment
output port and the general-purpose output port
functions.
CMOS IC
Ordering number : ENN7159
20102RM (OT) No. 7159-1/26
LC75813E, 75813T
1/3, 1/4 Duty General-Purpose LCD Driver
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V
Parameter Symbol Conditions Ratings Unit
Maximum supply voltage
V
DD
max V
DD
–0.3 to +7.0
V
V
LCD
max V
LCD
–0.3 to +7.0
V
IN
1 CE, CL, DI, INH –0.3 to +7.0
Input voltage V
IN
2 OSC –0.3 to VDD+ 0.3 V
V
IN
3V
LCD
1, V
LCD
2 –0.3 to V
LCD
+ 0.3
Output voltage
V
OUT
1 OSC –0.3 to V
DD
+ 0.3
V
V
OUT
2 S1 to S87, COM1 to COM4, P1 to P8 –0.3 to V
LCD
+ 0.3
I
OUT
1 S1 to S87 300 µA
Output current I
OUT
2 COM1 to COM4 3
mA
I
OUT
3 P1 to P8 5
Allowable power dissipation Pd max Ta = 85°C 200 mW
Operating temperature Topr –40 to +85 °C
Storage temperature Tstg –55 to +125 °C
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
• Serial data control of frame frequency for common and
segment output waveforms.
• High generality, since display data is displayed directly
without decoder intervention.
• Independent V
LCD
for the LCD driver block (V
LCD
can
be set to any voltage in the range 2.7 to 6.0 volts,
regardless of the logic block power-supply voltage.)
• The INH pin can force the display to the off state.
• RC oscillator circuit
Package Dimensions
unit: mm
3151A-QFP100E
unit: mm
3274-TQFP100 (14×14)
No. 7159--2/26
LC75813E, 75813T
20.0
23.2
14.0
17.2
0.15
0.8
(2.7)
3.0max
0.1
0.3
0.65
(0.58)
1 30
80 51
31
50
100
81
[LC75813E]
SANYO: QFP100E
100
1 25
26
50
5175
76
14.0
(1.0)
(1.0)
0.1
0.125
16.0
0.2
0.5
1.2max
0.5
14.0
16.0
[LC75813T]
SANYO: TQFP100
Parameter Symbol Conditions
Ratings
Unit
min typ max
Supply voltage
V
DDVDD
2.7 6.0
V
V
LCDVLCD
2.7 6.0
Input voltage
V
LCD
1 V
LCD
1 2/3 V
LCD
V
LCD
V
V
LCD
2 V
LCD
2 1/3 V
LCD
V
LCD
Input high level voltage V
IH
CE, CL, DI, INH 0.8 V
DD
6.0 V
Input low level voltage V
IL
CE, CL, DI, INH 0 0.2 V
DD
V
Recommended external resistance R
OSC
OSC 39 kΩ
Recommended external capacitance C
OSC
OSC 1000 pF
Guaranteed oscillation range f
OSC
OSC 19 38 76 kHz
Data setup time t
ds
CL, DI: Figure 2 160 ns
Data hold time t
dh
CL, DI: Figure 2 160 ns
CE wait time t
cp
CE, CL: Figure 2 160 ns
CE setup time t
cs
CE, CL: Figure 2 160 ns
CE hold time t
ch
CE, CL: Figure 2 160 ns
High level clock pulse width t
øH
CL: Figure 2 160 ns
Low level clock pulse width t
øL
CL: Figure 2 160 ns
Rise time t
r
CE, CL, DI: Figure 2 160 ns
Fall time t
f
CE, CL, DI: Figure 2 160 ns
INH switching time t
c
INH, CE: Figure 3 10 µs
Allowable Operating Ranges at Ta = –40 to +85°C, VSS= 0 V
Note: *1 Excluding the bias voltage generation divider resistors built in the V
LCD
1 and V
LCD
2. (See Figure 1.)
No. 7159-3/26
LC75813E, 75813T
Parameter Symbol Conditions
Ratings
Unit
min typ max
Hysteresis V
H
CE, CL, DI, INH 0.1 V
DD
V
Input high level current I
IH
CE, CL, DI, INH: VI= 6.0 V 5.0 µA
Input low level current I
IL
CE, CL, DI, INH: VI= 0 V –5.0 µA
V
OH
1 S1 to S87: IO= –20 µA V
LCD
– 0.9
Output high level voltage V
OH
2 COM1 to COM4: IO= –100 µA V
LCD
– 0.9 V
V
OH
3 P1 to P8: IO= –1 mA V
LCD
– 0.9
V
OL
1 S1 to S87: IO= 20 µA 0.9
Output low level voltage V
OL
2 COM1 to COM4: IO= 100 µA 0.9 V
V
OL
3 P1 to P8: IO= 1 mA 0.9
V
MID
1 COM1 to COM4: 1/2 bias, IO= ±100 µA
1/2 V
LCD
– 1/2 V
LCD
+
0.9 0.9
V
MID
2 S1 to S87: 1/3 bias, IO= ±20 µA
2/3 V
LCD
– 2/3 V
LCD
+
0.9 0.9
Output middle level voltage*1 V
MID
3 S1 to S87: 1/3 bias, IO= ±20 µA
1/3 V
LCD
– 1/3 V
LCD
+
V
0.9 0.9
V
MID
4 COM1 to COM4: 1/3 bias, IO= ±100 µA
2/3 V
LCD
– 2/3 V
LCD
+
0.9 0.9
V
MID
5 COM1 to COM4: 1/3 bias, IO= ±100 µA
1/3 V
LCD
– 1/3 V
LCD
+
0.9 0.9
Oscillator frequency f
OSC
OSC: R
OSC
= 39 kΩ, C
OSC
= 1000 pF 30.4 38 45.6 kHz
I
DD
1 V
DD
: Power-saving mode 5
I
DD
2 VDD: VDD= 6.0 V, output open, f
OSC
= 38 kHz 250 500
Current drain I
LCD
1 V
LCD
: Power-saving mode 5 µA
I
LCD
2 V
LCD
:
V
LCD
= 6.0 V, output open, 1/2 bias, f
OSC
= 38 kHz
200 400
I
LCD
3 V
LCD
:
V
LCD
= 6.0 V, output open, 1/3 bias, f
OSC
= 38 kHz
120 240
Electrical Characteristics for the Allowable Operating Ranges
Figure 1
V
SS
To the common segument drivers
V
LCD
2
V
LCD
1
Except these resistors
V
LCD
1. When CL is stopped at the low level
2. When CL is stopped at the high level
Figure 2
Block Diagram
No. 7159-4/26
LC75813E, 75813T
S1/P1
S2/P2
S8/P8
S9
S85
CE
CL
DI
S86
COM4/S87
COM3
COM2
COM1
V
SS
V
LCD
2
V
LCD
1
V
LCD
V
DD
INH
OSC
SHIFT REGISTER
SEGMENT DRIVER & LATCH
ADDRESS
DETECTOR
CLOCK
GENERATOR
COMMON
DRIVER
tøH tøL
tr tf
tds tdh
tcp tcs
tch
V
IL
V
IH
V
IH
V
IH
V
IL
V
IL
50%
CL
CE
DI
tøL tøH
tf tr
tds tdh
tcp tcs
tch
V
IL
V
IH
V
IH
V
IH
V
IL
V
IL
50%
CL
CE
DI
Pin Functions
No. 7159-5/26
LC75813E, 75813T
Symbol
Pin No.
Function Active I/O
Handling
LC75813ELC75813T
when unused
3 to 10
11 to 88
1 to 8
9 to 86
92 to 90
89
90 to 88
87
98
96
100
98
1
2
100
99
99
97
95
93
96
94
93
91
94
92
S1/P1 to S8/P8
S9 to S86
COM1 to COM3
COM4/S87
OSC
CE
CL
DI
INH
V
LCD
1
V
LCD
2
V
DD
V
LCD
Segment outputs for displaying the display data transferred by serial data
input. The pins S1/P1 to S8/P8 can be used as general-purpose output
ports when so set up by the control data.
Common driver outputs.
The frame frequency is f
O
Hz.
The COM4/S87 pin can be used as a segment output in 1/3 duty.
Oscillator connection.
An oscillator circuit is formed by connecting an external resistor and
capacitor to this pin.
Serial data transfer inputs. These pins are connected to the control
microprocessor.
CE: Chip enable
CL: Synchronization clock
DI: Transfer data
Display off control input
• INH = low (V
SS
)....Off
S1/P1 to S8/P8 = low (V
SS
)
(These pins are forcibly set to the segment output port
function and fixed at the V
SS
level.)
S9 to S86 = low (V
SS
)
COM1 to COM3 = low (V
SS
)
COM4/S87 = low (V
SS
)
• INH = high (V
DD
)..On
Note that serial data transfers can be performed when the display is forced
off by this pin.
Used to apply the LCD drive 2/3 bias voltage externally. This pin must be
connected to V
LCD
2 when 1/2 bias drive is used.
Used to apply the LCD drive 1/3 bias voltage externally. This pin must be
connected to V
LCD
1 when 1/2 bias drive is used.
Logic block power supply. Provide a voltage in the range 2.7 to 6.0 V.
LCD driver block power supply. Provide a voltage in the range 2.7 to 6.0 V.
—
—
—
H
—
L
—
—
—
—
O
O
I/O
I
I
I
I
I
I
—
—
Open
Open
V
DD
GND
GND
Open
Open
—
—
97
95
V
SS
Ground pin. Connect to ground. — — —
VSS
VDD
S82
S79
S83
S84
COM2
VLCD
P4/S4
S10
S16
S21
S15
S34
S39
S44
S59
S58
S49
S50
S51
S52
S53
S54
S55
S56
S57
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
P3/S3
S9
P2/S2
P1/S1
DI
CL
S80
LC75813E
(QFP100E)
S81
S85
S86
COM3
S87/COM4
COM1
VLCD1
VLCD2
OSC
INH
S33
S32
S31
S30
S29CE
5180
5081
31100
301
P8/S8
P7/S7
P6/S6
P5/S5
S14
S20
S13
S12
S11
S19
S18
S17
S25
S24
S23
S22
S28
S27
S26
S38
S37
S36
S35
S43
S42
S41
S40
S48
S47
S46
S45
VDD
S86
S84
S76
S55
S51
S52
S53
S54
S56
S57
S58
S59
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
P5/S5
S11
P4/S4
P3/S3
P2/S2
P1/S1
S77
S79
S78
S80
LC75813T
(TQFP100)
S81
S82
S83
S85
S87/COM4
COM3
COM1
COM2
VLCD
VLCD1
VSS
VLCD2
OSC
CE
INH
CL
S35
S34
S33
S32
S31
S29
S30
S27
S28
S26DI
5175
5076
26100
251
S10
S9
P8/S8
P7/S7
P6/S6
S16
S22
S15
S14
S13
S12
S21
S20
S19
S18
S17
S25
S24
S23
S40
S39
S38
S37
S36
S45
S44
S43
S42
S41
S50
S49
S48
S47
S46
Top view
Pin Assignments
Serial Data Transfer Format
1. 1/3 duty
① When CL is stopped at the low level
Note: DD···Direction data.
No. 7159-6/26
LC75813E, 75813T
B1B0
D2D100 D83 D84 D85 D86 D87
CCB address
8 bits
Display data
87 bits
Control data
15 bits
DD
2 bits
CCB address
8 bits
Display data
87 bits
Fixed data
15 bits
DD
2 bits
CCB address
8 bits
Display data
87 bits
Fixed data
15 bits
DD
2 bits
DI
CL
CE
000 100
B3B2 A0 A1 A3A2
A0 A1 A3A2
A0 A1 A3A2
0 0 0 0 0 P0 P1 P2 P30 0 0SCFCDT DR BU
B1B0
0 0 D88 D89
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 00
B3B2
D170 D171 D172 D173 D174
B1B0
0 0 D176D175
0 0 0 1 0 0
B3B2
D257 D258 D259 D260 D261 0 0 00 00 0 00 0 1 00 00 00
Note: DD···Direction data.
• CCB address......40H
• D1 to D261........Display data
• P0 to P3.............Segment output port/general-purpose output port switching control data
• DR.....................1/2 bias drive or 1/3 bias drive switching control data
• DT .....................1/3 duty drive or 1/4 duty drive switching control data
• FC......................Common and segment output waveforms frame frequency setting control data
• SC......................Segments on/off control data
• BU.....................Normal mode/power-saving mode control data
② When CL is stopped at the high level
No. 7159-7/26
LC75813E, 75813T
D2D10 0 0 00 D83 D84 D85 D86 D87
DI
CL
CE
100 P0 P1 P2 P3 DR DT FC SC BU0 0 0 0 0 0 0 0
0000 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D89D88 D170 D171 D172 D173 D174
1000
0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0D176D175 D257 D258 D259 D260 D2611000
CCB address
8 bits
Display data
87 bits
Control data
15 bits
DD
2 bits
CCB address
8 bits
Display data
87 bits
Fixed data
15 bits
DD
2 bits
CCB address
8 bits
Display data
87 bits
Fixed data
15 bits
DD
2 bits
B1B0 B3B2 A0 A1 A3A2
B1B0 B3B2 A0 A1 A3A2
B1B0 B3B2 A0 A1 A3A2
No. 7159--8/26
LC75813E, 75813T
2. 1/4 duty
① When CL is stopped at the low level
Note: DD···Direction data.
B1B0
D2 D83 D84 D85 D86 D87 D88D10 0 0 0 0 0 1 0
CCB address
8 bits
Display data
88 bits
Control data
14 bits
DD
2 bits
CCB address
8 bits
Display data
88 bits
Fixed data
14 bits
DD
2 bits
CCB address
8 bits
Display data
84 bits
Fixed data
18 bits
DD
2 bits
CCB address
8 bits
Display data
84 bits
Fixed data
18 bits
DD
2 bits
DI
CL
CE
B3B2 A0 A1 A2 A3
B1B0 B3B2 A0 A1 A2 A3
B1B0 B3B2 A0 A1 A2 A3
B1B0 B3B2 A0 A1 A2 A3
0 0 0 0 0 FCDT DR 0 0BUSC P3P2P1P0
0 D89 D900 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11000 0 0
D171 D172 D173 D174 D175 D176
0 0 D177 D178
00 100 0
D259 D260 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
0 00 D261 D262
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 110 0 0
D343 D344
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