Sanyo LC75810T Specifications

Ordering number : ENN∗7141

CMOS IC

LC75810E, 75810T

1/8 to 1/10 Duty Dot Matrix LCD Display Controllers/Drivers

Overview

The LC75810E and LC75810T are 1/8 to 1/10 duty dot matrix LCD display controllers/drivers that support the display of characters, numbers, and symbols. In addition to generating dot matrix LCD drive signals based on data transferred serially from a microcontroller, the LC75810E and LC75810T also provide on-chip character display ROM and RAM to allow display systems to be implemented easily.

Features

•

Controls and drives a 5 × 7, 5 × 8, or 5 × 9 dot matrix

LCD.

•

Supports accessory display segment drive

(up to 80 segments)

•

Display technique:

1/8-duty, 1/4-bias drive (5 × 7 dots, 6 × 7 dots) 1/9-duty, 1/4-bias drive (5 × 8 dots, 6 × 8 dots) 1/10-duty, 1/4-bias drive (5 × 9 dots, 6 × 9 dots)

•

Display digits:

16 digits × 1 line (5 × 7 dots), 15 digits × 1 line (5 × 8 or 5 × 9 dots) 13 digits × 1 line (6 × 7, 6 × 8, or 6 × 9 dots)

•

Display control memory

CGROM: 240 characters (5 × 7, 5 × 8, or 5 × 9 dots) CGRAM: 16 characters (5 × 7, 5 × 8, or 5 × 9 dots) DCRAM: 64 × 8 bits ALATCH: 80 bits

Continued on next page.

•••• CCB is a trademark of SANYO ELECTRIC CO., LTD.

•••• CCB is SANYO’s original bus format and all the bus

addresses are controlled by SANYO.

Q Any and all SANYO products described or contained herein do not have specifications that can handle

applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.

Q SANYO assumes no responsibility for equipment failures that result from using products at values that exceed,

even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.

Package Dimensions

unit: mm

3151A-QFP100E

[LC75810E]

23.2

20.0

0.65

[LC75810T]

16.0

14.0

125

0.5

100

(0.58)

3.0max

unit: mm

3274-TQFP100

1.2max

80

81

130

(2.7)

0.1

76

100

(1.0)

0.1

0.2

51

50

14.0

17.2

31

0.3

SANYO: QFP100E

5175

50

14.0

16.0

26

0.8

0.15

0.5

0.125

SANYO: TQFP100

32902RM(OT)No.7141-1/54

LC75810E/T

Continued from preceding page.

•

Instruction function

Display on/off control Smooth up, down, left, and right scrolling of the display

•

Provides a backup function based on power saving mode

•

The frame frequency of the common and segment output

waveforms can be controlled by instructions.

•

Built-in display contrast adjustment circuit

•

Serial data input supports CCB format communication with

the system controller

•

Independent LCD driver block power supply V

•

Provides a

•

RC oscillator circuit

pin for IC internal initialization.

RES

LCD

No.7141-2/54

Pin Assignments (Top view)

LC75810E/T

COM10/S79

COM9/S80

COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1

VDD

VLCD VLCD0 VLCD1 VLCD2 VLCD3

VSS

OSC

RES

S78

CL

S77

DI

S76

S1

S59

S75

S61

S62

S63

S64

S65

S66

S67

S68

S69

S70

S71

S72

S73

S74

S57

S58

S60

S53

S54

S55

S56

LC75810E

(QFP100E)

S4

S3S9S2

S5

S6

S7

S8

S10

S12

S11

S16

S15

S14

S13

S17

S21

S20

S19

S18

S24

S23

S22

S49

S50

S51

S52

5180

5081

S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29CE

31100

301

S25

S28

S27

S26

S51

S52

S53

S54

S56

S57

S58

S59

S61

S62

S63

S64

S65

S66

S67

S68

S69

S70

S71

S72

S73

S74

S76 S77 S78

COM10/S79

COM9/S80

COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1

VDD

VLCD VLCD0 VLCD1 VLCD2 VLCD3

VSS

OSC

RES

CE CL

S75

S1

S2

S3

S4

S5

S6

S7

LC75810T

(TQFP100)

S9

S8

S10

S11

S60

S16

S15

S14

S13

S12

S17

S55

5175

5076

S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26DI

26100

251

S22

S21

S20

S19

S18

S25

S24

S23

No.7141-3/54

LC75810E/T

Specifications

Absolute Maximum Ratings at Ta ==== 25°°°°C, V

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage

Input voltage

Output voltage

Output current

VDD max VDD −0.3 to +7.0

V

max V

LCD

VIN1 CE, CL, DI,

−0.3 to +11.0

LCD

RES

−0.3 to +7.0

VIN2 OSC −0.3 to VDD + 0.3

3 V

V

IN

V

1 OSC −0.3 to V

OUT

V

2 V

OUT

I

1 S1 to S80 300 µA

OUT

I

2 COM1 to COM10 3 mA

OUT

1, V

LCD

2, V

LCD

0, S1 to S80, COM1 to COM10 −0.3 to V

Allowable power dissipation Pd max Ta = 85°C 200 mW Operating temperature Topr −40 to +85 °C Storage temperature Tstg −55 to +125 °C

Allowable Operating Ranges at Ta ==== −−−−40°°°°C to ++++ 85°°°°C, V

Parameter Symbol Conditions

VDD VDD 2.7 6.0

Supply voltage

V

Output voltage V

V

Input voltage

V

Input high level voltage VIH CE, CL, DI,

Input low level voltage VIL CE, CL, DI,

Recommended external resistance

Recommended external capacitance

R

C

When the display contrast adjustment circuit is used. 7.0 10.0

LCD

When the display contrast adjustment circuit is not used. 4.5 10.0

0 V

LCD

1 V

LCD

2 V

LCD

3 V

LCD

OSC 10 kΩ

osc

OSC 470 pF

osc

0 4.5 V

LCD

1 3/4 V

LCD

2 2/4 V

LCD

3 1/4 V

LCD

RES

0.8 VDD 6.0 V

RES

0 0.2 VDD V

Guaranteed oscillation range fosc OSC 150 300 600 kHz

Data setup time tds CL, DI (Figure 2) 160 ns

Data hold time tdh CL, DI (Figure 2) 160 ns

CE wait time tcp CE, CL (Figure 2) 160 ns

CE setup time tcs CE, CL (Figure 2) 160 ns

CE hold time tch CE, CL (Figure 2) 160 ns High level clock pulse width tφH CL (Figure 2) 160 ns Low level clock pulse width tφL CL (Figure 2) 160 ns

Minimum reset pulse width t

WRES

RES

(Figure 3) 1 µs

==== 0V

SS

3 −0.3 to V

==== 0V

SS

Ratings

min. typ. max.

0 V

LCD

0 V

LCD

0 V

LCD

+ 0.3

DD

+ 0.3

V

LCD

0

LCD

0

LCD

0

LCD

V

Unit

V

No.7141-4/54

LC75810E/T

Electrical Characteristics for the Allowable Operating Ranges

Parameter Symbol Conditions

Hysteresis VH CE, CL, DI,

Input high level current IIH CE, CL, DI,

Input low level current IIL CE, CL, DI,

VOH1 S1 to S80: IO = −20 µA

Output high level voltage

V

2 COM1 to COM10: IO = −100 µA

OH

Output low level voltage

Output middle level voltage ∗1

Oscillator frequency f

VOL1 S1 to S80: IO = 20 µA 0.6

2 COM1 to COM10: IO = 100 µA 0.6

V

OL

V

1 S1 to S80: IO = ±20 µA

MID

V

2 COM1 to COM10: IO = ±100 µA

MID

V

3 COM1 to COM10: IO = ±100 µA

MID

R

OSC:

osc

OSC

C

OSC

IDD1 VDD: Power saving mode 5

V

DD

Output open

f

OSC

: Power saving mode 5

LCD

V

LCD

Output open

:

LCD

f

OSC

Current drain

IDD2 VDD:

I

1 V

LCD

I

2 V

LCD

When the display contrast adjustment circuit is used

V

LCD

Output open

I

LCD

3 V

LCD

:

f

OSC

When the display contrast adjustment circuit is not used

Ratings

min. typ. max.

RES

0.1VDD V

RES

VI = 6.0 V 5.0 µA

:

RES

VI = 0 V −5.0 µA

:

V

LCD

0−0.6

V

LCD

0−0.6

Unit

V

2/4 V

= 10 kΩ = 470 pF

0

LCD

−0.6

3/4 V

0

LCD

−0.6

1/4 V

0

LCD

−0.6

210 300 390 kHz

2/4 V

0

LCD

+0.6

3/4 V

0

LCD

+0.6

1/4 V

LCD

+0.6

V

0

= 6.0 V

700 1400

= 300 kHz

= 10.0 V

= 300 kHz

450 900

µA

= 10.0 V

= 300 kHz

200 400

Note ∗1: Excluding the bias voltage generation divider resistors built into the V

V

LCD

CONTRAST

ADJUSTER

0

V

LCD

1

V

LCD

2

V

LCD

V

3

LCD

V

SS

Excluding these resistors

Figure 1

0, V

1, V

2, V

LCD

3, and VSS pins. (See figure 1.)

LCD

To the common and segment drivers

No.7141-5/54

•

When CL is stopped at the low level

CE

LC75810E/T

VIH

VIL

t

φ

H

t

dh

CL

DI

VIH 50%

VIL

VIH

VIL

t

ds

•

When CL is stopped at the high level

CE

φ

L

t

CL

DI

ds

t

φ

L

t

cs

cp

t

ch

VIH

VIL

φ

H

t

dh

t

VIH 50% VIL

VIH

VIL

t

cs

cp

t

ch

Figure 2

Block Diagram

V

DD

V

LCD

0

V

LCD

1

V

LCD

2

V

LCD

V

3

LCD

V

SS

RES

COM1

COMMON

DRIVER

CONTRAST

ADJUSTER

COM8

TIMING

GENERATOR

CLOCK

GENERATOR

S80/COM9

S78

S79/COM10

ALATCH

INSTRUCTION

DECODER

INSTRUCTION

REGISTER

SEGMENT DRIVER

80bits

SCROLL

COUNTER

SHIFT REGISTER

LATCH

CGRAM

5 × 9 × 16

bits

ADDRESS

COUNTER

ADDRESS

REGISTER

5 × 9 × 240

CCB INTERFACE

S1

CGROM

bits

DCRAM

64 × 8

bits

OSC

DI

CL

CE

No.7141-6/54

LC75810E/T

Pin Functions

S1 to S78

S79/COM10

S80/COM9

Pin No.

LC75810E LC75810T

3 to 80

81

82

1 to 78

79

80

Function

Segment driver outputs

The S79/COM10 and S80/COM9 pins can be used as common driver outputs under the “set display technique” instruction.

Active

level

I/O

− O OPEN

COM1 to COM8 90 to 83 88 to 81 Common driver outputs − O OPEN

OSC 98 96

CE 100 98 H I

CL 1 99 I

Oscillator connection. An oscillator circuit is formed by connecting an external resistor and capacitor at this pin.

Serial data transfer inputs. These pins are connected to the microcontroller.

CE: Chip enable

− I/O VDD

CL: Synchronization clock

DI 2 100

DI: Transfer data

− I

Reset signal input

RES

• When

is low (VSS)

− Display off

RES

99 97

S1 to S78 = “L” (V S79/COM10 and S80/COM9 = “L” (V COM1 to COM8 = “L” (V

− Serial data transfer is disabled.

)

SS

)

SS

)

SS

L I GND

− The OSC pin oscillator is stopped.

RES

• When

is high (VDD)

− Display on after a “display on/off control” (display on state

setting) instruction is executed.

− Serial data transfers are enabled.

− The OSC pin oscillator operates.

LCD drive 4/4 bias voltage (high level) supply pin. The level on this pin can be changed by the display contrast adjustment circuit.

V

0 93 91

LCD

However, V external power must not be applied to this pin since the pin circuit

0 must be greater than or equal to 4.5 V. Also,

LCD

− O OPEN

includes the display contrast adjustment circuit.

V

1 94 92

LCD

V

2 95 93

LCD

V

3 96 94

LCD

VDD 91 89

LCD drive 3/4 bias voltage (middle level) supply pin. This pin can be used to supply the 3/4 V

0 voltage level externally.

LCD

LCD drive 2/4 bias voltage (middle level) supply pin. This pin can be used to supply the 2/4 V

0 voltage level externally.

LCD

LCD drive 1/4 bias voltage (middle level) supply pin. This pin can be used to supply the 1/4 V

0 voltage level externally.

LCD

Logic block power supply connection. Provide a voltage of between 2.7 and 6.0 V.

− I OPEN

− − −

LCD driver block power supply connection. Provide a voltage of

V

92 90

LCD

between 7.0 and 10.0 V when the display contrast adjustment circuit is used and provide a voltage of between 4.5 and 10.0 V

− − −

when the circuit is not used.

VSS 97 95 Power supply connection. Connect to ground. − − −

Handling

when

unused

GND

No.7141-7/54

LC75810E/T

Block Functions

•

AC (Address counter)

AC is a counter that provides the DCRAM address. The address is automatically modified internally, and the LCD display state is retained.

•

DCRAM (Data control RAM)

DCRAM is the RAM that is used to store display data expressed as 8-bit character codes. (These character codes are converted to 5 × 7, 5 × 8, or 5 × 9 dot matrix character patterns using CGROM or CGRAM.) DCRAM has a capacity of 64 × 8 bits, and can hold 64 characters. The table below lists the correspondence between the 6-bit DCRAM address loaded into AC and the display position on the LCD panel.

•

For a 64 digits × 1 line display structure (For a “set display technique” instruction with 0Z1 = 0 and 0Z2 = 0)

When the DCRAM address loaded into AC is 00H

Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 61 62 63 64

DCRAM address

(hexadecimal)

First line 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 3C 3D 3E 3F

However, when the display smooth scrolling is performed, the DCRAM address shifts as follows.

Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 61 62 63 64

DCRAM address

(hexadecimal)

First line 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 3D 3E 3F 00

Shift to the left by 1 character digit

Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 61 62 63 64

DCRAM address

(hexadecimal)

First line 3F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 3B 3C 3D 3E

Shift to the right by 1 character digit

Note that the display area on the LCD is display digits 1 to 16 on the first line when a display technique is 5 × 7, 5 × 8, or 5 × 9 dots, and it is display digits 1 to 13 on the first line when a display technique is 6 × 7, 6 × 8, or 6 × 9 dots.

•

For a 32 digits × 2 lines display structure (For a “set display technique” instruction with 0Z1 = 1 and 0Z2 = 0)

When the DCRAM address loaded into AC is 00H

Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 29 30 31 32

DCRAM address

(hexadecimal)

First line 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 1C 1D 1E 1F

Second line 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 3C 3D 3E 3F

However, when the display smooth scrolling is performed, the DCRAM address shifts as follows.

Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 29 30 31 32

DCRAM address

(hexadecimal)

First line 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 1D 1E 1F 00

Second line 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 3D 3E 3F 20

Shift to the left by 1 character digit

Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 29 30 31 32

DCRAM address

(hexadecimal)

First line 1F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 1B 1C 1D 1E

Second line 3F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 3B 3C 3D 3E

Shift to the right by 1 character digit

Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 29 30 31 32

DCRAM address

(hexadecimal)

First line 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 3C 3D 3E 3F

Second line 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 1C 1D 1E 1F

Shift to the up or down by 1 character digit

Note that the display area on the LCD is display digits 1 to 16 on the first line when a display technique is 5 × 7, 5 × 8, or 5 × 9 dots, and it is display digits 1 to 13 on the first line when a display technique is 6 × 7, 6 × 8, or 6 × 9 dots.

No.7141-8/54

LC75810E/T

•

For a 16 digits × 4 lines display structure (For a “set display technique” instruction with 0Z1 = 0 and 0Z2 = 1)

When the DCRAM address loaded into AC is 00H

DCRAM address (hexadecimal)

Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

First line 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F

Second line 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F

Third line 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F

Fourth line 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F

However, when the display smooth scrolling is performed, the DCRAM address shifts as follows.

DCRAM address (hexadecimal)

Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

First line 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00

Second line 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 10

Third line 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 20

Fourth line 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 30

Shift to the left by 1 character digit

Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

DCRAM address (hexadecimal)

First line 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E

Second line 1F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E

Third line 2F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E

Fourth line 3F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E

Shift to the right by 1 character digit

Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

First line 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F

DCRAM address (hexadecimal)

Second line 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F

Third line 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F

Fourth line 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F

Shift to the up by 1 character digit

Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

First line 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F

DCRAM address (hexadecimal)

Second line 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F

Third line 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F

Fourth line 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F

Shift to the down by 1 character digit

Note that the display area on the LCD is display digits 1 to 16 on the first line when a display technique is 5 × 7, 5 × 8, or 5 × 9 dots, and it is display digits 1 to 13 on the first line when a display technique is 6 × 7, 6 × 8, or 6 × 9 dots.

Note ∗2: The DCRAM address is expressed in hexadecimal.

Least significant bit

↓

LSB MSB

DCRAM address DA0 DA1 DA2 DA3 DA4 DA5

Most significant bit

↓

Hexadecimal Hexadecimal

Example: When the DCRAM address is 2EH

DA0 DA1 DA2 DA3 DA4 DA5

0 1 1 1 0 1

Note ∗3: 5 × 7 dots

5 × 8 dots 5 × 9 dots 6 × 7 dots 6 × 8 dots 6 × 9 dots

• • •

16-digit display 5 × 7 dots.

• • •

16-digit display 4 × 8 dots.

• • •

16-digit display 3 × 9 dots.

• • •

13-digit display 6 × 7 dots.

• • •

13-digit display 6 × 8 dots.

• • •

13-digit display 6 × 9 dots.

No.7141-9/54

LC75810E/T

3

2

3

2

•

CGROM (Character generator ROM)

CGROM is the ROM that is used to generate the 240 kinds of 5 × 7, 5 × 8, or 5 × 9 dot matrix character patterns from the 8-bit character codes. CGROM has a capacity of 240 × 45 bits. When a character code is written to DCRAM, the character pattern stored in the CGROM corresponding to the character code is displayed at the position on the LCD corresponding to the DCRAM address loaded into AC.

•

CGRAM (Character generator RAM)

CGRAM is the RAM to which user programs can freely write arbitrary character patterns. Up to 16 kinds of 5 × 7, 5 × 8, or 5 × 9 dot matrix character patterns can be stored. CGRAM has a capacity of 16 × 45 bits.

•

ALATCH (Additional data latch)

ALATCH is the latch that is used to store the ADATA display data for the accessory display. ALATCH has a capacity of 80 bits, and the stored display data is displayed directly without the use of CGROM or CGRAM.

•

SC (Scroll counter)

SC is the counter that is used to scroll the display in the left, right, up, or down directions in dot units. Since this function scrolls in dot units, it implements smooth scrolling.

Reset Function

The LC75810E and LC75810T are reset when a low level is applied to the

pin at power on and, in normal mode. On a

RES

reset the LC75810E and LC75810T create a display with all LCD panels turned off. However, after a reset applications must set the contents of DCRAM, ALATCH, and CGRAM before turning on display with a “display on/off control” instruction since the contents of these memories are undefined. That is, applications must execute the following instructions.

• Set display technique

• DCRAM data write

• ALATCH data write (If ALATCH is used.)

• CGRAM data write (IF CGRAM is used.)

• Set AC and SC addresses

• Set display contrast (If the display contrast adjustment circuit is used.)

After executing the above instructions, applications must turn on the display with a “display on/off control” instruction. Note that when applications turn off in the normal mode, applications must turn off the display with a “display on/off control” instruction. (See the detailed instruction descriptions.)

Serial Data Transfer Format

•

When CL is stopped at the low level

CE

CL

D14

DI

B1

B0

•

When CL is stopped at the high level

1110D0D1

CCB address

8 bits

1000

D4D3D2

A3A2A1A0B3B2

Instruction data

Up to 144 bits

D14

CE

CL

D14

DI

B0

B1

•

CCB address: 4EH

•

D0 to D143: Instruction data

CCB address

8 bits

00011110

D0 D1

D4D3D2

A3A2A1A0B3B2

Instruction data

Up to 144 bits

D14

The data is acquired on the rising edge of the CL signal and latched on the falling edge of the CE signal. When transferring instruction data from the microcontroller, applications must assure that the time from the transfer of one set of instruction data until the next instruction data transfer is significantly longer than the instruction execution time.

No.7141-10/54

LC75810E/T

s

µ

0

1

0

FC

DT2

DT1

X

DW

OZ2

OZ1

technique

Set display

µ

5)

∗

(

s/27

s/162

µ

0

27

0

1

0

BU

SC

A

M

DG16

DG15

DG14

DG13

DG12

DG11

DG10

DG9

DG8

DG7

DG6

DG5

DG4

DG3

DG2

DG1

control

Display on/off

1

0

X

D/U

R/L

X

VS3

VS2

VS1

VS0

X

HS2

HS1

HS0

Display scroll

6)

∗

(

4)

∗

time (

Execution

D143

D142

D141

D140

D139

D138

D137

D136

D135

D134

D133

D132

D131

D130

D129

D128

D127

D126

D125

D124

D123

D122

D121

D120

D119

D118

D117

D116

D115

D114

D113

D112

D111

•

D81

D80

D79

•

D57

D56

D55

•

D1D0Instruction

Instruction Table

µ

Set AC and SC

s

µ

27

0

1

0

X

DA5

DA4

DA3

DA2

DA1

DA0

X

VA3

VA2

VA1

VA0

X

HA2

HA1

HA0

addresses

s

µ

s/ti

µ

27

DCRAM data

1

0

1

0

X

IM2

IM1

X

DA5

DA4

DA3

DA2

DA1

DA0

AC7

AC6

AC5

AC4

AC3

AC2

AC1

AC0

8)

∗

(

7)

∗

write (

s

µ

s

µ

0

s/40.5

µ

27

0

1

0

X

AD80

AD79

AD78

AD77

AD76

AD75

AD74

AD73

AD72

AD71

AD70

AD69

AD68

AD67

AD66

AD65

AD64

AD63

AD62

AD61

AD60

AD59

AD58

AD57

AD56

•

AD26

AD25

AD24

•

AD2

AD1

write

CGRAM data

ALATCH data

•

1

0

X

WM

CA7

CA6

CA5

CA4

CA3

CA2

CA1

CA0

X

CD45

CD44

CD43

CD42

CD41

CD40

CD39

CD38

CD37

CD36

CD35

CD34

CD33

CD32

CD2

CD1

10) (

9)

write (

s

µ

∗

0

X: don’t care

0

1

0

X

CTC

X

CT3

CT2

CT1

CT0

s

µ

58

=

300

210

×

s

µ

300 kHz).

=

s 40.5

µ

1.43

×

ti

=

300

210

×

s

µ

s ti

300 kHz. The execution times differ when the oscillator frequency fosc differs.

=

4: The execution times listed here apply when fosc

∗

contrast

Set display

∗

Notes

µ

232

=

300

×

s

µ

210 kHz

s 162

=

µ

39

=

300

×

s

µ

Example: When fosc

27

210

300 kHz) if another “display scroll” instruction is executed immediately after a preceding “display scroll” instruction.

=

1) is set, the execution time is 27 µs (when fosc

=

5: Note that when the power saving mode (BU

6: The execution time must be seen as being 162 µs (when fosc

∗

1).

=

0) or super-increment mode (IM1 = 0, IM2

=

1, IM2

=

8: Note that the data format differs when a “DCRAM data write” instruction is executed in normal increment mode (IM1

∗

7,

∗

300 kHz) if a “DCRAM data write” instruction is executed in super-increment mode. (See detailed instruction descriptions.)

=

Also note that the execution time is ti µs (when fosc

300 kHz)

=

1). Also note that the execution time is 40.5 µs (when fosc

=

if a “CGRAM data write” instruction is executed in double write mode. (See detailed instruction descriptions.)

10: Note that the data format differs when a “CGRAM data write” instruction is executed in double write mode (WM

∗

9,

∗

No.7141-11/54

LC75810E/T

Detailed Instruction Descriptions

•

Set display technique

D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143

OZ1 OZ2 DW X X X X X DT1 DT2 FC 0 0 0 0 1

DT1, DT2: Set the display technique

DT1 DT2 Display technique

0 0 1/8 duty, 1/4 bias drive S80 S79

1 0 1/9 duty, 1/4 bias drive COM9 S79

0 1 1/10 duty, 1/4 bias drive COM9 COM10

• • •

Code

X:don’t care

Output pins

S80/COM9 S79/COM10

∗11: Sn (n = 79, 80): Segment output

COMn (n = 9, 10): Common output

FC: Set the frame frequency of the common and segment output waveforms

FC

1/8 duty, 1/4 bias drive f8[Hz] 1/9 duty, 1/4 bias drive f9[Hz] 1/10 duty, 1/4 bias drive f10[Hz]

0

1

fosc

3072

fosc

1536

Frame frequency

fosc

3456

fosc

1728

fosc

3840

fosc

1920

OZ1, OZ2: Set the display structure

OZ1 OZ2 Display structure

0 0 64 digits × 1 line display structure 1 0 32 digits × 2 lines display structure 0 1 16 digits × 4 lines display structure

∗12: See block functions (DCRAM)

DW: Set the dot font width

DW Dot font width Number of display digits

0 5-dot font width 16 digits × 1 line (5 × 7 dots), 15 digits × 1 line (5 × 8 or 5 × 9 dots) 1 6-dot font width 13 digits × 1 line (6 × 7, 6 × 8, or 6 × 9 dots)

•

∗13:

5-dot font width (5 × 7, 5 × 8, or 5 × 9 dots)

COM1

COM2 COM3 COM4 COM5 COM6 COM7 COM8

S80/COM9

S79/COM10

S1S2S3S4S5S6S7S8S9

•

6-dot font width (6 × 7, 6 × 8, or 6 × 9 dots)

COM1

COM2 COM3 COM4 COM5 COM6 COM7 COM8

S80/COM9

S79/COM10

S1S2S3S4S5S6S7S8S9

S10

S11

S12

S67

S71

S68

S72

S69

S73

S70

S74

S71

S75

S72

S73

S76

S74

S77

S75

S78

S76

COM10/S79

S77

COM9/S80

S78

No.7141-12/54

LC75810E/T

•

Display on/off control

D120 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143

DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9

• • •

DG10 DG11 DG12 DG13 DG14 DG15 DG1

Code

M A SC BU 0 0 1 0

6

M, A: Specifies the data to be turned on or off.

M A Display operating state

0 0 Both MDATA and ADATA are turned off. (The display is forcibly turned off, regardless of the DG1 to DG16 data.)

0 1 Only ADATA is turned on. (The ADATA of display digits specified by the DG1 to DG16 data are turned on.)

1 0 Only MDATA is turned on. (The MDATA of display digits specified by the DG1 to DG16 data are turned on.)

1 1 Both MDATA and ADATA are turned on. (The MDATA and ADATA of display digits specified by the DG1 to DG16 data are turned on.)

*14: MDATA, ADATA

5 × 7 dot matrix 5 × 8 dot matrix 5 × 9 dot matrix

• • • • •

• • •

ADATA

MDATA

• • • • •

• • •

ADATA

MDATA

• • • • •

• • •

ADATA

MDATA

6 × 7 dot matrix 6 × 8 dot matrix 6 × 9 dot matrix

• • • • •

• • •

ADATA

MDATA

• • • • •

• • •

ADATA

MDATA

• • • • •

• • •

ADATA

MDATA

DG1 to DG16: Specifies the display digit.

Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Display digit data DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 DG11 DG12 DG13 DG14 DG15 DG16

For example, if DG1 to DG8 are 1, and DG9 to DG16 are 0, then display digits 1 to 8 will be turned on, and display digits 9 to 16 will be turned off (blanked).

SC: Controls the common and segment output pins.

SC Common and segment output pin states

0 Output of LCD drive waveforms

1 Fixed at the VSS level (all segments off)

Note ∗15: When SC is 1, the S1 to S80 and COM1 to COM10 output pins are set to the VSS level, regardless of the M, A, and DG1 to DG16 data.

BU: Controls the normal mode and power saving mode.

BU Mode

0 Normal mode

Power saving mode

(In this mode, the OSC pin oscillator is stopped, and the common and segment pins are set to the V

1

the “display on/off control” and “set display contrast” instructions cannot be executed. Thus applications must set the IC to normal mode before executing any of the other instructions.)

level. In this mode, instructions other than

SS

No.7141-13/54

LC75810E/T

•

Display scroll

D120 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143

HS0 HS1 HS2 X X X X X VS0 VS1 VS2 VS3 X X X X R/L D/U X 0 0 0 1 1

HS0 to HS2: Set the amount of smooth scrolling to be applied to MDATA in the left/right direction.

HS0 HS1 HS2 Amount of smooth scrolling to be applied to MDATA in the left/right direction

0 0 0 No shift in either the left or right direction

1 0 0 Shift 1 dot to the left or right. (The shift direction (left or right) is specified with the R/L data.)

0 1 0 Shift 2 dots to the left or right. (The shift direction (left or right) is specified with the R/L data.)

1 1 0 Shift 3 dots to the left or right. (The shift direction (left or right) is specified with the R/L data.)

0 0 1 Shift 4 dots to the left or right. (The shift direction (left or right) is specified with the R/L data.)

1 0 1 Shift 5 dots to the left or right. (The shift direction (left or right) is specified with the R/L data.)

0 1 1 Shift 6 dots to the left or right. (The shift direction (left or right) is specified with the R/L data.)

• • •

Code

X: don’t care

VS0 to VS3: Set the amount of smooth scrolling to be applied to MDATA in the up/down direction.

VS0 VS1 VS2 VS3 Amount of smooth scrolling to be applied to MDATA in the up/down direction

0 0 0 0 No shift in either the up or down direction

1 0 0 0 Shift 1 dot to the up or down. (The shift direction (up or down) is specified with the D/U data.)

0 1 0 0 Shift 2 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.)

1 1 0 0 Shift 3 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.)

0 0 1 0 Shift 4 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.)

1 0 1 0 Shift 5 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.)

0 1 1 0 Shift 6 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.)

1 1 1 0 Shift 7 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.)

0 0 0 1 Shift 8 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) 1 0 0 1 Shift 9 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) (∗16) 0 1 0 1 Shift 10 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) (∗17)

Notes: ∗16: This shift cannot be used when MDATA is 5 × 7 or 6 × 7 dots. ∗17: This shift cannot be used when MDATA is 5 × 7, 5 × 8, 6 × 7 or 6 × 8 dots.

R/L: Specifies the MDATA shift direction (left or right). D/U: Specifies the MDATA shift direction (up or down).

R/L MDATA shift direction (left or right) D/U MDATA shift direction (up or down)

0 Shift left 0 Shift up

1 Shift right

1 Shift down

∗18 Example of the “display scroll” instruction execution Assume that a 32 digits × 2 lines display structure (OZ1 = 1, OZ2 = 0) has been set up with the “set display technique” instruction, and that the following data has been written to DCRAM with the “DCRAM data write” instruction.

Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

DCRAM

First line A B C D E F G H I J K L M N O P Q R S T U V W X Y Z < > z y x w

data

Second line 0 1 2 3 4 5 6 7 8 9 a b c d e f g h i j k l m n o p q r s t u v

No.7141-14/54

•

Display state (1) With no shifting in any direction, left, right, up, or down.

HS0 HS1 HS2 VS0 VS1 VS2 VS3 R/L D/U

0 0 0 0 0 0 0 X X

X: don’t care

(5 × 7 dot matrix)

(6 × 7 dot matrix)

LC75810E/T

•

Display state (2) Shifted 3 dots to the left relative to display state (1)

HS0 HS1 HS2 VS0 VS1 VS2 VS3 R/L D/U

1 1 0 0 0 0 0 0 0

(5 × 7 dot matrix)

(6 × 7 dot matrix)

•

Display state (3) Shifted 6 dots to the left relative to display state (1) Shifted 3 dots to the left relative to display state (2)

HS0 HS1 HS2 VS0 VS1 VS2 VS3 R/L D/U HS0 HS1 HS2 VS0 VS1 VS2 VS3 R/L D/U

0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0

(5 × 7 dot matrix)

(6 × 7 dot matrix)

No.7141-15/54

•

Display state (4) Shifted 4 dots to the up relative to display state (1)

HS0 HS1 HS2 VS0 VS1 VS2 VS3 R/L D/U

0 0 0 0 0 1 0 0 0

(5 × 7 dot matrix)

(6 × 7 dot matrix)

LC75810E/T

•

Display state (5) Shifted 8 dots to the up relative to display state (1) Shifted 4 dots to the up relative to display state (4)

HS0 HS1 HS2 VS0 VS1 VS2 VS3 R/L D/U HS0 HS1 HS2 VS0 VS1 VS2 VS3 R/L D/U

0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0

(5 × 7 dot matrix)

(6 × 7 dot matrix)

•

Display state (6) Shifted 3 dots to the left and 4 dots to the up relative to display state (1)

HS0 HS1 HS2 VS0 VS1 VS2 VS3 R/L D/U

1 1 0 0 0 1 0 0 0

(5 × 7 dot matrix)

(6 × 7 dot matrix)

No.7141-16/54

LC75810E/T

•

Display state (7) Shifted 6 dots to the left and 8 dots to the up relative Shifted 8 dots to the up relative to display state (3) to display state (1)

HS0 HS1 HS2 VS0 VS1 VS2 VS3 R/L D/U HS0 HS1 HS2 VS0 VS1 VS2 VS3 R/L D/U

0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0

Shifted 6 dots to the left relative to display state (5) Shifted 3 dots to the left and 4 dots to the up relative

HS0 HS1 HS2 VS0 VS1 VS2 VS3 R/L D/U HS0 HS1 HS2 VS0 VS1 VS2 VS3 R/L D/U

0 1 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0

to display state (6)

(5 × 7 dot matrix)

(6 × 7 dot matrix)

•

Set AC and SC addresses pattern for SC.>

D112 D113 D114 D115 D116 D117 D118 D119 D120 D121 D122 D123 D124 D125 D126 D127

HA0 HA1 HA2 X X X X X VA0 VA1 VA2 VA3 X X X X

• • •

<Specifies the DCRAM address for AC and the dot address of the dot matrix character

Code

D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143

DA0 DA1 DA2 DA3 DA4 DA5 X X X X X 0 0 1 0 0

DA0 to DA5: DCRAM address

DA0 DA1 DA2 DA3 DA4 DA5

LSB

MSB

↑ ↑

Least Most

significant bit significant bit

HA0 to HA2: Dot address in the horizontal direction for the dot matrix character pattern

HA0 HA1 HA2

LSB MSB

↑ ↑

Least Most

significant bit significant bit

VA0 to VA3: Dot address in the vertical direction for the dot matrix character pattern

VA0 VA1 VA2 VA3

LSB MSB

↑ ↑

Least Most

significant bit significant bit

X: don’t care

No.7141-17/54