Sanyo LC75711NE Specifications

Ordering number : EN*4907

31595TH (OT) No. 4907-1/21

Overview

The LC75710NE series products are dot matrix VFD
controller/driver LSIs that display characters, numbers,
and symbols. These LSIs generate dot matrix VFD drive
signals based on serial data sent from a microprocessor,
and allow display systems to be implemented easily using
the built-in character generator ROM and RAM.
The LC75710NE series products are fabricated in a
CMOS process and can contribute to achieving low-power
operation in user applications.

Features

•5 × 7 dot matrix VFD display controller/driver

(Driver outputs can be connected directly to VFD
devices: pull-down resistors are not required.)

• Display technique: Dynamic lighting technique

• Display digits: 1 to 16 digits (programmable)

• Display control data

CGROM: 5 × 7 dots, 160 characters
CGRAM: 5 × 7 dots, 8 characters
ADRAM: 16 × 8 bits
DCRAM: 64 × 8 bits

• Instruction functions
Display on/off control
Display shift
Display blink
Intensity adjustment (dimmer)

• Serial data input (DI, CL, and CE pins)

• Built-in reset circuit

• 64-pin flat package

Differences between the LC75710NE,
LC75711NE, and LC75712E

• The data in the built-in character generator ROM
(CGROM) differs between these products. All other
functions are identical.

Package Dimensions

unit: mm

3159-QFP64E

Preliminary

SANYO: QIP64E

[LC75710NE, 75711NE, 75712E]

LC75710NE, 75711NE, 75712E

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Dot Matrix VFD Display Controller/Driver

CMOS LSI

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

Pin Assignment and Sample Application Circuit

No. 4907-2/21

LC75710NE, 75711NE, 75712E

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V

Allowable Operating Ranges at Ta = –40 to +85°C, VDD= 4.5 to 5.5 V, VSS= 0 V

No. 4907-3/21

LC75710NE, 75711NE, 75712E

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage

V

DD

max V

DD

–0.3 to +6.5

V

V

FL

max V

FL

VDD– 55 to VDD+ 0.3

Input voltage

V

IN

1 OSCI –0.3 to VDD+ 0.3

V

V

IN

2 DI, CL, CE, RES –0.3 to +6.5

I

OUT

1 AM1 to AM35 1

Output current I

OUT

2 AA1 to AA3 10 mA

I

OUT

3 AA4 to AA8, G1 to G16 20

Allowable power dissipation Pd max

Ta ≤ 85°C, with up to 70% of the AM1 to AM35

400 mW

outputs driven
Operating temperature Topr –40 to +85 °C
Storage temperature Tstg –50 to +125 °C

Parameter Symbol Conditions min typ max Unit

Supply voltage

V

DD

V

DD

4.5 5.0 5.5
V

V

FL

V

FL

VDD– 50 V

DD

VIH1 DI, CL, CE 0.8 V

DD

5.5

Input high level voltage V

IH

2 RES 0.7 V

DD

5.5 V

V

IH

3 OSCI 0.7 V

DD

V

DD

Input low level voltage

V

IL

1 DI, CL, CE 0 0.2 V

DD

V

V

IL

2 RES, OSCI 0 0.3 V

DD

Guaranteed oscillator range f

OSC

OSCI, OSCO 1.0 2.7 3.5 MHz

Recommended external resistor R

OSC

OSCI, OSCO 10 kΩ

Recommended external capacitor C

OSC

OSCI, OSCO 30 pF

Minimum reset pulse width t

WRES

RES 1 µs

Low level clock pulse width t

øL

CL 0.5 µs

High level clock pulse width t

øH

CL 0.5 µs

Data setup time t

DS

DI, CL 0.5 µs

Data hold time t

DH

DI, CL 0.5 µs

CE wait time t

CP

CE, CL 0.5 µs

CE setup time t

CS

CE, CL 0.5 µs

CE hold time t

CH

CE, CL 0.5 µs

Electrical Characteristics within the Allowable Operating Ranges

Note: Since this IC incorporates high voltage ports it is easily damaged by static discharges. Therefore, extra care is required when handling this IC.

Block Diagram

No. 4907-4/21

LC75710NE, 75711NE, 75712E

Parameter Symbol Conditions min typ max Unit

Input high level current I

IH

DI, CL, CE, RES, OSCI: Vi = 5.5 V 5 µA

Input low level current I

IL

DI, CL, CE, RES, OSCI: Vi = 0 V –5 µA

V

OH

1 AM1 to AM35: IO= 1 mA VDD– 1.0

Output high level voltage

V

OH

2 AA1 to AA3: IO= 10 mA VDD– 1.0

V

V

OH

3 AA4 to AA8, G1 to G16: IO= 20 mA VDD– 2.0

V

OH

4 OSCO: IO= 0.5 mA VDD– 2.0 V

DD

Output low level voltage V

OL

OSCO: IO= –0.5 mA 0 2.0 V

Output off voltage V

OFF

AM1 to AM35, AA1 to AA8, G1 to G16: VFL= VDD– 50 V VDD– 49 V

Pull-down resistors

R

1

AM1 to AM35: VDD– VFL= 48 V 140 650

kΩ

R

2

AA1 to AA8, G1 to G16: VDD– VFL= 48 V 70 325

Oscillator frequency f

OSC

R = 10 kΩ, C = 30 pF 2.16 2.7 3.24 MHz

Hysteresis voltage V

H

DI, CL, CE 0.5 V

Supply current I

DD

Outputs open, f

OSC

= 2.7 MHz, VFL= VDD– 50 V 5 mA

Pin Functions

No. 4907-5/21

LC75710NE, 75711NE, 75712E

Pin No. Pin circuit Function

V

DD

V

SS

V

FL

DI
CL
CE

OSCI
OSCO

RES

AM1 to AM35
AA1 to AA3

AA4/G16
AA5/G15
AA6/G14
AA7/G13
AA8/G12

G1 to G11

TEST

1
1
1

1
1
1

1
1

1

38

5

11

1

Logic block power supply: +5 V (typical)
Logic block power supply: ground
Driver block power supply

Serial data interface

DI: Transfer data
CL: Synchronization clock
CE: Chip enable

External oscillator RC circuit connections

System reset input

Anode outputs
Pull-down resistors are built in.

Anode/grid outputs

These pins function as grid output pins when the number of
displayed digits is selected to be between 12 and 16 digits with
the “Grid register load” instruction.

Pull-down resistors are built in.

Grid outputs
Pull-down resistors are built in.

LSI testing
This pin must be connected to V

SS

during normal operation.

Block Functions

1. AC (address counter)
AC is a counter that provides addresses for DCRAM and ADRAM.
The address is modified automatically by internal operations to maintain the VFD display state.

2. DCRAM (data control RAM)
DCRAM is RAM that holds the display data, which is expressed as 8-bit character codes. (These character codes are
converted to 5 × 7 dot matrix patterns using the CGROM and CGRAM memories.) DCRAM has a capacity of 64 × 8
bits, and can hold the data for 64 characters. The relationship between the 6-bit DCRAM address in AC and the
display position on the VFD display is described below.

• When the DCRAM address in AC is 00H. (16 digits displayed)

However, the DCRAM address moves as follows when a display shift is performed by specifying MDATA.

Note: The 6-bit DCRAM addresses are expressed in hexadecimal.

3. ADRAM (additional data RAM)
ADRAM is RAM used to store ADATA display data. ADRAM has a 16 × 8-bit capacity and the stored display data
is output directly without using CGROM and CGRAM. The relationship between the 4-bit ADRAM address in AC
and the display position on the VFD display is described below.

• When the ACRAM address in AC is 0H. (16 digits displayed)

However, the ADRAM address moves as follows when a display shift is performed by specifying ADATA.

Note: DCRAM and ADRAM addresses are expressed in hexadecimal.

Example: When the DCRAM address is 3E

H

.

No. 4907-6/21

LC75710NE, 75711NE, 75712E

Display digit 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

DCRAM address (hexadecimal) 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00

Right shift

Display digit 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

DCRAM address (hexadecimal) 10 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01

Left shift

Display digit 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

DCRAM address (hexadecimal) 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 3F

Display digit 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

ADRAM address (hexadecimal) F E D C B A 9 8 7 6 5 4 3 2 1 0

Right shift

Display digit 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

ADRAM address (hexadecimal) 0 F E D C B A 9 8 7 6 5 4 3 2 1

Left shift

Display digit 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

ADRAM address (hexadecimal) E D C B A 9 8 7 6 5 4 3 2 1 0 F

DA5 DA4 DA3 DA2 DA1 DA0

1 1 1 1 1 0

DCRAM address

Hexadecimal Hexadecimal

ADRAM address

Hexadecimal

LSBMSB

DA0DA1DA2DA3DA4DA5

LSBMSB

RA0RA1RA2RA3

4. CGROM (character generator ROM)
CGROM is ROM that is used to generate the 160 different 5 × 7 dot matrix character patterns. It has a capacity of
160 × 35 bits. When 8-bit character codes are written to DCRAM, the CGROM character pattern corresponding to
this 8-bit character code is displayed at the VFD display position corresponding to the DCRAM address in AC.
Tables 3 to 5 show the correspondence between the character codes and the character patterns.

5. CGRAM (character generator RAM)
CGRAM is RAM to which user programs can write arbitrary data. Up to eight 5 × 7 dot matrix character patterns can
be stored in the CGRAM. CGRAM has a capacity of 8 × 35 bits.
To display a character pattern stored in CGRAM, write one of the character codes shown at the left of tables 3 to 5 to
DCRAM. The CGRAM character pattern will be displayed at the VFD position corresponding to the DCRAM
address in AC.

Reset Function

The LC75710NE series accepts a reset when a low level is applied to the RES pin. On a reset the LC75710NE series
creates a display with all VFD lamps turned off. However, note that the values in DCRAM, ADRAM, and CGRAM, as
well as the values of the duty cycle register (intensity) and the grid register (number of digits) are undefined following a
reset. Therefore, before turning on display with a display on/off control instruction, these values must be initialized. In
particular, the following instructions must be executed when power is first applied.

• Display blink

• DCRAM data write

• ADRAM data write (if ADRAM is used)

• CGRAM data write (if CGRAM is used) Initial state settings

• Set AC address

• Grid register load

• Intensity adjustment (dimmer)

After executing the above instructions the display must be turned on by executing a “Display on/off control” instruction.

Note that incorrect display may occur if the number of displayed digits and the intensity are not set up in advance. This
can occur in cases where a display on/off control instruction is executed before the grid register load and intensity
adjustment instructions are executed. To prevent this problem, always execute the following three instructions together
as a single set.

• Grid register load

• Intensity adjustment (dimmer)

• Display on/off control

No. 4907-7/21

LC75710NE, 75711NE, 75712E