Sanyo LC74782M Specifications

Ordering number : EN4989A

CMOS LSI

LC74782, 74782M

On-Screen Display Controller LSI

for VCR Products

Overview

The LC74782 and LC74782M are on-screen display CMOS LSIs that display characters and patterns on a TV screen under microprocessor control. The LC74782 and LC74782M display up to 12 lines of 24 characters, each in a 12 × 18 dot matrix.

Features

•Display structure: 12 lines × 24 characters (up to 288 characters)

•Character structure: 12 (horizontal) × 18 (vertical) dots

•Character sizes: Three size settings each in the vertical and horizontal directions

•Character set: 256 characters

•Display start position: 64 position settings each in the vertical and horizontal directions

•Blinking: In individual character units

•Blinking types: Two types with periods of about 0.5 and

1.0second

•Blanking: Whole font area blanking (12 × 18 dots)

•Background colors: 8 colors (in internal synchronization

mode): 4fSC (NTSC/PAL/PAL-M/ PAL-N)

Background colors: 4 colors (in internal synchronization mode): 2fSC (NTSC)

Background colors: 1 color (blue) (in internal synchronization mode): 2fSC (PAL/PAL-M/PAL-N)

•External control input: 8-bit serial input format

•Built-in sync separator circuit

•Character blanked data output

•Video output: Compound NTSC, PAL, PAL-N and PAL-M output

Package Dimensions

unit: mm

3067-DIP24S

[LC74782]

SANYO: DIP24S

unit: mm

3045B-MFP24

[LC74782M]

SANYO: MFP24

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

92595HA/63095TH (OT) No. 4989-1/16

LC74782, 74782M

Pin Functions

Pin No.

Symbol

Function

Description

VSS1

Ground

Ground connection (digital system ground)

XtalIN

Crystal oscillator connection

Used to connect the crystal oscillator and capacitor used to generate the internal

XtalOUT

synchronization signal, or to input an external clock (2fsc or 4fsc).

CTRL1

Crystal oscillator input switching

Switches between external clock input mode and crystal oscillator mode.

Low = crystal oscillator mode, high = external clock mode

Outputs the blank signal (the OR of the character and border signals). (Outputs a composite

BLANK

Blanking output

sync signal when MOD0 is high.) Outputs the crystal oscillator clock during reset (when the

RST

pin is low), but can be set up to not output this signal by microprocessor command.

OSCIN

LC oscillator connection

Connections for the coil and capacitor that form the oscillator that generates the character

OSCOUT

output dot clock.

Outputs the character signal. (Functions as the external synchronization signal discrimination

signal output pin when MOD0 is high, and outputs the state of the judgment as to whether the

CHARA

Character output

external synchronization signal is present or not. Outputs a high level when the synchronization

signal is present.) Outputs the dot clock (LC oscillator) during reset, but can be set up to not

output this signal by microprocessor command.

Enable input

Serial data input enable input. Serial data input is enabled when low. A pull-up resistor is built in

(hysteresis input).

SCLK

Clock input

Serial data input clock input.

A pull-up resistor is built in (hysteresis input).

SIN

Data input

Serial data input. A pull-up resistor is built in (hysteresis input).

VDD2

Power supply

Composite video signal level adjustment power supply pin (analog system power supply).

CVOUT

Video signal output

Composite video signal output

Must be either connected to ground or left open.

CVIN

Video signal input

Composite video signal input

VDD1

Power supply

Power supply (+5 V: digital system power supply)

Video signal input for the built-in sync separator circuit (Used for either horizontal

SYNIN

Sync separator circuit input

synchronization signal or composite sync signal input when the built-in sync separator circuit is

not used.)

SEPC

Sync separator circuit bias voltage

Built-in sync separator circuit bias voltage monitor pin

Built-in sync separator circuit composite sync signal output. (When MOD1 is high, outputs a high

SEPOUT

Composite sync signal output

level during internal synchronization and a low level during external synchronization.) (Outputs

the SYNIN input signal when the internal sync separator circuit is not used.)

SEPIN

Vertical synchronization

Inputs a vertical synchronization signal created by integrating the SEPOUT pin output signal. An

signal input

integrator must be attached at the SEPOUT pin. This pin must be tied to VDD1 if unused.

The setting indicated by this pin takes priority in switching between the NTSC, PAL, PAL-M and

CTRL2

NTSC/PAL-M switching input

PAL-N formats. A low level selects NTSC after a reset. The microprocessor command NTSC,

PAL, PAL-M, or PAL-N setting is valid. High = PAL-M format.

Controls whether or not the

signal is input to the SEPIN input. Low =

input,

CTRL3

SEPIN input control

VSYNC

high =

VSYNC

not input.

RST

Reset input

System reset input. A pull-up resistor is built in (hysteresis input).

VDD1

Power supply (+5 V)

Power supply (+5 V: digital system power supply)

No. 4989-2/16

LC74782, 74782M

Pin Assignment

Specifications

Absolute Maximum Ratings at Ta = 25°C

Parameter	Symbol	Conditions	Ratings	Unit

Maximum supply voltage	VDD max	VDD1 and VDD2 pins	VSS – 0.3 to VSS + 7.0	V
Maximum input voltage	VIN max	All pins	VSS – 0.3 to VDD + 0.3	V
Maximum output voltage	VOUT max	BLANK, CHARA and SEPOUT pins	VSS – 0.3 to VDD + 0.3	V
Allowable power dissipation	Pd max	Ta = 25°C	350	mW

Operating temperature	Topr		–30 to +70	°C

Storage temperature	Tstg		–40 to +125	°C

Allowable Operating Ranges at Ta = –30 to +70°C

Parameter

Symbol

Conditions

min

typ

max

Unit

Supply voltage

VDD1

VDD1 pin

4.5

5.0

5.5

VDD2

VDD2 pin

4.5

5.0

1.27 VDD1

VIH1

0.8 VDD1

VDD1 + 0.3

Input high level voltage

RST, CS, SIN and SCLK pins

VIH2

CTRL1, CTRL2, CTRL3 and SEPIN pins

0.7 VDD1

VDD1 + 0.3

VIL1

SIN and SCLK pins

VSS – 0.3

0.2 VDD1

Input low level voltage

RST,

CS,

VIL2

CTRL1, CTRL2, CTRL3 and SEPIN pins

VSS – 0.3

0.3 VDD1

CS, SIN and SCLK pins, applies to pins set

Pull-up resistance

RPU

RST,

kΩ

by options.

Composite video input voltage

VIN1

CVIN pin: VDD1 = 5 V

2.0

Vp-p

VIN2

SYNIN pin: VDD1 = 5 V

2.0

2.5

Vp-p

Input voltage

VIN3

XtalIN pin (in external clock input mode),

0.10

5.0

Vp-p

fin = 2fsc or 4fsc: VDD1 = 5 V

FOSC1

XtalIN and XtalOUT oscillator pins (2fsc: NTSC)

7.159

MHz

FOSC1

XtalIN and XtalOUT oscillator pins (4fsc: NTSC)

14.318

MHz

FOSC1

XtalIN and XtalOUT oscillator pins (2fsc: PAL)

8.867

MHz

FOSC1

XtalIN and XtalOUT oscillator pins (4fsc: PAL)

17.734

MHz

Oscillator frequency

FOSC1

XtalIN and XtalOUT oscillator pins (2fsc: PAL-M)

7.151

MHz

FOSC1

XtalIN and XtalOUT oscillator pins (4fsc: PAL-M)

14.302

MHz

FOSC1

XtalIN and XtalOUT oscillator pins (2fsc: PAL-N)

7.164

MHz

FOSC1

XtalIN and XtalOUT oscillator pins (4fsc: PAL-N)

14.328

MHz

FOSC2

OSCIN and OSCOUT oscillator pins (LC oscillator)

MHz

Note: If the XtalIN pin is used in clock input mode, be sure to prevent input noise from becoming a problem.

No. 4989-3/16

LC74782, 74782M

Electrical Characteristics at Ta = –30 to +70°C, VDD1 = 5 V unless otherwise specified

Parameter

Symbol

Conditions

min

typ

max

Unit

Input off leakage current

Ileak1

CVIN pin

µA

Output off leakage current

Ileak2

CVOUT pin

µA

Output high level voltage

VOH1

BLANK, CHARA and SEPOUT pins: VDD1 = 4.5 V,

3.5

IOH = –1.0 mA

Output low level voltage

VOL1

BLANK, CHARA and SEPOUT pins: VDD1 = 4.5 V,

1.0

IOH = 1.0 mA

SIN, SCLK, CTRL1, CTRL3 and SEPIN pins:

IIH

RST,

CS,

µA

Input current

VIN = VDD1

IIL

CTRL1, CTRL2, CTRL3 and OSCIN pins: VIN = VSS1

–1

µA

IDD1

VDD1 pin; all outputs: open, Xtal: 7.159 MHz,

Operating current drain

LC: 8 MHz

IDD2

VDD2 pin: VDD2 = 5 V

Sync level

VSN

CVOUT pin

VDD1 = 5.0 V,

0.70

0.82

0.94

VDD2 = 5.0 V

0.91

1.03

1.15

Pedestal level

VPD

CVOUT pin

VDD1 = 5.0 V,

1.31

1.43

1.55

VDD2 = 5.0 V

1.53

1.65

1.77

Color burst low level

VCBL

CVOUT pin

VDD1 = 5.0 V,

1.00

1.12

1.24

VDD2 = 5.0 V

1.21

1.33

1.45

Color burst high level

VCBH

CVOUT pin

VDD1 = 5.0 V,

1.63

1.75

1.87

VDD2 = 5.0 V

1.84

1.96

2.08

Background color low level

VRSL

CVOUT pin

VDD1 = 5.0 V,

1.47

1.59

1.71

VDD2 = 5.0 V

1.68

1.80

1.92

Background color high level

VRSH

CVOUT pin

VDD1 = 5.0 V,

1.99

2.11

2.23

VDD2 = 5.0 V

2.19

2.31

2.43

Border level 0

VBK0

CVOUT pin

VDD1 = 5.0 V,

1.42

1.54

1.66

VDD2 = 5.0 V

1.63

1.75

1.87

Border level 1

VBK1

CVOUT pin

VDD1 = 5.0 V,

1.99

2.11

2.23

VDD2 = 5.0 V

2.19

2.31

2.43

Character level

VCHA

CVOUT pin

VDD1 = 5.0 V,

2.58

2.70

2.82

VDD2 = 5.0 V

2.78

2.90

3.02

Note: 1. When the sync level is 0.8 V. 2. When the sync level is 1.0 V.

Timing Characteristics at Ta = –30 to +70°C, VDD1 = 5 ± 0.5 V

Parameter	Symbol			Conditions			min	typ	max	Unit

Minimum input pulse width	tW (SCLK)	SCLK pin					200			ns
Minimum input pulse width	tW (CS)
	tW (CS)	CS pin (the period when			CS	is high)	1			µs
	tSU (CS)		pin				200			ns
Data setup time	tSU (CS)	CS	pin				200			ns
Data setup time	tSU (SIN)	SIN pin					200			ns
	tSU (SIN)	SIN pin					200			ns
	th (CS)		pin				2			µs
Data hold time	th (CS)	CS	pin				2			µs
Data hold time	th (SIN)	SIN pin					200			ns
	th (SIN)	SIN pin					200			ns
One word write time	tword	8-bit data write time					4.2			µs
One word write time	twt	RAM data write time					1			µs
	twt	RAM data write time					1			µs

No. 4989-4/16

LC74782, 74782M

Serial Data Input Timing

No. 4989-5/16

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