Sanyo LC74781M Specifications

92595HA/63095TH (OT) No. 4988-1/16

Overview

The LC74781 and LC74781M are on-screen display
CMOS LSIs that display characters and patterns on a TV
screen under microprocessor control. The LC74781 and
LC74781M display up to 12 lines of 24 characters, each in
a 12 × 18 dot matrix.

Features

• Display structure: 12 lines × 24 characters (up to

288 characters)

• Character structure: 12 (horizontal) × 18 (vertical) dots

• Character sizes: Three size settings each in the vertical
and horizontal directions

• Character set: 128 characters

• Display start position: 64 position settings each in the
vertical and horizontal directions

• Blinking: In individual character units

• Blinking types: Two types with periods of about 0.5 and

1.0 second

• Blanking: Whole font area blanking (12 × 18 dots)

• Background colors: 8 colors (in internal synchronization

mode): 4fSC (NTSC/PAL/PAL-M/
PAL-N)

Background colors: 4 colors (in internal synchronization

mode): 2fSC (NTSC)

Background colors: 1 color (blue) (in internal

synchronization mode): 2fSC
(PAL/PAL-M/PAL-N)

• External control input: 8-bit serial input format

• Built-in sync separator circuit

• Character blanked data output

• Video output: Compound NTSC, PAL, PAL-N and
PAL-M output

Package Dimensions

unit: mm

3067-DIP24S

SANYO: DIP24S

[LC74781]

unit: mm

3045B-MFP24

SANYO: MFP24

[LC74781M]

CMOS LSI

Ordering number : EN4988A

LC74781, 74781M

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

On-Screen Display Controller LSI

for VCR Products

Pin Functions

No. 4988-2/16

LC74781, 74781M

Pin No. Symbol Function Description

1 V

SS

1 Ground Ground connection (digital system ground)

2 Xtal

IN

Crystal oscillator connection

Used to connect the crystal oscillator and capacitor used to generate the internal

3 Xtal

OUT

synchronization signal, or to input an external clock (2fsc or 4fsc).

4 CTRL1 Crystal oscillator input switching

Switches between external clock input mode and crystal oscillator mode.
Low = crystal oscillator mode, high = external clock mode

Outputs the blank signal (the OR of the character and border signals). (Outputs a composite

5 BLANK Blanking output sync signal when MOD0 is high.) Outputs the crystal oscillator clock during reset (when the

RST pin is low), but can be set up to not output this signal by microprocessor command.

6 OSC

IN

LC oscillator connection

Connections for the coil and capacitor that form the oscillator that generates the character

7 OSC

OUT

output dot clock.
Outputs the character signal. (Functions as the external synchronization signal discrimination

signal output pin when MOD0 is high, and outputs the state of the judgment as to whether the

8 CHARA Character output external synchronization signal is present or not. Outputs a high level when the synchronization

signal is present.) Outputs the dot clock (LC oscillator) during reset, but can be set up to not
output this signal by microprocessor command.

9 CS Enable input

Serial data input enable input. Serial data input is enabled when low. A pull-up resistor is built in
(hysteresis input).

10 SCLK Clock input

Serial data input clock input.

A pull-up resistor is built in (hysteresis input).
11 SIN Data input Serial data input. A pull-up resistor is built in (hysteresis input).
12 V

DD

2 Power supply Composite video signal level adjustment power supply pin (analog system power supply).

13 CV

OUT

Video signal output Composite video signal output
14 NC Must be either connected to ground or left open.
15 CV

IN

Video signal input Composite video signal input
16 V

DD

1 Power supply Power supply (+5 V: digital system power supply)

Video signal input for the built-in sync separator circuit (Used for either horizontal

17 SYN

IN

Sync separator circuit input synchronization signal or composite sync signal input when the built-in sync separator circuit is

not used.)

18 SEP

C

Sync separator circuit bias voltage Built-in sync separator circuit bias voltage monitor pin

Built-in sync separator circuit composite sync signal output. (When MOD1 is high, outputs a high

19 SEP

OUT

Composite sync signal output level during internal synchronization and a low level during external synchronization.) (Outputs

the SYN

IN

input signal when the internal sync separator circuit is not used.)

20 SEP

IN

Vertical synchronization Inputs a vertical synchronization signal created by integrating the SEP

OUT

pin output signal. An

signal input integrator must be attached at the SEP

OUT

pin. This pin must be tied to VDD1 if unused.

The setting indicated by this pin takes priority in switching between the NTSC, PAL, PAL-M and

21 CTRL2 NTSC/PAL-M switching input PAL-N formats. A low level selects NTSC after a reset. The microprocessor command NTSC,

PAL, PAL-M, or PAL-N setting is valid. High = PAL-M format.

22 CTRL3 SEP

IN

input control

Controls whether or not the VSYNC signal is input to the SEP

IN

input. Low = VSYNC input,

high = VSYNC not input.
23 RST Reset input System reset input. A pull-up resistor is built in (hysteresis input).
24 V

DD

1 Power supply (+5 V) Power supply (+5 V: digital system power supply)

Pin Assignment

Specifications

Absolute Maximum Ratings at Ta = 25°C

Allowable Operating Ranges at Ta = –30 to +70°C

Note: If the XtalINpin is used in clock input mode, be sure to prevent input noise from becoming a problem.

No. 4988-3/16

LC74781, 74781M

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage V

DD

max VDD1 and VDD2 pins VSS– 0.3 to VSS+ 7.0 V

Maximum input voltage V

IN

max All pins VSS– 0.3 to VDD+ 0.3 V

Maximum output voltage V

OUT

max BLANK, CHARA and SEP

OUT

pins VSS– 0.3 to VDD+ 0.3 V
Allowable power dissipation Pd max Ta = 25°C 350 mW
Operating temperature Topr –30 to +70 °C
Storage temperature Tstg –40 to +125 °C

Parameter Symbol Conditions min typ max Unit

Supply voltage

V

DD

1 VDD1 pin 4.5 5.0 5.5 V

V

DD

2 VDD2 pin 4.5 5.0 1.27 VDD1 V

Input high level voltage

V

IH

1 RST, CS, SIN and SCLK pins 0.8 VDD1 VDD1 + 0.3 V

V

IH

2 CTRL1, CTRL2, CTRL3 and SEPINpins 0.7 VDD1 VDD1 + 0.3 V

Input low level voltage

V

IL

1 RST, CS, SIN and SCLK pins VSS– 0.3 0.2 VDD1 V

V

IL

2 CTRL1, CTRL2, CTRL3 and SEPINpins VSS– 0.3 0.3 VDD1 V

Pull-up resistance R

PU

RST, CS, SIN and SCLK pins, applies to pins set

25 50 90 kΩ

by options.

Composite video input voltage

V

IN

1 CVINpin: VDD1 = 5 V 2.0 Vp-p

V

IN

2 SYNINpin: VDD1 = 5 V 2.0 2.5 Vp-p

Input voltage V

IN

3

Xtal

IN

pin (in external clock input mode),

0.10 5.0 Vp-p

f

in

= 2fsc or 4fsc: VDD1 = 5 V

F

OSC

1 XtalINand Xtal

OUT

oscillator pins (2fsc: NTSC) 7.159 MHz

F

OSC

1 XtalINand Xtal

OUT

oscillator pins (4fsc: NTSC) 14.318 MHz

F

OSC

1 XtalINand Xtal

OUT

oscillator pins (2fsc: PAL) 8.867 MHz

F

OSC

1 XtalINand Xtal

OUT

oscillator pins (4fsc: PAL) 17.734 MHz

Oscillator frequency F

OSC

1 XtalINand Xtal

OUT

oscillator pins (2fsc: PAL-M) 7.151 MHz

F

OSC

1 XtalINand Xtal

OUT

oscillator pins (4fsc: PAL-M) 14.302 MHz

F

OSC

1 XtalINand Xtal

OUT

oscillator pins (2fsc: PAL-N) 7.164 MHz

F

OSC

1 XtalINand Xtal

OUT

oscillator pins (4fsc: PAL-N) 14.328 MHz

F

OSC

2 OSCINand OSC

OUT

oscillator pins (LC oscillator) 5 10 MHz

Electrical Characteristics at Ta = –30 to +70°C, VDD1 = 5 V unless otherwise specified

Note: 1. When the sync level is 0.8 V.

2. When the sync level is 1.0 V.

Timing Characteristics at Ta = –30 to +70°C, VDD1 = 5 ± 0.5 V

No. 4988-4/16

LC74781, 74781M

Parameter Symbol Conditions min typ max Unit

Input off leakage current I

leak

1 CVINpin 1 µA

Output off leakage current I

leak

2 CV

OUT

pin 1 µA

Output high level voltage V

OH

1

BLANK, CHARA and SEP

OUT

pins: VDD1 = 4.5 V,

3.5 V

I

OH

= –1.0 mA

Output low level voltage V

OL

1

BLANK, CHARA and SEP

OUT

pins: VDD1 = 4.5 V,

1.0 V

I

OH

= 1.0 mA

Input current

I

IH

RST, CS, SIN, SCLK, CTRL1, CTRL3 and SEPINpins:

1 µA

V

IN

= VDD1

I

IL

CTRL1, CTRL2, CTRL3 and OSCINpins: VIN= VSS1 –1 µA

Operating current drain

I

DD

1

V

DD

1 pin; all outputs: open, Xtal: 7.159 MHz,

15 mA

LC: 8 MHz

I

DD

2 VDD2 pin: VDD2 = 5 V 20 mA

Sync level V

SN

CV

OUT

pin

V

DD

1 = 5.0 V,

*1 0.70 0.82 0.94 V

V

DD

2 = 5.0 V

*2 0.91 1.03 1.15 V

Pedestal level V

PD

CV

OUT

pin

V

DD

1 = 5.0 V,

*1 1.31 1.43 1.55 V

V

DD

2 = 5.0 V

*2 1.53 1.65 1.77 V

Color burst low level V

CBL

CV

OUT

pin

V

DD

1 = 5.0 V,

*1 1.00 1.12 1.24 V

V

DD

2 = 5.0 V

*2 1.21 1.33 1.45 V

Color burst high level V

CBH

CV

OUT

pin

V

DD

1 = 5.0 V,

*1 1.63 1.75 1.87 V

V

DD

2 = 5.0 V

*2 1.84 1.96 2.08 V

Background color low level V

RSL

CV

OUT

pin

V

DD

1 = 5.0 V,

*1 1.47 1.59 1.71 V

V

DD

2 = 5.0 V

*2 1.68 1.80 1.92 V

Background color high level V

RSH

CV

OUT

pin

V

DD

1 = 5.0 V,

*1 1.99 2.11 2.23 V

V

DD

2 = 5.0 V

*2 2.19 2.31 2.43 V

Border level 0 V

BK

0 CV

OUT

pin

V

DD

1 = 5.0 V,

*1 1.42 1.54 1.66 V

V

DD

2 = 5.0 V

*2 1.63 1.75 1.87 V

Border level 1 V

BK

1 CV

OUT

pin

V

DD

1 = 5.0 V,

*1 1.99 2.11 2.23 V

V

DD

2 = 5.0 V

*2 2.19 2.31 2.43 V

Character level V

CHA

CV

OUT

pin

V

DD

1 = 5.0 V,

*1 2.58 2.70 2.82 V

V

DD

2 = 5.0 V

*2 2.78 2.90 3.02 V

Parameter Symbol Conditions min typ max Unit

Minimum input pulse width

t

W (SCLK)

SCLK pin 200 ns

t

W (CS)

CS pin (the period when CS is high) 1 µs

Data setup time

t

SU (CS)

CS pin 200 ns

t

SU (SIN)

SIN pin 200 ns

Data hold time

t

h (CS)

CS pin 2 µs

t

h (SIN)

SIN pin 200 ns

One word write time

t

word

8-bit data write time 4.2 µs

t

wt

RAM data write time 1 µs

Serial Data Input Timing

No. 4988-5/16

LC74781, 74781M