Sanyo LC7455A Specifications

Ordering number : ENN5680A

CMOS IC

LC7455A/M

U.S. Closed Caption Signal Extraction IC

Overview

The LC7455A/M receives the composite video signal from V/C (Video Chroma) signal processor and extracts the closed caption data with several signals from the decoder IC or microcomputer, are then sent to the decoder IC.

Features

(1)Low power consumption due to CMOS process

(2)Accurate caption signal extraction using a built-in peak hold circuit and digital technology.

(3)

Power Requirement

:

5V± 10%

(4)

Package

LC7455A :

DIP16

LC7455M :

MFP18

Ver.1.01	D2700 RM (IM) Ohta No.5680-1/11
N1494

LC7455A/M

Pin Assignment

DIP16

MFP18

1

VSS1

CP 16

1

VSS1

CP 18

2

TEST

VSS2 17

2

TEST

VSS2 15

LN21

VDD2

3

16

3

LN21

VDD2 14

O/

/CFOUT

MOD1

4

15

E

4

O/

E

/CFOUT

MOD1 13

/CFIN

VCOR

5

14

HS

5

HS

/CFIN

VCOR

12

CPDT

CVIN

6

13

CPDT

CVIN

6

11

7

SCKIN

MOD0 12

SCKIN

MOD0

7

10

8

CE

VDD1 11

VDD1

8

CE

9

9

NC

NC

10

LC7455A

LC7455M

Pin Description

Terminal

Pin No

Function Description

DIP16

MFP18

MODE1

MODE2

MODE3

VSS1

1

1

Negative power supply for digital circuit

TEST

2

2

Test pin, Leave open in operation

LN21

3

3

Line 21H pulse output (Even field)

Line 21H pulse output

(Both field)

O/

E

/CFOUT

4

4

Field determination output

CF oscillation output terminal

Field determination output

/CFIN

5

5

output

CF oscillation input terminal

input

HS

Hsync

Hsync

CPDT

6

6

Caption data output (Nch open

drain)

SCKIN

7

7

Input for Caption-data-transmission clock

8

8

Chip select input

CE

VDD1

9

11

Positive power supply for digital circuit

MOD0

10

12

leave open

connect to VDD1

leave open

CVIN

11

13

Composite video input

VCOR

12

14

Built-in VCO frequency control

MOD1

13

15

leave open

leave open

connect to VDD1

VDD2

14

16

Positive power supply for analog

circuit

VSS2

15

17

Negative power supply for analog circuit

CP

16

18

Built-in PLL filter pin

*VDD1,VSS1are the power supply terminals for built-in digital circuit. And VDD2,VSS2 are the power supply terminals for built-in analog circuit. Connect like following figure to reduce the noise influence.

LC7455A/M

VDD1

Power supply

VSS1 VDD2

VSS2

No.5680-2/11

LC7455A/M

Package Dimension

(unit : mm)

3006B

SANYO : DIP-16

(unit : mm)

3095

SANYO : MFP-18

No.5680-3/11

LC7455A/M

System Block Diagram (DIP16)

	CP		VSS2				VDD2		MOD1
	16		15				14		13
PLL		PLL
(VCO)		reference clock
		A: MODE 2
						DATA PEAK HOLD
		B: MODE 3
						(DATA Slice)
		C: MODE 1

A B C

VCOR		CVIN		MOD0
12		11		10

CLAMP

HSYNC PEAK HOLD

(Hsync Slice)

VDD1

9

				DATA	SLICER
						Data
						OUTPUT CONTROL
			O/E 1/32 Divider			DATA OUTPUT
						BUFFER
		(MODE1,3)		Clock Generator
				(MODE2)	(MODE2)
1	2	3		4	5	6	7	8
VSS	TEST	LN21		/CFOUT	/CFIN	CPDT	SCKIN	CE
				E	HS
				O/

Mode Description

	Terminal		MODE	Applications	Operation
	MOD1	MOD0
	Leave open	Leave open	MOD1	VTR	•Extraction of Line-21 data of the even field Built-in PLL circuit uses the
					horizontal synchronized signal separated from C-Video signal as the reference of
					PLL operation.
	Leave open	Connect	MOD2	VTR	•Extraction of Line-21 data of the even field Built-in PLL circuit uses
		to			the 1/32-divided signal from 508KHz oscillation as the reference of the
		VDD1			PLL operation.
					Note that the 508KHz oscillation requires 508KHz-ceramic resonator externally.
	Connect	Leave open	MOD3	NTSC-TV	•Extraction of Line-21 data of the even/Odd field Built-in PLL circuit uses the
	to				horizontal synchronized signal generated from external Fly-Back circuit as the
	VDD1				reference of the PLL operation.

No.5680-4/11