Sanyo LC7455A Specifications
Ordering number : ENN5680A
LC7455A/M
U.S. Closed Caption Signal Extraction IC
Overview
The LC7455A/M receives the composite video signal from V/C (Video Chroma) signal processor and extracts the closed
caption data with several signals from the decoder IC or microcomputer, are then sent to the decoder IC.
Features
(1) Low power consumption due to CMOS process
(2) Accurate caption signal extraction using a built-in peak hold circuit and digital technology.
(3) Power Requirement : 5V± 10%
(4) Package LC7455A : DIP16
LC7455M : MFP18
CMOS IC
Ver.1.01
N1494
D2700 RM (IM) Ohta No.5680-1/11
LC7455A/M
Pin Assignment
DIP16 MFP18
1
2
3
4
5
6
7
8
9
VSS1
TEST
LN21
O/
/CFOUT
E
/CFIN
HS
CPDT
SCKIN
CE
NC
1
2
3
VSS1
TEST
LN21
CP
VSS2
VDD2
16
15
14
4
O/
/CFOUT
E
MOD1
13
/CFIN
5
6
7
HS
CPDT
SCKIN
VCOR
CVIN
MOD0
12
11
10
8
CE
VDD1
9
CP
VSS2
VDD2
MOD1
VCOR
CVIN
MOD0
VDD1
NC
18
17
16
15
14
13
12
11
10
LC7455A LC7455M
Pin Description
Terminal
VSS1 1 1
TEST 2 2
LN21 3 3
O/E/CFOUT
/CFIN
HS
CPDT 6 6
SCKIN 7 7
CE
VDD1 9 11
MOD0 10 12
CVIN 11 13
VCOR 12 14
MOD1 13 15
VDD2 14 16
VSS2 15 17
CP 16 18
* VDD1,VSS1are the power supply terminals for built-in digital circuit. And VDD2,VSS2 are the power supply terminals for
built-in analog circuit. Connect like following figure to reduce the noise influence.
Pin No Function Description
DIP16 MFP18 MODE1 MODE2 MODE3
Negative power supply for digital circuit
Test pin, Leave open in operation
4 4
5 5
8 8
Line 21H pulse output (Even field) Line 21H pulse output
Field determination output CF oscillation output terminal Field determination output
output
Hsync
Caption data output (Nch open drain)
Input for Caption-data-transmission clock
Chip select input
Positive power supply for digital circuit
leave open connect to VDD1 leave open
Composite video input
Built-in VCO frequency control
leave open leave open connect to VDD1
Positive power supply for analog circuit
Negative power supply for analog circuit
Built-in PLL filter pin
CF oscillation input terminal
(Both field)
input
Hsync
LC7455A/M
Power
supply
VDD1
VSS1
VDD2
VSS2
No.5680-2/11
Package Dimension
(unit : mm)
3006B
(unit : mm)
3095
LC7455A/M
SANYO : DIP-16
SANYO : MFP-18
No.5680-3/11
LC7455A/M
N
N
(
)
(
)
(
)
System Block Diagram (DIP16)
13
MOD1
16
CP
15
VSS2
14
VDD2
12
VCOR
11
CVIN
10
MOD0
VDD1
9
PLL
(VCO)
PLL
reference clock
A: MODE 2
B: MODE 3
C: MODE 1
A B C
DATA PEAK HOLD
(DATA Slice)
HSYNC
(
Hsync
CLAMP
PEAK HOLD
Slice)
DATA SLICER
Data
OUTPUT CONTROL
1
VSS
2
TEST
MODE1,3
3
LN21
O/
E
MODE2
1/32 Divider
Clock Generator
4
/CFOUT
E
O/
MODE2
5
/CFI
HS
DATA OUTPUT
BUFFER
6
CPDT
7
SCKI
8
CE
Mode Description
Terminal
MOD1 MOD0
Leave open Leave open MOD1 VTR •Extraction of Line-21 data of the even field Built-in PLL circuit uses the
Leave open Connect
to
VDD1
Connect
Leave open MOD3 NTSC-TV •Extraction of Line-21 da ta of the even/Odd field Bu ilt-in PLL circuit u ses the
to
VDD1
MODE Applications Operation
horizontal synchr on ized s ign al separ at ed from C-V ideo si gnal as the r eference of
PLL operation.
MOD2 VTR
•Extraction of Line-21 data of the even field Built-in PLL circuit uses
the 1/32-divided signal from 508KHz oscilla- tion as the reference of the
PLL operation.
Note that the 508KHz oscillation requires 508KHz-ceramic resonator externally.
horizontal synchronized signal generated fr om external Fly-Back circuit as the
reference of the PLL operation.
No.5680-4/11
Loading...