PIP Controllers
CMOS IC
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
Overview
The LC74401E, LC74402, and LC74402E are memory
controllers for TV set and VCR PIP (picture in picture)
systems. Since these LSIs include three D/A converter
circuits, a component PIP system can be constructed by
combining one of these LSIs with memory and an A/D
converter such as the LC7480.
Features
• Horizontal resolution: 600 TV lines
*1
• Three D/A converters (for the Y, R-Y, and B-Y signals)
are incorporated in the PIP memory controller block.
• High image quality is supported by vertical filter
function frame memory processing*2.
•I2C bus controlled.
• Built-in PLL circuit (requires an external LPF)
• Supports NTSC, PAL, and multiple (NTSC-PAL)
formats
• External control functions (only provided by the
LC74401E)
— 8-bit D/A converter (PWM): Six pins
— General-purpose ports: Four pins
• Sub-screen specifications
— Number of sub-screens: 1-8
*2
— Display on/off and frame on/off/color switching,
wipe function
— Supports switching between fixed (4 corners) and
arbitrary (8-bit specification of vertical and
horizontal position) display positions.
— Size: Area: 1/4, 1/9, 1/16, Vertical compression: 1/2,
1/3, 1/4; Horizontal compression: 2/3, 1/3, 1/6
Note: Horizontal compression can be adjusted by
changing the PLL divisor.
The display area can be changed independently
in the vertical and horizontal directions.
— Horizontal resolution (Y signal): About 250 dots
— Gradation (quantization): 64 (6 bits)
• Operating supply voltage: 5 V ± 10%
• QFP80E: LC74401E
• DIP64S: LC74402-Pin assignment identical to the
LC7442 (except for the serial control pins)
• QFP64E: LC74402E-Pin assignment identical to the
LC7442E (except for the serial control pins)
Note 1
When the main screen synchronization PLL has the standard value
(PLL7 to PLL3 = 10011)
Note 2: The specifications depend on the amount of
external memory as listed in the table below.
o: Frame display of both dynamic and static images supported.
(Frame memory processing)
▲▲: Frame display of dynamic images only supported.
✕: Not supported.
Note: The number of sub-screens listed in the table above are doubled
in split mode. (However, image quality is reduced.)
D/A Clock
Y 15.00 MHz
R-Y 3.75 MHz
B-Y 3.75 MHz
Display memory 256 K 1 M
One screen ▲▲ o
Two screens ✕ o
Three screens ✕ ▲▲
Four screens ✕ ▲▲