SANYO LC4608C Datasheet

Overview

The LC4608C is a driver for ink-jet printer heads with 64­bit output. It converts 4-bit parallel input into 16-step gray
scale output by regulating the transmission gate’s output
time.

Features

This 64-bit CMOS driver with 16-step gray scale output
and high withstand voltage offers the following features.

• Built-in 64 × 4-bit static shift register

• Built-in 64 × 4-bit static latch

• 16-step gray scale output from 4-bit parallel input

• Built-in 64 × 2-channel transmission gate output

• Transmission gate on resistance of 60 Ω (typ.) 100 Ω

(max)

• CMOS process with high withstand voltage (42 V)

CMOS IC

33198RM (OT) No. 5782-1/11

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Printer Head Driver

LC4608C

Ordering number : EN5782

Parameter Symbol Conditions Ratings Unit

Supply voltage (logic) V

DD

–0.5 to +7.0 V

Supply voltage (high withstand voltage circuits) V

H

–0.5 to +42 V

Driver output breakdown voltage BV

DO

–0.5 to +42 V

Driver output current I

DO

Peak value within allowable operating range ±400 mA

Input current I

IN

–20 to +20 mA

Input voltage (logic) V

IN

1 –0.5 to VDD+0.5 V

Input voltage (COM, output) V

IN

2 –0.5 to VH+0.5 V
Operating temperature Topr –10 to +90 °C
Storage temperature Tstg –65 to +150 °C
Junction temperature Tj –10 to +125 °C

Specifications

Maximum Ratings

Parameter Symbol Conditions

Ratings

Unit

min typ max

Supply voltage

V

DD

4.5 5.0 5.5 V

V

H

*1 24.0 40.0 V

Input voltage

V

IN

0V

DD

V

COM 0 V

H

V

Output current DOn I

DO

VH= 40 V *2 200 400 mA

Clock frequency f

clk

8.0 MHz

Data setup time t

ds

40 ns

Data hold time t

dh

40 ns

Latch setup time t

Ls

140 ns

Clock pulse width t

wCLK

50 ns

Latch pulse width t

wLAT

80 ns

Allowable Operating Ranges at VDD= 5.0 V±10%, Topr = –10 to +90°C unless otherwise specified

Continued on next page.

No. 5782-2/11

LC4608C

Parameter Symbol Conditions

Ratings

Unit

min typ max

STBCLK frequency f

STB

1.0 MHz

CLK → LOAD setup time t

SL

80 ns

LOAD → CLK hold time t

HL

80 ns

LOAD pulse width t

WL

80 ns

STBCLK → LOAD setup time t

STBL

80 ns

LOAD → STBCLK hold time t

LSTB

80 ns

Clock rising edge time t

r

35 ns

Clock falling edge time t

f

35 ns

Latch rising edge time t

lr

70 ns

Latch falling edge time t

lf

70 ns

Operating temperature Tjopr –1.0 +90 °C

Continued from preceding page.

Note : 1. The figures for normal operation are a load capacitance Cpzt of 1 nF, a power supply voltage VHof 30 V, and a max input level COMmax of 25 V.

2. Value for V

H

= 40 V, COMmax = 40 V, frequency = 35 kHz, and duty factor = 1/100.

Note : 1. The sign is negative for incoming current and positive for outgoing current.

2. –I

IH

1 applies to the following input pins: SI0 to SI3, CLK, LAT, LOAD, STBCLK, and STB1 to STB3. –IIHapplies to the following input pins: STB4

and STB5.

3. I

IL

1 applies to the following input pins: SI0 to SI3, CLK, LAT, LOAD, STBCLK, and STB1 to STB5.

Note : 5. The figures are for a load capacitance Cpzt of 1 nF and a power supply voltage V

H

of 30 V as measured with RL= 3 kΩ and COMn = 25 V DC.

Parameter Symbol Conditions

Ratings

Unit

min typ max

Input high-level voltage V

IH

VDD× 0.7 VDD+0.3 V

Input low-level voltage V

IL

–0.3 VDD× 0.3 V

Input high-level current *2

–I

IH

1 VDD= 5.0 V, VIH= 5.0 V 0 0.5 µA

–I

IH

2 VDD= 5.0 V, VIH= 5.0 V 0 50 100 µA
Input low-level current *3 I

IL

VDD= 5.0 V 0 0.5 µA

Output high- level voltage V

OHIO

= –400 µA VDD– 0.5 V

Output low-level voltage V

OLIO

= 400 µA 0.5 V

Output high-level current transmission gate

V

OHT

VDD= 5.0 V, VH= 40 V, COMn = 40 V,

39 39.4 V

voltage I

OHT

= 10 mA

Output low-level current transmission gate

V

OLT

VDD= 5.0 V, VH= 40 V, COMn = 40 V,

0.6 1.0 V

voltage –I

OHT

= 10 mA

Transmission gate on resistance R

ONVH

= 40 V, VDS= 3 V 60 100 Ω

Within chip

Transmission gate on resistance variation Rx –15 +15 Ω

Current drain I

DD

1 VDD– GND, fclk = 3.5 MHz, f

Sln

= 1.75 MHz –15 +15 Ω
Leakage current between pins ±INL Leakage current between pins 0 10 µA
Output leakage current I

LEAKVDD

= 5.0 V, VH= 42 V 0 100 µA

Electrical Characteristics
DC Characteristics at VDD= 5.0 V±10%, Tjopr = –10 to +90°C unless otherwise specified

2 (MAX – MIN) × 100

——————————

MAX + MIN

Parameter Symbol Conditions

Ratings

Unit

min typ max

SOn output rising edge time t

or

CL= 10 pF 50 ns

SOn input rising edge time t

of

CL= 10 pF 50 ns

STBn → DOn propagation delay time

t

dor

*5 1.0 µs

t

dof

*5 1.0 µs

CLK → SOn propagation delay time

t

sor

CL= 10 pF 140 ns

t

sof

CL= 10 pF 140 ns

Switching Characteristics at VDD= 5.0 V±10%, Tjopr = –10 to +90°C unless otherwise specified

Timing Chart 1

No. 5782-3/11

LC4608C

Timing Chart 2

Timing Chart 3

No. 5782-4/11

LC4608C

Usage Note

The power on and power off sequences must use the following orders.
Power on sequence: V

DD

→ 5-V input circuits→ VH→ COMn

Power off sequence: COMn → V

H

→ 5-V input circuits → V

DD

Block Diagram

Timing Chart 4

Level shift circuit

Gray scale

control logic

4-bit

counter

4-bit latche × 64

4-bit shift register × 64