SANYO LC4104C Datasheet

Overview

The LC4104 is a segment driver LSI for large-scale dot matrix LCD displays. The LC4104 latches 160-bits of display data transferred from the controller over a 4- or 8bit parallel interface and generates the LCD drive signals. In conjunction with the LC4102 common driver, the LC4104 forms a chip set that can drive large-screen LCD panels.

Features

• High-voltage CMOS (P-sub) process

• LCD drive voltage: 36 V

• Logic system power-supply voltage: 2.7 to 5.5 V

• Maximum fcp: 12 MHz (VDD= 5 V ±10%), 10 MHz (VDD= 2.7 to 4.5 V)

• Slim chip (The output pads are located along one of the

long sides.)

• Parallel input circuit can be switched between 4 and

8 bits.

• Output directionality switching

• DISPOFF function (Holds the LCD drive voltage at a

fixed level.)

• Display duty ratios: 1/160 to 1/480

• Appropriate for COG (chip on glass) mounting. (A gold

bump structure is adopted in the pad areas.)

• LC4104C: Chip product

CMOS LSI (P-sub)

Ordering number : EN *5194D

43098HA (OT)/73097HA (OT)/D3095HA (OT) No. 5194-1/9

Preliminary

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

LCD Dot Matrix Segment Driver

for STN Displays

LC4104C

Block Diagram

Specifications

The following electrical characteristics apply when sealed in a Sanyo standard PGA-208 package.

Absolute Maximum Ratings at VSS= 0 V

Note: V0, V2, V3, and V5 must obey the following inequalities: V

DDH

≥ V0 ≥V2 ≥ V

DDH

– 7 V, and 7 V ≥ V3 ≥ V5 ≥ VSS.

No. 5194-2/9

LC4104C

Parameter Symbol Conditions min typ max Unit

Maximum supply voltage V

max –0.3 7 V

Maximum supply voltage V

DDH

max –0.3 40 V

Maximum supply voltage V

max –0.3 +0.3 V

Input voltage V

D0 to D7, LOAD, CP, R/L, TEST, DISP, M, EIO1, EIO2,

–0.3 V

+ 0.3 V

Input voltage V0, V2 V0, V2 V

DDH

– 7 V

DDH

+ 0.3 V

Input voltage V3 V3 –0.3 V

+ 7 V Input voltage V5 V5 –0.3 +0.3 V Operating temperature Topr –20 +75 °C Storage temperature Tstg –55 +125 °C

Allowable Operating Ranges at Ta = –20 to +75°C, VSS= 0 V

Note: V0, V2, V3, and V5 must obey the following inequalities: V

DDH

≥ V0 ≥ V2 ≥ V

DDH

– 7 V, and 7 V ≥ V3 ≥ V5 ≥ VSS. At power on: First turn on the logic system power supply and then turn on the high-voltage system power supply. At power off: First turn off the high-voltage system power supply and then turn off the logic system power supply.

Allowable Operating Ranges at Ta = –20 to +75°C, VSS= 0 V, VDD= 5 V ± 10%

Note: * The clock rise time (tr) and fall time (tf) must obey inequalities ➀ and ② below.

➀: tr, tf <

②: tr, tf ≤ 50 ns

Allowable Operating Ranges at Ta = –20 to +75°C, VSS= 0 V, VDD= 2.7 to 4.5 V

Note: * The clock rise time (tr) and fall time (tf) must obey inequalities ➀ and ② below.

➀: tr, tf <

②: tr, tf ≤ 50 ns

– tw (cph) – tw (cpl)

fcp

– tw (cph) – tw (cpl)

fcp

No. 5194-3/9

LC4104C

Parameter Symbol Conditions min typ max Unit

Supply voltage V

2.7 5.5 V

Supply voltage V

DDH

20 36 V

Supply voltage V

0 V

Input high-level voltage V

D0 to D7, LOAD, CP, R/L, M, TEST, DISP, BS,

0.8 V

EIO1, EIO2

Input low-level voltage V

D0 to D7, LOAD, CP, R/L, M, TEST, DISP, BS,

0 0.2 V

EIO1, EIO2

Input voltage V0, V2 V0, V2 V

DDH

– 7 V

DDH

Input voltage V3 V3 0 V

SSH

+ 7 V

Input voltage V5 V5 0 V

Parameter Symbol Conditions min typ max Unit CP clock frequency fcp CP 12 MHz High-level load pulse width tw (ldH) LOAD 50 ns High-level clock pulse width tw (cpH) CP 20 ns Low-level clock pulse width tw (cpL) CP 20 ns LOAD/CP setup time tsu (ld) LOAD, CP 100 ns LOAD/CP hold time tho (ld) LOAD, CP 200 ns DATA/CP setup time tsu (cp) CP, D0 to D7 10 ns DATA/CP hold time tho (cp) CP, D0 to D7 10 ns EIO input setup time tsu (ei) CP, EIO1, EIO2 24 ns Clock rise time tr LOAD, CP* 50 ns Clock fall time tf LOAD, CP* 50 ns

Parameter Symbol Conditions min typ max Unit CP clock frequency fcp CP 10 MHz High-level load pulse width tw (ldH) LOAD 50 ns High-level clock pulse width tw (cpH) CP 37 ns Low-level clock pulse width tw (cpL) CP 37 ns LOAD/CP setup time tsu (ld) LOAD, CP 100 ns LOAD/CP hold time tho (ld) LOAD, CP 200 ns DATA/CP setup time tsu (cp) CP, D0 to D7 35 ns DATA/CP hold time tho (cp) CP, D0 to D7 35 ns EIO input setup time tsu (ei) CP, EIO1, EIO2 30 ns Clock rise time tr LOAD, CP* 50 ns Clock fall time tf LOAD, CP* 50 ns

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