SANYO LC4101C Datasheet

Overview

The LC4101C is a segment driver for large-scale dot
matrix LCD panels. It latches 240 bits of display data sent
from the controller over a 4-bit or 8-bit parallel connection
and generates the LCD drive signals. The LC4100C and
LC4101C form a large-screen LCD panel driver chip set.

Features

• Fabricated in a CMOS (P-sub) high-voltage process.

• LCD drive voltage: 36 V

• Logic system power-supply voltage: 3.0 to 5.5 V

•fcpmax: 12 MHz (VDD= 5 V ±10 %), 6.5 MHz (V

DD

= 3 to 4.5 V)

• 240 outputs

• Parallel input switchable between 4 and 8 bits

• DISPOFF function that locks the drive voltages output
to the LCD at fixed levels.

• Display duty: 1/160 to 1/480

CMOS LSI

Ordering number : EN5280A

O3096HA (OT)/43096HA (OT) No. 5280-1/9

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN

LCD Dot Matrix Segment Driver

for STN Displays

LC4101C

Specifications

Absolute Maximum Ratings at Ta = 25°C ± 2°C, standard VSS, V

EEn

= V

EE1

or V

EE2

, V

SSn

= V

SS1

or V

SS2

Note: The voltages V0, V2, V3, and V5must obey the relationships V

EEn

≥ V0≥ V2≥ VEE– 7, and 7 ≥ V3≥ V5≥ V

SSn

. (Unit: V)

Parameter Symbol Conditions Ratings Unit

V

DD

–0.3 to +7 V

Supply voltage V

EEn

–0.3 to +40 V

V

SSn

–0.3 to +0.3 V

V

IN

D0 to D7, LOAD, CP, L/R, BS, TEST,

–0.3 to V

DD

+ 0.3 V

DISP, DF, EIO1, EIO2

Input voltage V

0

, V2V0, V

2

V

EEn

– 7 to V

EEn

+ 0.3 V

V

3

V

3

–0.3 to V

SSn

+7 V

V

5

V

5

–0.3 to +0.3 V
Operating temperature Topr –20 to +75 °C
Storage temperature Tstg –55 to +125 °C

Allowable Operating Ranges at Ta = –20 to +75°C, standard VSS, V

EEn

= V

EE1

or V

EE2

, V

SSn

= V

SS1

or V

SS2

Note: 1. The voltages V0, V2, V3, and V5must obey the relationships V

EEn

≥ V0≥ V2≥ VEE– 7, and 7 ≥ V3≥ V5≥ V

SSn

. (Unit: V)

2. When turning on the power supplies, first turn on the logic system power supply and then turn on the high-voltage system power supply;
alternatively, turn both on at the same time.
When turning off the power supplies, first turn off the high-voltage system power supply and then turn off the logic system power supply;
alternatively, turn both off at the same time.

No. 5280-2/9

LC4101C

Parameter Symbol Conditions min typ max Unit

V

DD

3.0 5.5 V

Supply voltage V

EEn

20 36 V

V

SSn

0 V

Input high-level voltage V

IH

D0 to D7, CP, L/R, BS, DF, TEST, DISP,

0.8 V

DD

V

DD

V

EIO1, EIO2, LOAD

Input low-level voltage V

IL

D0 to D7, CP, L/R, BS, DF, TEST, DISP,

0 0.2 V

DD

V

EIO1, EIO2, LOAD

V

0

, V2V0, V

2

V

EEn

– 7 V

EEn

V

Input voltage V

3

V

3

0 V

SSn

+ 7 V

V

5

V

5

0 V

CP clock frequency f

cp

CP 12 MHz

High-level load

t

w (ldh)

LOAD 50 ns

pulse width
High-level clock

t

w (cph)

CP 28 ns

pulse width
Low-level clock

t

w (cpl)

CP 28 ns

V

DD

= pulse width

5 V ± 10%

Load clock frequency f

load

LOAD 1 MHz

LOAD/CP setup time t

su (ld)

LOAD, CP 30 ns

LOAD/CP hold time t

ho (ld)

LOAD, CP 200 ns

DATA/CP setup time t

su (cp)

CP, D0 to D7 28 ns

DATA/CP hold time t

ho (cp)

CP, D0 to D7 20 ns

EIO input setup time t

su (ei)

CP, EIO1, EIO2 30 ns

Clock rise time t

r

LOAD, CP 50 ns

Clock fall time t

f

LOAD, CP 50 ns

CP clock frequency f

cp

CP 6.5 MHz

High-level load

t

w (ldh)

LOAD 50 ns

pulse width
High-level clock

t

w (cph)

CP 40 ns

pulse width
Low-level clock

t

w (cpl)

CP 40 ns

V

DD

= pulse width

3 to 4.5 V

Load clock frequency f

load

LOAD 200 kHz

LOAD/CP setup time t

su (ld)

LOAD, CP 35 ns

LOAD/CP hold time t

ho (ld)

LOAD, CP 350 ns

DATA/CP setup time t

su (cp)

CP, D0 to D7 50 ns

DATA/CP hold time t

ho (cp)

CP, D0 to D7 50 ns

EIO input setup time t

su (ei)

CP, EIO1, EIO2 45 ns

Clock rise time t

r

LOAD, CP 50 ns

Clock fall time t

f

LOAD, CP 50 ns

Electrical Characteristics at Ta = –20 to +75°C, standard VSS, VDD= 3 to 5.5 V

Note: 1. With LOAD = 28 kHz, fcp = 6.5 MHz, fDF= 75 Hz, or with no output load. Input voltages VIHand VILmust be VDDand V

SS,

respectively.

2. The standby current drain rating assumes that the EIOn (input) are at V

DD

.

Block Diagram

No. 5280-3/9

LC4101C

Parameter Symbol Conditions min typ max Unit

Input high-level current I

IH

VIN= VDD: D0 to D7, CP, L/R, BS, DF, TEST, DISP,

1

EIO1, EIO2, LOAD

µA

Input low-level current I

IL

VIN= VSS: D0 to D7, CP, L/R, BS, DF, TEST, DISP,

–1 µA

EIO1, EIO2, LOAD

Output high-level voltage V

OHIO

= –0.4 mA: EIO1, EIO2 0.8 V

DD

V

DD

V

Output low-level voltage V

OL

IO= 0.4 mA: EIO1, EIO2 V

SS

0.2 V

DD

V

V

EE

= 20 V, V0– V0= 0.5 V, V2– V0= 0.5 V,

Output on resistance R

OUTV0

– V3= 0.5 V, V0– V5= 0.5 V, V0= 20 V, 0.8 1.6 kΩ

V

2

= 20 V, V3= 0 V, V5= 0 V: OUT1 to OUT240

Current drain I

DD

VDD= 3 to 5.5 V 7.5 µA

Operating current drain I

EE

VDD= 3 to 5.5 V, V

EEn

= 26 V*

1

3.0 mA

V

DD

= 5 V ± 10%, V

EEn

= 36 V 3.0 mA

Static current Istb *

2

750 µA