SANYO LB1999M Datasheet

Ordering number : EN5975

O3098RM (OT) No. 5975-1/8

Overview

The LB1999M is a 3-phase brushless motor driver that is
particularly appropriate for VCR capstan motor drivers.

Functions

· 3-phase full-wave drive

· Built-in torque ripple correction circuit (fixed correction
ratio)

· Built-in current limiter circuit and control characteristics
that include gain switching

· Upper and lower side output stage over-saturation
prevention circuit that does not require external
capacitors.

· FG amplifier with built-in Schmitt comparator

· Thermal shutdown circuit

Package Dimensions

unit: mm

3129-MFP36SLF

SANYO: MFP36SLF

[LB1999M]

LB1999M

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Three-Phase Brushless Motor Driver

for VCR Capstan Motors

Monolithic Digital IC

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

Allowable power dissipation, Pdmax — W

Ambient temperature, Ta — °C

Independent IC

Specifications

Absolute Maximum Ratings at Ta = 25°C

Allowable Operating Ranges at Ta = 25°C

Electrical Characteristics at Ta = 25°C, VCC= 5 V, VS= 15 V

Notes : 1.The torque ripple correction ratio is determined as follows from the Rf voltage waveform. Continued on next page.

2.Parameters that are indicated as design target values in the conditions column are not tested.

No. 5975-2/8

LB1999M

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage

V

CC

max 7 V

V

S

max 24 V

Maximum output current I

O

max 1.3 A
Allowable power dissipation Pd max Independent device 0.95 W
Operating temperature Topr –20 to + 75 °C
Storage temperature Tstg –55 to + 150 °C

Parameter Symbol Conditions Ratings Unit

Supply voltage

V

S

5 to 22 V

V

CC

4.5 to 5.5 V

Hall input amplitude V

HALL

Between the Hall inputs ±30 to ±80 mVo-p

GSENSE pin input range V

GSENSE

With respect to the control system ground –0.20 to + 0.20 V

Parameter Symbol Conditions

Ratings

Unit

min typ max

VCC supply current I

CC

RL = ∞, V

CTL

= 0 V (Quiescent) 12 18 mA

[Outputs]

V

O

sat1

I

O

= 500 mA, Rf = 0.5 Ω, Sink + Source

2.1 2.6 V

Output saturation voltage

V

CTL

= V

LIM

= 5 V

(With saturation prevention)

VOsat2

I

O

= 1.0 A, Rf = 0.5 Ω, Sink + Source

2.6 3.5 V

V

CTL

= V

LIM

= 5 V

(With saturation prevention)
Output leakage current IOleak 1.0 mA
[FR]
FR pin input threshold voltage V

FSR

2.25 2.50 2.75 V

FR pin input bias current I

B

(FSR) –5.0 µA
[Control]
CTLREF pin voltage V

CREF

2.37 2.50 2.63 V

CTLREF pin input range V

CREFIN

1.7 3.50 V

CTL pin input bias current I

B

(CTL) With V

CTL

= 5 V and the CTLREF pin open 8.0 µA

CTL pin control start voltage

V

CTL

(ST)

With Rf = 0.5 Ω, V

LIM

= 5 V, IO≥ 10 mA,

2.20 2.35 2.50 V

Hall input logic fixed (U, V, W = H, H, L)

CTL pin control switching voltage V

CTL

(ST2) With Rf = 0.5 Ω, V

LIM

= 5 V 3.00 3.15 3.30 V

CTL pin control Gm1 Gm (CTL)

With Rf = 0.5 Ω, ∆I

O

= 200 mA,

0.52 0.65 0.78 A/V

Hall input logic fixed (U, V, W = H, H, L)

CTL pin control Gm2 Gm2 (CTL)

With Rf = 0.5 Ω, ∆V

CTL

= 200 mV,

1.20 1.50 1.80 A/V

Hall input logic fixed (U, V, W = H, H, L)

[Current Limiter]
LIM current limit offset voltage Voff (LIM)

With Rf = 0.5 Ω, V

CTL

= 5 V, IO≥ 10 mA,

140 200 260 mV

Hall input logic fixed (U, V, W = H, H, L)

LIM pin input bias current I

B

(LIM)

With V

CTL

= 5 V and the V

CREF

pin open,

V

LIM

= 0 V

–2.5 µA

LIM pin current control level I

LIM

With Rf = 0.5 Ω, V

CTL

= 5 V, V

LIM

= 2.06 V,

830 900 970 mA

Hall input logic fixed (U, V, W = H, H, L)
[Hall Amplifier]
Hall amplifier input offset voltage

Voff (HALL) –6 +6 mV
Hall amplifier input bias current IB(HALL) 1.0 3.0 µA
Hall amplifier common-mode input voltage range

VCM(HALL) 1.3 3.3 V

For the high and low peaks in the Rf waveform

Torque ripple correction ratio TRC when I

O

= 200 mA. 9 %

(Rf = 0.5 Ω)

*1

[FG Amplifier]
FG amplifier input offset voltage Voff (FG) –8 +8 mV
FG amplifier input bias current I

B

(FG) –100 nA

FG amplifier output saturation voltage V

O

sat (FG)

Sink side, for the load provided by the internal

0.5 0.6 V

pull-up resistor

FG bias voltage V

FGBI

2.4 2.5 2.6 V

FG amplifier common-mode input voltage V

GM

(FG) 0.5 4.0 V

Continued from preceding page.

Notes : 1.The torque ripple correction ratio is determined as follows from the Rf voltage waveform.

2.Parameters that are indicated as design target values in the conditions column are not tested.

Truth Table and Control Functions

No. 5975-3/8

LB1999M

Correction ratio =

2 × (Vp– Vb)

100 × (%)

Vp– V

b

For each Hall logic setting

Ground level

Source → Sink

Hall input

FR

U V W

1

Phase V → Phase W

H H L

H

Phase W → Phase V L

2

Phase U → Phase W

H L L

H

Phase W → Phase U L

3

Phase U → Phase V

H L H

H

Phase V → Phase U L

4

Phase W → Phase V

L L H

H

Phase V → Phase W L

5

Phase W → Phase U

L H H

H

Phase U → Phase W L

6

Phase V → Phase U

L H L

H

Phase U → Phase V L

Note: In the FR column, “H” refers to a voltage of 2.75 V or higher, and “L” refers

to 2.25 V or lower (when V

CC

= 5 V.)

Note: In the Hall input column, “H” refers to the state in the corresponding phase

where the + input is at a potential at least 0.01 V higher than the – input,
and “L” refers to the state where the – input is at a potential at least 0.01 V
higher than the + input.

Note: Since the drive technique adopted is a 180° technique, phases

other than the sink and source phase do not turn off.

Parameter Symbol Conditions

Ratings

Unit

min typ max

[

Saturation

]

Saturation prevention circuit lower

The voltages between each OUT and

side voltage setting

VOsat (DET)

Rf pair when IO= 10 mA, Rf = 0.5 Ω, and 0.175 0.25 0.325 V
V

CTL

= V

LIM

= 5 V

[

Schmitt Amplifier

]

Duty ratio DUTY Under the specified conditions (R

F

= 39 kΩ) 48.7 50 51.3 %

Upper side output saturation voltage Vsatu (SH) I

O

= –20 µA 4.8 V

Lower side output saturation voltage Vsatd (SH) I

O

= 100 µA 0.2 V
Hysteresis width Vhys 32 46 60 mV
TSD operating temperature T-TSD Design target value

*2

170 °C