No. 5640-3/6
LA5621M, 5621V
Parameter Symbol Conditions
Ratings
Unit
min typ max
[FET drive block]
Drive high-level voltage V
GATE-H
Same as current drain 1-1 5.3 5.4 V
Drive low-level voltage V
GATE-L
SW6: on, Same as
current drain
1-2
0.1 0.2 V
[Comparator block] SW1, 2, 5, 6: on
Input offset voltage 1 V
IO
1
Comparator 1, when CPU voltage is reversed
–3 +2 +7 mV
Input offset voltage 2 V
IO
2
Comparator 2, when BIAS2 voltage is reversed
–3 –1 +1 mV
Input offset voltage 3 V
IO
3 Total temperature, comparator 2 –5 +3 mV
Input offset current I
IO
Comparators 1, 2 5 50 nA
Input bias current I
IB
Comparators 1, 2 –250 –25 nA
In-phase input voltage range V
ICR
Comparators 1, 2
VCC2 – 1.5
V
Input current during negative voltage application
I
LIM
Comparators 1, 2 non-reversed input block only, SW3: on
–1.5 mA
[Input pin block] V
IN
1–= 15 mV, VIN1+= 23 mV, VIN2–= 15 mV, VIN2+= 23 mV
CHARGE pin threshold voltage V
CHG-TH
SW1, 2, 5, 6: When on, BIAS2 voltages are reversed
0.5 1.2 V
CHARGE pin input bias current 1 I
CHG-BI
1 Current during threshold voltage 10 µA
CHARGE pin input bias current 2 I
CHG-BI
2V
CHARGE
= VCC2557085µA
CHARGE-INH pin open voltage V
CH-IN-OP
SW1, 2, 5, 6: on VCC2V
CHARGE-INH pin threshold voltage V
CH-IN-TH
SW1, 2, 5, 6: When on, BIAS2 voltages are reversed
0.7 1.3 V
CHARGE-INH pin low-level input current I
CH-IN
SW1, 2, 5, 6: on –30 µA
BATT/EXT pin open voltage V
BA/EX-OP
SW1, 2, 6: on VCC2V
BATT/EXT pin threshold voltage V
BA/EX-TH
SW1, 2, 6: When on, BIAS2 voltages are reversed
1.45 2.05 V
BATT/EXT pin low-level input current V
BA/EX
SW1, 2, 5, 6: on –30 µA
Continued from preceding page.
Handling Cautions
Observe precautions when handling these ICs because they are electrostatic sensitive devices.
Pin Assignment