SANYO LA3246 Datasheet
Ordering number: EN 2651B
Monolithic Linear IC
LA3246
Stereo Preamplifier for Compact Double Cassette
Playback-only Use
Overview
The LA3246 is a stereo preamplifier IC for double cassette
tape playback-only use. The LA3246 is intended for use in
portable radio-cassette tape recorders and tape decks.
Applications
.
Stereo compact cassette player for playback-only use
.
Stereo cassette deck player
Functions
.
Preamplifier × 2, Mixing amplifier × 1, Electronic switch × 6
Features
.
On-chip electronic switch for input select (auto reverse or
A deck/B deck select)
.
On-chip electronic switch for normal/higher dubbing select
and electronic switch for metal/normal tape select
.
Wide operating voltage range (VCCop = 3.5 to 14 V)
.
With output MIX pin (for music select control)
.
Low noise voltage range (VNI= 0.9 µV typ, Rg = 2.2 kΩ
NAB)
.
Can be used in conjunction with the LA3240, 3241, 3242 to
easily make up a doublecassette dubbing system.
Package Dimensions
unit : mm
3021B-DIP20
[LA3246]
SANYO : DIP20 (300 mil)
Specifications
Maximum Ratings at Ta = 25°C
Parameter Symbol Conditions Ratings Unit
Maximum supply voltage V
Allowable power dissipation Pd max 500 mW
Operating temperature Topr –20 to +75 °C
Storage temperature Tstg –40 to +125 °C
Maxiumum Ratings at Ta = 25°C
Parameter Symbol Conditions Ratings Unit
Recommended supply voltage V
Operating voltage range V
max 16 V
CC
CC
op 3.5 to14 V
CC
6V
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
D3097HA(II)/41594HK/N107TA, TS No.2651-1/13
LA3246
Operating Characteristics at Ta = 25°C, VCC= 6.0 V, RL=10kΩ,f=1kHz, 0 dB = 0.775 V
Parameter Symbol Conditions min typ max Unit
Quiescent current
Voltage gain (Open) VGo 75 85 dB
Voltage gain (Closed) VG Nor/Nor speed, NAB 39.5 40.5 41.5 dB
Total harmonic distortion THD V
Maximum output voltage V
Crosstalk (between channels) CT1 V
Crosstalk (between F/R) CT2 V
Channel balance V
Equivalent input noise voltage V
MIX output voltage V
Ripple filter output current I
Electronic switch ON-state
resistance
DC feedback resistance R
Input bias current I
Pd max – Ta
Icco Nor/Nor speed forward 5 7 12 mA
Iccs Metal/High speed forward 7 10 17 mA
= 0.65 V, Nor/Nor speed 0.03 0.2 %
max THD = 1%, Nor/Nor speed 0.7 1.2 V
O
BL
NI
MIX VO1, VO2 = 0 dBm –3 0 +3dB
O
F OUT
Ron
F
F
O
= –5 dBm, Rg = 2.2 kΩ, Nor/Nor speed 50 65 dB
O
= –5 dBm, Rg = 2.2 kΩ, Nor/Nor speed 50 65 dB
O
VIN= –50 dBm 0 2 dB
Rg = 2.2 kΩ, B.P.F 20 Hz to 20 kHz, Nor/Nor speed 0.9 1.7 µV
10 15 mA
Between P1 to P4 and 5, between pin 16 and 17 100 250 Ω
Between P1 to P7 and 10, between pin 10 and 14 30 70 Ω
240 300 360 Ω
0.5 3.0 µA
Allowable power dissipation, Pd max – mW
Ambient temperature, Ta – °C
Equivalent Circuit Block Diagram
Top view
No.2651-2/13
Test Circuit
LA3246
Sample Application Circuit
Unit (resistance: Ω, capacitance: F)
Note 1. The output frequency characteristic for Nor Tape/High speed mode (pin 6: High, pin 15: Low) and that for Metal
Tape/Nor speed mode (pin 6: Low, pin 15: Low) are set to be the same.
2. Since the input bias current flows out of pins 1, 2 and pins 19, 20, a resistor (recommended value: 30 kΩ to 350 kΩ,
maximum value: 500 kΩ) must be connected a coupling capacitor in series with these pins.
3. *: A capacitor must be connected to the input to absorb a surge.
4. The electronic select switching level is approximately 1/2 × (V
5. The value of the capacitor connected to pin 12 can be increased/decreased to adjust starting time t
application of V
worse.
6. No capacitor is connected to pin 13. (Even if connected, the ripple can not be rejected.)
7. Extreme caution should be exercised when handling the IC as it is subject to dielectric breakdown.
.(C=100µF,ts= 0.4 s.) If the capacitor value is made less than 47 µF, the ripple rejection will get
CC
CC
–0.9).
at the time of
s
No.2651-3/13
LA3246
Sample Printed Circuit Pattern (Cu-foiled area)
Unit (resistance: Ω, capacitance: F)
IC Usage Notes
(1) It is recommended to connect a surge absorbing capacitor across input pins 1, 2 and GND and across input pins 19, 20 and
GND.
(2) The base of a PNP transistor is connected to input pins 1, 2 and 19, 20. If an electrolytic capacitor is connected in series with
the input pins, connect input resistor R
at the time of input switching)
If a resistor of more than 500 kΩ is connected across input pin and GND, the noise (output) caused by amp 1 and amp 2 select is
liable to increase at the time of F/R switching.
must not exceed 500 kΩ. (Reason: To minimize the variation in output DC voltage
IN
Ω
No.2651-4/13
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