Show a clean procedure in the following in reference by swab of cotton.
1. Cotton swab is wrapped with Cleaning paper.
2. Add the isopropyl alcohol.
3. Gently move the tip of cotton swab just like a draw a whirlpool from inside to outside on the surface of lens.
- 1 -
Page 3
LASER BEAM SAFETY PRECAUTION
• Pick-up that emits a laser beam is used in this CD player section.
CAUTION :
THIS PRODUCT CONTAINS A LOW POWER LASER DEVICE,
TO ENSURE CONTINUED SAFETY DO NOT REMOVE ANY
COVERS OR ATTEMPT TO GAIN ACCESS TO THE INSIDE
OF THE PRODUCT.
REFER ALL SERVICING TO QUALIFIED PERSONNEL.
LASER OUTPUT ..............0.6 mW Max. (CW)
WAVELENGTH .................. 790 nm
CAUTION – INVISIBLE LASER RADIATION WHEN OPEN AND
INTERLOCKS DEFEATED. AVOID EXPOSURE TO BEAM.
ADVARSEL – USYNLIG LASER STRÅLING VED ÅBNING, NÅR
SIKKERHEDSAFBRYDERE ER UDE AF FUNKTION, UNDGÅ UDS ÆTTELSE
FOR STRÅLING.
VARNING – OSYNLIG LASER STRÅLNING NÄR DENNA DEL ÄR ÖPPNAD
OCH SPÄRR ÄR URKOPPLAD. STRÅLEN ÄR FARLIG.
VORSICHT – UNSICHTBARE LASERSTRAHLUNG TRITT AUS, WENN
DECKEL GEÖFFNET UND WENN SICHERHEITSVERRIEGELUNG
ÜBERBRÜCKT IST. NICHT, DEM STRAHL AUSSETZEN.
VARO – AVATTAESSA JA SUOJALUKITUS OHITETTAESSA OLET ALTTIINA
NÄKYMÄTTÖMÄLLE LASERSÄTEILYLLE. ÄLÄ KATSO SÄ
TEESEEN.
TAPE ADJUSTMENTS
a. Replacing the head
1. After replacement, demagnetize the heads by using
a degausser.
2. Be sure to clean the heads before attempting to make
any adjustments.
3. Be sure both channels (1 and 2) are the same level.
(Using a dual-channels oscilloscope).
4. All wiring should be returned to the original position
after work is completed.
R / P HEAD
RED
WHITE
YELLOWEARTH
c.Adjusting motor speed
1. Insert the test tape (MTT-111 or etc. 3,000 Hz).
2. Press the PLAY button.
3. Use a flat-tip screwdriver to turn the SVR to adjust so
that the frequency counter becomes 3,000 Hz.
4. Press the STOP button.
d.Replacing the moto
MOTOR SPEED
ADJUSTMENT
1
4
3
2
4
b. Adjusting head azimuth
1. Load a test tape (VTT-738, etc. :10kHz) for
azimuth adjustment.
2. Press the PLAY button.
3. Use a cross-tip screwdriver to turn the screw for
normal azimuth adjustment so that the left and right
outputs are maximized at the same phase during
normal playback.
4. Press the STOP button.
e. Checking the mechanism torques
• Clean the head, capstan and pinch roller before making
any measurement.
Connect Sweep generator to test
point TP13(L), TP14(R) and TP15(E).
Connect to VTVM603kHzL2204
point TP13(L), TP14(R) and TP15(E).
SG
Frequency
450kHz
at 999kHz
Adjustment
T2001
L2205
1404kHzCT211
Remark
MaximumLoop Ant
Maximum
- 3 -
Page 5
EXPLODED VIEW (CABINET & CHASSIS)
1
3
2
6
7
10
9
8
Y01
Y02
Y03
Y03
Y04
Y05
Y05
Y07
Y08
Y07
Y06
Y08
Y09
Y10
Y11
Y14
Y15
Y16
Y16
Y17
Y18
Y19
Y12
Y13
11
15
14
13
4
5
12
16
17
18
19
24
25
73
27
28
29
32
33
30
31
34
35
26
24
20
21
51
52
55
53
54
56
71
72
74
75
57
76
58
23
22
- 4 -
Page 6
PARTS LIST
PRODUCT SAFETY NOTICE
EACH PRECAUTION IN THIS MANUAL SHOULD BE FOLLOWED DURING SERVICING. COMPONENTS IDENTIFIED WITH THE
!!
IEC SYMBOL
PERFORMANCE CAN BE OF SPECIAL SIGNIFICANCE. WHEN REPLACING A COMPONENT IDENTIFIED BY
REPLACEMENT PARTS DESIGNATED, OR PARTS WITH THE SAME RATINGS OF RESISTANCE, WATTAGE OR VOLTAGE THAT
ARE DESIGNATED IN THE PARTS LIST IN THIS MANUAL. LEAKAGE-CURRENT OR RESISTANCE MEASUREMENTS MUST BE
MADE TO DETERMINE THAT EXPOSED PARTS ARE ACCEPTABLY INSULATED FROM THE SUPPLY CIRCUIT BEFORE
RETURNING THE PRODUCT TO THE CUSTOMER.
CAUTION :Regular type resistors and capacitors are not listed. To know those values, refer to the schematic diagram.
N.S.P :Not available as service parts.
!
IN THE PARTS LIST AND THE SCHEMATIC DIAGRAM DESIGNATED COMPONENTS IN WHICH SAFETY AND
!!
!
, USE ONLY THE
Regular type resistors are less than 1/4 W carbon type and 0 ohm chip resistors.
Regular type capacitors are less than 50 V and less than 1000 µF type of Ceramic type and Electrical type.
TM01645 033 8625 E HEAD 6PA
TM02645 041 3025 R.P HEAD
TM03645 009 1612 PINCH ROLLER ARM ASSY
TM04645 009 1766 RF BELT
TM05645 033 3415 MAIN BELT
TM06614 312 0629 ASSY,MOTOR,FOR SERVICE
IC601 IC LC72338-9B55 (Single-Chip PLL + Controller)
XIN
XOUT
FMIN
AMIN
SNS
VDD
VSS
HCTR
LCTR
HOLD
TEST1
TEST2
PA0
PA1
PA2
PA3
PB0
PB1
PB2
PB3
PC0
PC1
PC2
PC3
PG0
SCK0/PG1
SO0/PG2
SI0/PG3
1
REFERENCE DIVIDERDIVIDER
80
74
1 / 16,1 / 17
PROGRAMMABLE DIVIDER
SELECTER
PHASE
DETECTOR
UNLOCK
F/F
COMMON
DRIVER
75
72
73
76
70
71
V-DET
SNSFF
1 / 2
UNIVERSAL
COUNTER
(20bits)
LATCH
LCDA/B
4
LCPA/B
4
SEG
PLA
7
LCD
LATCH
96
PORT
DRIVER
69
79
2
18
17
16
15
14
13
12
11
10
9
8
7
BUS
DRIV.
LATCH
BUS
DRIV.
LATCH
BUS
DRIV.
SIO
512 x 4bits
ROM
8K x 16bits
ADDRESS DECODER
PROGRAM COUNTER
STACK
6
5
4
3
LATCH
BUS
DRIV.
RAM
ALU
ADDRESS
DECODER
BUS
DRIVER
INSTRUCTION
DECODER
JUDGE
DAC
BEEP
LATCH
BUS
DRIV.
LATCH
BUS
DRIV.
LATCH
BUS
DRIV.
LATCH
BUS
DRIV.
LATCH
BUS
DRIV.
LATCH
BUS
DRIV.
MPX
MPX
MPX
MPX
MPX
INTERRUPT
ADC
MPX
LATCH
BUS
DRIV.
77 E01
78
E02
58
COM1
57
COM2
56
COM3
Vdd1
60
59
Vdd2
S1
55
54
S2
53
S3
52
S4
S5
51
S6
50
S7
49
S8
48
S9
47
S10
46
S11
45
44
S12
43
S13
S14
42
41
S15
S16
40
39
S17/PE0
38
S18/PE1/SCK2
S19/PE2/SO2
37
36
S20/PE3/SI2
S21/PF0
35
34
S22/PF1/SCK1
33
S23/PF2/SO1
S24/PF3/SI1
32
30
S25/PM0
29
S26/PM1
28
S27/PM2
27
S28/PM3
26
S29/PN0/BEEP
25
S30/PN1
24
S31/PN2
23
S32/PN3
61
PJ3/DAC3
62
PJ2/DAC2
63
PJ1/DAC1
64
PJ0/DAC0
19
PK3
20
PK2
21
PK1/INT1
22
PK0/INT0
65
PH3/ADI3
66
PH2/ADI2
67
PH1/ADI1
68
PH0/ADI0
- 11 -
Page 13
IC BLOCK DIAGRAM & DESCRIPTION
IC601 IC LC72338-9B55 (Single-Chip PLL + Controller)
PIn name Pin No. I/O I/O FormatFunctions
Port only for key return signal input.
PA0
PA1
PA2
PA3
PB0
PB1
PB2
PB3
PC0
PC1
PC2
PC3
PG0
PG1/SCK0
PG2/SO0
PG3/SI0
XIN
XOUT1 80
EO1
EO2
VSS
VDD
FMIN
AMIN
HCTR
SNS
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4 3 I/O
78
77
76
31,73
74
75
70
72
I
O
I
O
O
-
I
I
I
I
Pull-down
resistor
input
Unbalance
CMOS
Push-pull
CMOS
posh-pull
The threshold voltage is set to a relatively low value.
When a key matrix is formed by combining PB and PC ports,
maximum three simultaneous key presses can be detected.
All of four pull-down resistor are set by the IOS instruction with
Pn=2, bl and specification of resistor for each pin is impossible.
The input is disabled in clock stop mode.
Port only for key source signal output.
Since the output transistor circuit is an unbalanced CMOS
structure, diodes to prevent short-circuiting due to multiple key
presses are not required.
In clock stop mode, these pins go to the output high-impedance
state and hold this state until an output instruction is executed.
General-purpose output/serial I/O ports. Schmidt type input
the IOS instruction performs switching between general-purpose
I/O ports and serial I/O ports, and between input and output for
general-purpose I/O ports.
• When used as general-purpose I/O ports these pins
can be set for input or output in bit units(bit I/O),
and are set for use as general-purpose I/O ports by
the IOS instruction with Pn=0.
b0=SI/O 0 0 • • • general-purpose port
1 • • • SI/O port
Specification of input or output is made by the IOS instruction
in bit units.
PG • • • Pn=6 0 • • • Input
1 • • • Output
• When used as serial I/O ports these pins are set for
serial I/O port use by the IOS instruction with Pn=0.
The content of serial I/O data buffer is saved or load by the
INR and OUTR instructions.
*Pin setup states when used as serial I/O ports
PG0 • • • general-purpose input or output
PG1 • • • SCK0 output in internal block
SCK0 input in external block
PG2 • • • SO0 output
PG3 • • • SI0 input
In clock stop mode, input is disabled and these pins go to
the high-impedance state.
During the power-on reset, these pins become general-purpose
input ports.
This pin is selected by the PLL instruction CW1 (b1=0,b0=don't
care). Capacitor coupling must be used for signalinput. Input is
disabled when the HOLD pin is set low inthe hold enable state.
Input is disable in clock stop mode,during the power-on reset,
and in the PLL stop state.
AMVCo (lcal oscillator) input pin.
This pin is selected and the band set by the PLL instruction
CW1 (b1,b0).
b1 b0 Band
1 0 2 to 40MHz (SW)
1 1 0.5 to 10MHz (MW,NW)
Capacitor coupling must be used for signal input.
Input is disabled when the HOLD pin is set low in the hold enable
state. Input is disabled in clock stop mode, during the power-on
reset, and in the PLL stop state.
Universal counter / general-purpose input port.
The IOS instruction b3 with Pn=3 switches the pin function
between universal counter input and general-purpose input.
• Frequency measurement
The universal counter function is selected by an IOS
instruction with Pn=3 and b2=0. HCTR frequency measure ment mode is set up by a UCS instruction with b3=0 and b2=0,
and counting is started with a UCC instruction after the count
time is selected. The CNTEND flag is set when the count
completes. To operate this circuit as an AC amplifier in this
mode, the input must be capacitor coupled.
• For use as the general-purpose input pin.
The general-porpose input port function is selected by an IOS
instruction with Pn=3 and b2=1. An internal register (address
OEH) input instruction INR(b0) is used to acquire data from
this pin.
Input is disabled in clock stop mede (the input pin will be pulled
down.) During the power-on reset, the universal counter function
is selected.
Voltage sense / general-purpose input pin port.
This circuit is designed for a relatively low input threshold voltage.
• For use as the voltage sense pin
This input pin is is used to determine whether or not a power
failure occurred after recovery from backup (clock stop) mode.
An internal sense F/F is used for this determination. The
sense F/F is tested with a TUL instruction (b2).
• For use as the general-purpose input port
When used as a genaral-purpose input port, the state is
sensed by using a TUL instruction (b3).
Since unlike other input ports, input is not disablle in clock
stop mode and during the power-on reset, special care is
required with respect to through currents.
PIn name Pin No. I/O I/O FormatFunctions
LCTR
71
I
HOLD
PH0/ADI0
PH1/ADI1
PH2/ADI2
PH3/ADI3
PJ0/DAC0
PJ1/DAC1
PJ2/DAC2
PJ3/DAC3
PK0/INT0
PK1/INT1
PK2
PK3
Vdd1
Vdd2
TEST1
TEST2
COM1
COM2
COM3
S1
|
S16
I
69
68
67
I
66
65
64
63
O
62
61
22
21
I/O
20
19
57
58
79
2
58
57
O
56
55
|
O
40
Universal counter (freqency and period measurement) / generalpurose input port.
This IOS instruction b3 with Pn=3 swithes the pin function
between universal counter input and general-puropse input.
• Frequency measurement
The universal counter function is selected by an IOS
instruction with Pn=3 and b3=0. LCTR frequency measure ment mode is set up by a UCS instruction with b3=0 and b2=1,
and counting is started with a UCC instruction after the count
time is selected. The CNTEND flag is set when the count
completes. To operate this circuit as an AC amplifier in this
mode, the input must be capacitor coupled.
• Period measurement
With the universal counter function selected, a UCS instruction
with b3=1 and b2=0 sets up the period measurement mode
and a UCC instruction starts counting after selecting the
count time. The CNTEND flag is set when the count
completes. In this mode, the signal must be input with DC
coupling to turn off the bias feedback resistor.
• For use as general-purpose input pin use.
The general-purpose input port function is selected by an IOS
instruction with Pn=3 and b3=1. An internal register (address
OEH) input instruction INR(b1) is used to acquire data from
this pin. Input is disabled in clock stop mode. (The input pin
will be pulled down.) During the power-on reset. The universal
counter function(in HCTR frequency measurement mode) is
selected.
PLLcontrol and CLOCK STOP mode control pin.
Setting this pin low in the hold enable state disables input to the
FMIN and AMIN pins and sets the E0 pin to the high-impedance
state. To enter clocl stop mode, set the HOLDEN flag, set this pin
low, and execute a CKSTP instruction. To clear clock stop mode
set this pin high.
General-purpose input ports/ADC input pins.
The IOS instruction with Pn=7 switches the pin function between
genetal-purpose input ports and ADC inputs.
• For use as the general-purpose input port
The IOS instruction with Pn=7 specifies the use as general purpose input port in bit units.
• For use as ADC input pin
The IOS instruction with Pn=7 specifies the use as ADC in bit
units. The IOS instruction with Pn=1 specifies the pin to
convert. The UCC instruction (b2) starts a conversion.
The ADCE flag will be set when the conversion completes.
Note) Executing an input instruction for a port specified for ADI
use will always return low since input is disabled. These
pins must be set up for general-purpose input port usage
before an input instruction is excuted. (In other words, the
port must be set to the general-porpose input function
before the input instruction is executed.)
Input is disabled in clock stop mode. During the power-on reset
these pins go to the general-purpose input port function.
General-purpose output ports/DAC input pin.
The IOS instruction with Pn=9 switches the pin function between
general-purpose output ports and ADC inputs. Since these pins
are open drain circuit, pull-up resistors are required in exrernal
circuit accepting these outputs.
• For use as general-purpose output port
The IOS instruction with Pn=9F specifies general-purrpose
input port use in bit units.
Nch
• For use as DAC
open drain
The IOS instruction Pn=9 is used to switch the port in bit units.
DAC data is loaded into tne DAC (0 to 3) specified with the
DAC instruction, Although PWM waveform is output as soon
as the port is switched, the data prior to that load is output for
up to 114µs (1/8.791kHz) after data is loaded.
The general-purpose output port function is selected after a power
-on reset, and the output go to the transistor off (H output) state.
General-purpose I/O / external interrupt ports
There is no instruction that switches the function between generalpurpose ports and external interrupt ports. These pins function for
input only when the external interrupt enable flag is set.
(Output disables)
• For use as general-purpose I/O port
These pins can be set for input or output in bit units (bit I/O).
The IOS instruction is used to specify input or output in bit
units.
CMOS
• For use as external interrupt pin
push-pull
This function can be used by setting the external interrupt
enable flags (INT0EN and INT1EN) in status register 2.
The corresponding pin is automatically set to the input port.
To enable interrupt operation, the interrupt enable flag (INTEN)
in status register 1 must also be set. The IOS instruction with
Pn=3, b1=INT1, and b0=INT0 is used to select rising or falling
edge detection.
In clock stop mode, input is disabled and these pins go to the highimpedance state. During the power-on reset, these pins go to the
general-purpose input port function.
Pin for external application of 2/3 voltage of LCD drive bias.
Pin for external application of 1/3 voltage of LCD drive bias.
LSI test pin.
These pins must be either left open or connected to ground.
CMOS
LCD driver common output pin.
three
Driver format 1/3 duty, 1/3 bias.
value
This pin is fixed at the low level in CLOCK STOP mode.
output
This pin is fixed at the low level after a power-on reset.
LCD driver common output pin.
CMOS
Driver format 1/3 duty, 1/3 bias.
three
The frame frequency 100MHz.
value
This pin is fixed at the low level in CLOCK STOP mode.
output
This pin is fixed at the low level after a power-on reset.
- 12 -
Page 14
IC BLOCK DIAGRAM & DESCRIPTION
IC601 IC LC72338-9B55 (Single-Chip PLL + Controller)
PIn name Pin No. I/O I/O FormatFunctions
S17/PE0
S18/PE1/SCK2
S19/PE2/SO2
S20/PE3/SI2
S25/PM0
S26/PM1
S27/PM2
S28/PM3
39
38
I/O
37
36
30
29
I/O
28
27
LCD driver segment output, general-porpose input/output and
serial I/O ports
The IOS instruction is used to switch between the LCD driver
segment output, general-purpose I/O, and serial I/O functions,
and to switch between input and output of the general-purpose
input port function.
• For use as segment output
These pins can be set in bit units.
The IOS instruction with Pn=ODH specifies segment output
use in bit units.
b0=S17/PE0 0 • • • Segment output
b1=S18/PE1 1 • • • PE0 to 3 output
b2=S19/PE2
b3=S20/PE3
• For use as general-purpose input /output port
These pins can be set for input /output in bit units.
(1 bit I/O)
b2=SI/O2 0 • • • Genetal-purpose port
CMOS
1 • • • SI/O port
three
Input /output is specified with the IOS instruction in bit units.
value
PE • • • Pn=4 0 • • • Input
output
1 • • • Output
and
• For serial I/O port
push-pull
The serial I/O port function is specified with the IOS instruction
(Pn=0).
The contents of the serial I/O data buffer can be saved and
loaded with the INR and OUTR instructions.
*Pin setup states when used as a serial I/O port
PE0 • • • General-purpose input /output
PE1 • • • SCK2 output in internal clock mode
SCK2 output in external clock mode
PE2 • • • SO2 output
PE3 • • • SI2 input
In CLOCK STOP mode, if this port is used as a general-purpose
I/O port or as a serial I/O port, the pins go to the input disabled
high-impedance state. If used for segment output, the pins fixed at
the low level. The segment output port function is selected after a
power-on reset.
LCD driver segment output, general-porpose input /output ports.
The IOS instruction is used to switch between the LCD driver
segment output, general-purpose I/O port, and serial I/O to switch
between input and output of the general-purpose input /output
port function.
• For use as segment output
These pins can be set in 4 bits units. The IOS instruction with
CMOS
Pn=OEH specifies segment output use in bit units.
three
b0=S25 to 28/PM0 to 3 0 • • • Segment output
value
1 • • • PM0 to 3
output
• For use as general-purpose input /output port
and
These pins can be set for input /output in bit units.
push-pull
Input /output is specified with the IOS instruction in bit units.
PM • • • Pn=OCH 0 • • • Input
1 • • • Output
In CLOCK STOP mode, if this port is used as a general-purpose
I/O port, the pins go to the input disabled high-impedance state. If
used for segment output, the pins are fixed at the low level. The
segment output port function is selected after a power-on reset.
PIn name Pin No. I/O I/O FormatFunctions
S21/PF0
S22/PF1/SCK1
S23/PF2/SO1
S24/PF3/SI1
S29/PN0/BEEP
S30/PN1
S31/PN2
S32/PN3
35
34
I/O
33
32
26
25
O
24
23
LCD driver segment output, general-porpose input/output and
serial I/O ports.
The PF0 to 3 inputs are in the Schmidt format.
The IOS instruction is used to switch between the LCD driver
segment output, general-purpose I/O, and serial I/O functions, and
to switch between input and output of the general-purpose input
port function.
• For use as segment output
These pins can be set in 4 bits units. The IOS instruction with
Pn=OEH specifies segment output use in bit units.
b0=S21 to 24/ PF0 to 3 0 • • • Segment output
1 • • • PE0 to 3
• For use as general-purpose input /output port
These pins can be set to input /output in bit units. (1 bit I/O)
CMOS
b1=SI/O 1 0 • • • Genetal-purpose port
three
1 • • • SI/O port
value
Input /output is specified with the IOS instruction in bit units.
output
PF • • • Pn=5 0 • • • Input
and
1 • • • Output
push-pull
• For use as serial I/O port
The serial I/O port function is specified with the IOS instruction
(Pn=0). The contents of the serial I/O data buffer can be saved
and loaded with the INR and OUTR instructions.
*Pin setup states when used as a serial I/O port
PF0 • • • General-purpose input /output
PF1 • • • SCK1 output in internal clock mode
SCK1 output in external clock mode
PF2 • • • SO1 output
PF3 • • • SI1 input
In CLOCK STOP mode, if this port is used as a general-purpose
I/O port or as a serial I/O port, the pins go to the input disabled
high-impedance state. If used for segment output, the pins are
fixed at the low level. The segment output port function is selected
after a power-on reset.
Segment output/general-porpose input port 1/ BEEP tone output
pins. The IOS instruction is used to switch between the segment
output port and the PN0 to 3 functions. The BEEP instruction
switches between the general-purpose output port and BEEP tone
function.
• For use as segment output
These pins can be set in 3 bits units. The IOS instruction with
Pn=OEH specifies segment output use in bit units.
b2=S29 to 32/ PN0 to 3 0 • • • Segment output
1 • • • PN0 to 3
CMOS
• For use as general-purpose output.
three
The general-porpose output port function is selected with the
value
BEEP instruction (b3=0).
output
PN1 to 3 are dedicated general-purpose output function pins.
and
• For use as BEEP output pin
push-pull
The BEEP instruction with b3=1 sets the BEEP output.
The BEEP instruction bit b0,b1 and b2 sets the frequency.
When this is set as the BEEP port, executing an output
instruction will rewrite the inter nal latch data but has no
influence on the output.
These pins go to the output high-impedance state in clock stop
mode. If used for segment output, the pins are fixed at the low level.
These pins go to the output high-impedance state during the
power-on reset and hold that state until an output instruction is
executed.
Each precaution in this manual should be followed during servicing. Components identified with the IEC symbol
diagram designated components in which safety and performance can be of special significance. When replacing a component identified by
the replacement parts designated, or parts with the same ratings of resistance, wattage or voltage that are designated in the parts list in this manual. Leakagecurrent or resistance measurements must be made to determine that exposed parts are acceptably insulated from the supply circuit before returning the product
to the customer.
and mark in the parts list and the schematic
!!
!
!!
!
and , use only
- 27 -- 26 -
Page 23
1
15
162030
11015
GND
CD-+B
CD-LCH
A-GND
CD-RCH
TU-LCH
TU-RCH
GND
E
RCLG
E
E
E
E
E
EE
E
E
T2.5A L250V
1AD4B10D1710A
T002 94V-0
E
E
E
E
E
E
E
E
E
DIP
DIP
R4941
C4832
C4833
C4831
C4801
C4701
C4731
C4732
C4733
IC412
C4913
CN490
CN406
CN405
FU401
D4983
D4981
D4982
D4980
J4204
C4953
C4815
C4715
C4814
C4816
C4716
L4881
IC411
PR496
D4951
R4951
R4952
C4951
R4852
C4714
R4752
C4912
C4911
C4713
C4813
Q4851
J4307
L4902
C4918
C4811
C4711
C4804
C4704
C4909
J4213
Q4902
C4921
J4126
J4123
Q4904
C4905
J4321
J4230
J4308
J4313
C4851
C4751
Q4751
D4961
C4961
C4726
C4826
J4211
Q4830
Q4730
J4314
J4117
J4207
J4208
J4209
D4963
J4310
J4320
J4214
J4217
Q4103
Q4903
D4102
J4228
J4115
Q4104
D4962
Q4106
J4119
J4319
L4781
J4224
CN402
CN401
J4205
J4200
J4234
J4236
J4114
CN421
C4901
J4222
J4231
J4229
J4233
J4125
CN441
J4100
IC410
R
L
S4950
Q4951
J4202
J4203
AC_SENS
GND
5.6V
BASS BOOST
A_MUTE
VOL_CK
VOL_DATE
VOL_STB
TAPE_PLAY
SURROUND
J4121
J4312
D4953
J4225
J4220
J4221
J4317
J4212
J4216
J4113
C4963
C4962
J4112
1250
1500
LG401
C4823
C4723
Q4740
Q4840
J4110
J4237
J4122
BEAT
J4206
C4730
J4111
C4837
J4306
J4215
J4109
J4210
J4108
J4219
J4116
J4120
J4223
C4110
Q4108
Q4109
J4232
J4127
J4128
J4124
J4309
Q4994
J4139
Q4992
CN431
CN480
CN215
CN216
ST/BY
AUX_MUTE
C4915
J4107
J4316
J4311
J4118
J4201
PR495
1AD4B10D1710A
J4106
J4315
J4227
J4318
J4218
J4226
J4235
J4323
J4324
J4325
J4132
J4322
J4300
J4140
J4141
J4239
REC
J4101
GND
C4994
IC446
D4993
C4993
J4138
J4129
J4301
J4302
Q4995
J4105
J4133
J4137
J4326
CN491
J4131
J4238
J4134
J4130
J4135
R4734
R4838
R4837
C4834
C4743
C4843
R4848
R4748
R4851
R4751
R4836
R4749
R4849
R4750
R4850
R4840
R4839
R4842
R4841
C4838
C4842
C4840
C4841
R4845
C4839
C4835
C4836
R4846
R4847
R4835
R4834
R4833
R4741
R4742
R4739
R4740
R4737
R4738
R4736
C4740
C4742
C4739
C4738
C4735
C4734
C4736R4745
R4735
R4733
R4746
R4747
C4741
C4981
C4982
C4983
C4980
C4952C4952C4952
R4718
R4818
R4832
R4732
R4731
R4730
R4831
R4830
R4948
R4905
C4803
C4707
R4705
C4705
R4805
C4805
R4810
R4804
R4803
C4802
C4706
C4806
R4710
C4703
R4704
C4702
R4703
R4912
R4910
C4919
R4911
C4920
C4916
R4914
C4906
C4708
R4708
C4709
R4709
R4809
C4809
R4808
C4808
C4712
C4812
R4816
R4716
R4756
R4961
R4961R4961
R4856
R4853
R4717
R4817
R4870
R4753
R4861
R4761
R4107
R4962R4962R4962
R4781
R4901
R4938
R4971
R4770
C4744
C4844
R4843
R4991
R4857
R4758
R4858
R4757
R4859
R4759
R4860
R4881
R4110
R4109
R4108
C4750
C4850
R4760
C4753
C4752
C4853
C4852
C4997
R4105
R4104
R4949
C4984
R4743
C4807
R4955
R4953
R4954
R4106
WIRING DIAGRAM (AMPLIFIER)
This is a basic wiring diagram.
- 29 -- 28 -
Page 24
WIRING DIAGRAM (POWER TRANSFORMER & LED)
POWER TRANSFORMER P.W. BOARD
NIP CUT
CN451
BL
BL
BW
BW
CN452
L4591
NIP CUT
T4981
LED P.W.BOARD
RE
BK
CN450
T002 94V-0
1AD4B10D1710E
1AD4B10D1710E
1AD4B10D1710F
1AD4B10D1710F
TOO2 94V-0
D6955
This is a basic wiring diagram.
D6954
D6953
R6952
R6951
D6952
D6951
+BGND
R6953
R6954
Feb. / '03BB Printed in Japan
SANYO Electric Co., Ltd.
Osaka, Japan
- 31 -- 30 -
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