Off-Line PWM Controllers with Integrated Power MOSFET
STR-A6000 Series Data Sheet
General Descriptions
The STR-A6000 series are power ICs for switching
power supplies, incorporating a MOSFET and a current
Package
DIP8
mode PWM controller IC.
The low standby power is accomplished by the
automatic switching between the PWM operation in
normal operation and the burst-oscillation under light
load conditions. The product achieves high
cost-performance power supply systems with few
external components.
Not to Scale
Lineup
Features
• Current Mode Type PWM Control
• Brown-In and Brown-Out function
• Auto Standby Function
No Load Power Consumption < 25mW
• Operation Mode
Normal Operation ----------------------------- PWM Mode
STR-A605×M 650 V
STR-A607×M 800 V
STR-A605×H 650 V
STR-A606×H 700 V
STR-A606×HD 700 V 100 kHz
*STR-A60××HD has two types OCP
• MOSFET ON Resistance and Output Power, P
OUT
R
Products
STR-A6051M 3.95 Ω 18.5 W 14 W 31 W 21 W
STR-A6052M 2.8 Ω22 W 17.5W 35 W 24.5 W
STR-A6053M 1.9 Ω26 W 21W 40 W 28 W
STR-A6079M 19.2 Ω8 W 6 W 13 W 9 W
STR-A6059H
STR-A6069HD
STR-A6061H
STR-A6061HD
STR-A6062H
STR-A6062HD
STR-A6063HD 2.3 Ω25 W 20 W 40 W 28 W
* The output power is actual continues power that is measured at
50 °C ambient. The peak output power can be 120 to 140 % of the
value stat ed here. Core size, ON Duty, and thermal design affect
the output power. It may be less than the value stated here.
10.2 PCB Trace Layout and Component Placement --------------------------------------- 22
11. Pattern Layout Example ----------------------------------------------------------------------------- 24
12. Reference Design of Power Supply ----------------------------------------------------------------- 25
Important Notes ---------------------------------------------------------------------------------------------- 27
Current polarities are defined as follo ws: current going into the IC (sinking) is po sitive current (+) ; and current coming
out of the IC (sourcing) is negative current (−).
Unless otherwise specified, T
Parameter
= 25 °C, 7 pin = 8 pin.
A
Symbol Test Conditions Pins Rating Units Remarks
1.2
1.8
Drain Peak Current
(1)
I
Single pulse 8 – 1
DPEAK
2.5
A
3.0
4.0
I
Avalanche Energy
S/OCP Pin Voltage
(2)(3)
=1.2A
LPEAK
I
=1.8A
LPEAK
I
=2A
LPEAK
I
=2A
LPEAK
I
LPEAK
I
LPEAK
I
LPEAK
I
LPEAK
=2.2A
=2.3A
=2.5A
=2.7A
8 – 1
1 − 3 −2 to 6 V
V
EAS
S/OCP
7
24
46
47
56
62
72
86
mJ
BR Pin Voltage VBR 2 − 3 −0.3 to 7 V
BR Pin Sink Curr ent IBR 2 − 3 1.0 mA
The following drawings show circuits enabled and disabled the Brown-In/Brown-Out f unct i o n.
The PCB traces D/ST pins should be as wide as possible, in order to enhance thermal dissipation.
In applications having a power supply specified such that D/ST pin has large transient surge voltages, a clamp
snubber circuit of a capacitor-resistor-diode (CRD) combination should be added on the primary winding P, or a
damper snubber circuit of a capacitor (C) or a resistor-capacitor (RC) combination should be added between the D/ST
pin and the S/OCP pin.
Figure 6-1. Typical Application Circuit (enabled Brown-In/Brown-Out function, DC line detection)
Lot Numbe r:
Y is the last digi t of the year of manufactu re (0 to 9)
M is the m onth of the ye a r (1 to 9, O, N, or D)
D is a period of da ys:
1: the first 10 days of the month (1st to 10th)
2: the second 10 days of the month (11th to 20th)
3: the last 10–11 days of the m onth (21st to 31st)
1
8
A 6 0 × × H
S K Y M D D
STR-A60××HD
Part Nu mber
Control Number
Lot Numbe r:
Y is the last digi t of the year of manufactu re (0 to 9)
M is the m onth of the ye a r (1 to 9, O, N, or D)
D is a period of da ys:
1: the first 10 days of the month (1st to 10th)
2: the second 10 days of the month (11th to 20th)
3: the last 10–11 days of the m onth (21st to 31st)
7. Package Outline
• DIP8 (The following show a representative type of DIP8.)
All of the parameter values used in these descriptions
are typical values, unless they are specified as minimum
or maximum.
Current polarities are defined as follows: current
going into the IC (sinking) is positive current (+); and
current coming out of the IC (sourcing) is negative
current (−).
9.1 Startup Operation
Figure 9-1 shows the circuit around IC. Figure 9-2
shows the start up operation.
The IC incorporates the startup circuit. T he circuit is
connected to D/ST pin. When D/ST pin voltage reaches
to Startup Circuit Operatio n Voltage V
startup circuit starts operation.
During the startup process, the constant current,
I
VCC pin voltage increases to V
= − 2.5 mA, charges C2 at VCC pin. When
STARTUP
CC(ON)
control circuit starts operation.
During the IC operation, the voltage rectified the
auxiliary wi nding voltage , V
, of Figure 9-1 becomes a
D
power source to the VCC pin. After switching ope ration
begins, the startup circuit turn s off automatically so that
its current consumption becomes zero.
The approxi mate val ue of a uxili ar y windin g volt age i s
about 15 V to 20 V, taking ac count of t he wind ing t urns
of D winding so that VCC pin voltage becomes
Equation (1) within the spec ifica tion of i nput a nd out put
voltage variation of power supply.
= 38 V, the
ST(ON)
= 15.3 V, the
With Brown-I n / Brown-Out function
When BR pin vo ltage is mor e than V
and less than V
= 5.6 V, the Bias Assist Functio n
BR(IN)
BR(DIS)
= 0.48 V
(refer to Section 9.3) is disabled. Thus, VCC pin
voltage repeats increasing to V
V
becomes V
( shown in Figure 9-3). When BR pi n voltage
CC(OFF)
or more, the IC starts switching
BR(IN)
and decreasing to
CC(ON)
operation.
Figure 9-1. VCC Pin Peripheral Circuit
(Without Brown-In / Brown-Out)
(1)
⇒10.5 (V)
26 (V)
Figure 9-2. Startup Operation
The oscillation start timing of IC depends on
(Without Brown-In / Brown-Out)
Brown-In / Brown-Out function (refer to Section 9.8).
Without Brown-In / Brown-Out function (BR pin
voltage is V
When VCC pin voltage increases to V
= 0.48 V or less)
BR(DIS)
CC(ON)
, the IC
starts switching operation, As shown in Figure 9-2.
The startup time of IC is determined by C2 capacitor
value. The approximate startup time t
START
(shown i n
Figure 9-2) is calcula te d as follows:
(2)
where,
t
V
START
CC(INT)
: Startup time of IC (s)
: Initial voltage on VCC pin (V)
Figure 9-4 shows the rela tionship of VCC pin voltage
and circuit current I
to V
= 8.1 V, the control circuit stops operation by
CC(OFF)
. When VCC pin voltage decreases
CC
UVLO (Undervoltage Lockout) circuit, and reverts to
the state before startup.
Figure 9-4. Relationship between
VCC Pin Volta ge and I
CC
9.3 Bias Assist Function
Figure 9-5 shows VCC pin voltage behavior during
the startup period.
After VCC pin voltage increases to V
at startup, the IC starts the operation. Then circuit
current increases and VCC pin voltage decreases. At the
same time, the a u xili ary winding vol ta ge V
proportion to output voltage. These are all balanced to
produce VCC pin voltage.
= 15.3 V
CC(ON)
increase s i n
D
pin voltage decreases to the startup current threshold
biasing voltage, V
= 9.5 V. While the Bias Assist
CC(BIAS)
function is activated, any decrease of the VCC pin
voltage is counteracted by providing the startup current,
I
, from the startup circuit. Thus, the VCC pin
STARTUP
voltage is kept almost constan t.
By the Bias Assist function, the value of C2 is
allowed to be small and the startup ti me beco mes shorter.
Also, because the increase of VCC pin voltage becomes
faster when the output runs with excess voltage, the
response time of the OVP function becomes shorter.
It is necessary to check and adjust the startup process
based on actual operation in the application, so that poor
starting conditions may be avoid e d.
9.4 Constant Output Voltage Control
The IC achieves the constant voltage control of the
power suppl y output by usin g the current-mode control
method, which enhances the response speed and
provides the stable operation.
The FB/OLP pin voltage is internally added the slo pe
compensation at the feedback control (refer to Section 4
Functional Block Dia gram), a nd the tar get volta ge, V
is generated. The IC compares the voltage, V
ROCP
current detection resistor with the target volta ge, V
the internal FB comparator, and controls the peak value
of V
so that it gets close to VSC, as sho wn in Figure
ROCP
9-6 and Figure 9-7.
SC
, of a
, by
SC
,
Figure 9-6. FB/OLP Pin Peripheral Circuit
Figure 9-5. VCC Pin Voltage during Startup Period
The surge voltage is induced at output winding at
turning off a power MOSFET. When the output load is
light at startup, the surge voltage causes the unexpected
feedback control. This results the lowering of the output
power and VC C pi n vol ta ge. When t he V CC p in vo lta ge
decreases to V
operation and a startup failure occurs. In order to prevent
this, the Bias Assi st function i s activate d when the VCC
from the error amplifier on the secondary-side also
increases. The feedback current is sunk at the FB/OLP
pin, transferred through a photo-coupler, PC1, and the
FB/OLP pin voltage decreases. Thus, V
and the peak value of V
and the peak drain current of I
is contro lled to be low,
ROCP
decreases.
D
decreases,
SC
This control prevents the output voltage from
increasing.
• Heavy load conditions
When load conditions become greater, the IC
performs the inverse operation to that described above.
Thus, V
increases and the peak drain current of ID
SC
increases.
This control prevents the output voltage from
decreasing.
In the current mode control method, when the drain
current waveform becomes trapezoidal in continuous
operating mode, even if the peak current level set by the
target voltage is constant, the on-time fluctuates based
on the initial value of the drain current.
This result s in the on-time fluctua ting in multiples of
the funda mental op erat ing fr eque ncy as shown i n Figure
9-8. This is called the subharmonics phenomenon.
In order to avoid this, the IC incorporates the Slope
Compensation function. Because the target voltage is
added a down-slope compensation signal, which reduces
the peak drain current as the on-duty gets wider relative
to the FB/OLP pin signal to compensate V
, the
SC
subharmonics phenomenon is suppressed.
Even if subharmonic oscillations occur when the IC
has some excess supply being out of feedback control,
such as during startup and load shorted, this does not
affect performance of normal operation.
for the constant voltage control of o utput.
In peak-current-mode control method, there is a case
that the power MOSFET turns off due to unexpected
response of FB comparator or overcurrent protection
circuit (OCP) to the steep s urge current in tur ning on a
power MOSFET.
In order to p revent this response to the surge voltag e
in turning-on the power MOSFET, the Leading Edge
Blanking, t
and STR-A60××HD for 280 ns) is built-in. During t
(STR-A60××H for 340 ns, STR-A60××H
BW
BW
,
the OCP thre shold voltage be comes about 1.7 V whic h
is higher than the normal OCP threshold voltage (refer
to Section 9.9).
9.6 Random Switching Function
The IC modulates its switching frequency randomly
by superp osing the mod ulati ng freq uenc y on f
OSC(AVG)
in
normal operation. This function reduces the conduction
noise compared to others without this function, and
simplifies noise filtering of the input lines of power
supply.
9.7 Automatic Standby Mode Function
Automatic standby mode is activated automatically
when the drain current, I
conditions, at which I
maximum drain current (it is in the OCP state). The
operation mode becomes burst oscillation, as shown in
Figure 9-9. Burst oscillation mode reduces switching
losses and improves power supply efficiency because of
periodic non-switching intervals.
, reduces under light load
D
i s less tha n 15 % to 20 % of the
D
Figure 9-9. Auto Standby Mode Timing
Figure 9-8. Drain Current, I
in Subharmonic Oscillation
, Waveform
D
Generally, to improve efficiency under light load
conditions, the frequenc y of the burst oscillation mode
becomes just a few kilohertz. Because the IC suppresses
the peak dra i n c ur r ent well during b urs t oscillation mode,
audible noises can be reduced.
9.5 Leading Edge Blanking Function
The IC uses the peak-current-mode control method
If the VCC pin voltage decreases to V
during the transition to the burst oscillation mode, the
Bias Assist function is activated and stabilizes the
is provided to
the VCC pin so that the VCC pin voltage does not
decrease to V
CC(OFF)
.
However, if the Bias Assist function is always
activated during steady-state operation including
standby mode, the power loss increases. Therefore, the
VCC pin voltage should be more than V
CC(BIAS)
, for
example, by adjusting the turns ratio of the auxiliary
winding and secondary winding and/or reducing the
value of R2 in Figure 10-2 (refer to Section 10.1
Peripheral Components for a detail of R2).
9.8 Brown-In and Brown-Out Function
This function stops switching operation when it
detects low input line voltage, and thus prevents
excessive input current and overheating.
This function turns on and off switching operation
according t o the BR pin vol tage detectin g the AC input
voltage. When BR pin voltage becomes more than
V
and the drai n currnet.
pin voltage is V
voltage decreases from steady-state and the BR pin
voltage falls to V
Delay Time, t
operation. When the AC input vo ltage incr eases and the
BR pin voltage reaches V
operating state that the VCC pin voltage is V
more, the IC starts switching ope ration.
unnecessary, connect the BR pin trace to the GND pin
trace so that the BR pin voltage is V
= 0.48 V, this function is activated.
BR(DIS)
Figure 9-10 sho ws waveforms of t he BR pin voltage
Even if the IC is in the operating state that the VCC
or more, when the AC input
CC(OFF)
= 4.8 V or less for the OLP
BR(OUT)
= 68 ms, the IC stops switching
OLP
= 5.6 V or more in the
BR(IN)
CC(OFF)
or
In case the Brown-In and Brown-Out function is
or less.
BR(DIS)
becomes t
= 68 ms or more, the IC stops switching
OLP
operation.
● STR-A60××HD:
When the BR pin voltage falls to V
less for t
= 68 ms, the IC stops switching operation.
OLP
BR(OUT)
= 4.8 V or
There are two types of detection method as follows:
9.8.1 DC Line Detection
Figure 9-11 shows BR pin peripheral circuit of DC
line detection. There is a ripple voltage o n C1 occurring
at a half period of AC cycle. In order to detect each peak
of the ripple voltage, the time constant of R
should be shorter than a half period of AC cycle.
Since the cycle of the ripple voltage is shorter than
, the switching operation does not s top when only the
t
OLP
bottom part of the ripple voltage becomes lower than
BR(OUT)
.
V
Thus it minimizes the influence of load conditions on
the voltage detection.
Figure 9-11. DC Line Detection
The components around BR pin:
and C4
C
・ R
and RB are a few megohms. Because of high
A
voltage applied and high resistance, it is
recommended to select a resistor designed against
electromigration or use a combination of resistors
in series for that to reduce each applied voltage,
according t o the requirement of the application.
is a few hundred kilohms
・ R
Figure 9-10. BR Pin Voltage and Drain Current
Waveforms
C
・ C4 is 470 pF to 2200 pF for high frequency noise
reduction
Neglecting the effect of both input resistance and
During burst oscillation mode, this funct ion operates
as follows:
● STR-A60××M and STR-A60××H:
This function is disabled during switching operation
stop period in burst oscillation mode. When the BR
pin voltage falls to V
or less in burs t oscillation
BR(OUT)
forward voltage of rectifier diode, the reference value of
C1 voltage when Brown-In and Bro wn-Out function is
activated is calculated as follows:
Brown-In Threshold V oltage V
Brown-Out Threshold Voltage V
V
can be expressed as the effective value of AC
DC(OP)
BR(IN)
BR(OUT)
5.6 V
4.8 V
input voltage us in g Eq uat ion (4).
R
, RB, RC and C4 should be selected based on actual
A
(4)
operation in the application.
9.8.2 AC Line Detection
Figure 9-12 shows BR pin peripheral circuit of AC
line detection. In order to detec t the AC input voltage ,
the time constant of R
period of AC cycle. Thus the response of BR pin
detection becomes slow compared with the DC line
detection.
This method detects the AC input voltage, and thus it
minimizes the influence from load conditions. Also, this
method is free of influence from C1 charging and
discharging time, the latch mode can be released
quickly*
and C4 should be longer than the
C
* High-Speed Latch Release
When Overvoltage Protection function (OVP) or
Thermal Shutdown function (TSD) are activated,
the IC stops switching operation in latch mode.
Releasing the latch mode is done by decreasing the
VCC pin voltage below V
the BR pin voltage below V
or by decreasing
CC(OFF)
.
BR(OUT)
In case of the DC line detection or without
Brown-in / Brown-Out function, the release time
depends on discharge time of C1 and takes longer
time until VCC pin voltage decreases to release
voltage.
In case of the AC line detection, BR pin voltage is
decreased quickly when AC input volt age, V
AC
, is
turned off, and thus the latch mode is quickly
released.
The components around BR pin:
・ R
and RB are a few megohms. Because of high
A
voltage applied and high resistance, it is
recommended to select a resistor designed against
electromigration or use a combination of resistors
in series for that to reduce each applied voltage,
according t o the requirement of the application.
is a few hundred kilohms
・ R
C
・ R
must be adjusted so that the BR pin voltage is
S
more than V
voltage is V
CC(OFF)
= 0.48 V when the VCC pin
BR(DIS)
= 8.1 V
・ C4 is 0.22 μF to 1 μF for averaging AC input
voltage and high frequenc y no ise red uct io n.
Neglecting the effect of input resistance is zero, the
reference effective value of AC input voltage when
Brown-In and Brown-Out function is activated is
calculated as follows:
(5)
where,
V
AC(OP)RMS
:The effective value of AC input voltage
when Brown-In a nd B ro wn-Out function
is activated
:Any one of threshold voltage of B R pin
V
BR(TH)
(see Table 9-1)
, RB, RC and C4 should be selected based on actual
Overcurrent Protection Function (OCP) detects each
drain peak current level of a power MOSFET on
pulse-by-pulse basis, and limits the output power when
the current level reaches to OCP threshold voltage.
During Leading Edge Blanking Time, the operation of
OCP is different depending on the products as follows.
● STR-A60××HD:
During Leading Edge Blanking Time, the OCP
threshold voltage becomes V
is higher than the normal OCP threshold voltage as
shown in Figure 9-13. Changing to this threshold
voltage prevents the IC from respondi ng to the surge
voltage in turning-on the power MOSFET. This
function operates as protection at the condition such
as output windings shorted or unusual withstand
voltage of secondary-side rectifier diodes.
● STR-A60××M and STR-A60××H:
OCP is disabled during Leading Edge Blanking Time.
When power MOSFET turns on, the surge voltage
width of S/OCP pin should be less than t
Figure 9-13. In order to pr event surge voltage, pay extra
attention to R
trace layout (refer to Section 10.2).
OCP
In addition, if a C (RC) damper snubber of Figure
9-14 is used, reduce the capacitor value of damper
snubber.
= 1.55 V which
OCP(LEB)
, as sho wn in
BW
Figure 9-14. Damper Snubber
< Input Compensatio n Function >
ICs with PWM co ntr o l usual l y ha ve s o me pr o p aga tio n
delay time. The steeper the slope of the actual drain
current at a high AC input voltage is, the larger the
detection voltage of actual drain peak current is,
compared to V
. Thus, the peak current has some
OCP
variation depending on the AC input voltage in OCP
state. In order to reduce the variation of peak current in
OCP state, the IC incorporates a built-in Input
Compensatio n f unc t io n.
The Input Compensation Function is the function of
correction of OCP threshold voltage depending with AC
input voltage , as shown in Figure 9-15. When AC input
voltage is lo w (ON Duty is broad), the OCP threshold
voltage is controlled to become high. The difference of
peak drain current become small compared with the case
where the AC i np ut volt age is hi gh (O N D uty is na rr ow) .
The compensation signal depends on ON Duty. The
relation between the ON Duty and the OCP threshold
voltage after compensation V
' is expressed as
OCP
Equation (6). When ON Duty is broade r than 36 %, the
Figure 9-15. Relationship between ON Duty and Drain
Current Limit after Compensation
(6)
where,
: OCP Thre shold Voltage at Zero ON Duty
V
OCP(L)
DPC: OCP Compensat i on Coefficient
ONTime: On-time of power MOSFET
ONDuty: On duty of power MOSFET
f
OSC(AVG)
: Average PWM Switching Frequency
Page 20
STR-A6000 Series
PC1
C3
4
FB
/OLP
U1
VCC
5
GND
3
D2
R2
C2
D
VCC pin voltage
FB/OLP pin voltage
Drain current,
I
D
V
CC(OFF)
V
FB(OLP)
t
OLP
V
CC(ON)
Non-switching interval
t
OLP
×=
)NORMAL(CC
)NORMAL(OUT
OUT(OVP)
V
V
V
9.10 Overload Protection Function (OLP)
Figure 9-16 shows the FB/OLP pin peripheral circ uit,
and Figure 9-17 shows each waveform for OLP
operation. When the pea k drain current of I
by OCP operation, the output voltage, V
and the feedback current from the secondary
photo-coupler becomes zero. Thus, the feedback current,
, charges C3 connected to the FB/OLP pin and the
I
FB
FB/OLP pin voltage increases. When the FB/OLP pin
voltage increases to V
OLP delay time, t
= 68 ms or more, the OLP function
OLP
= 8.1 V or more for the
FB(OLP)
is activated, the IC stops switching o peration.
During OLP operation, Bias Assist Function is
disabled. Thus, VCC pin voltage decreases to V
the control circuit stops operation. After that, the IC
reverts to the initial state by UVLO cir cuit, and the IC
starts operation when VCC pin voltage increases to
by startup current. Thus the intermittent
V
CC(ON)
operation by UVLO is repeated in OLP state.
This intermittent op eration reduces the stress of parts
such as power MOSFET and secondary side rectifier
diode. In addition, this operation reduces power
consumption because the switching period in this
intermittent operation is short co mpared with oscillation
stop period. When the abnormal condition is removed,
the IC returns to normal operatio n automatically.
is limited
D
, decreases
OUT
CC(OFF)
,
9.11 Overvoltage Protection (OVP)
When a voltage between VCC pin and GND pin
increases to V
activated, the IC stops switching operation at the latched
state. In order to keep the latched state, when VCC pin
voltage decreases to V
activated and VCC pin voltage is kept to over the
CC(OFF)
.
V
Releasing the latched state is done by turning off the
input voltage and by dropping the VCC pin voltage
below V
V
BR(OUT)
CC(OFF)
.
In case the VCC pin voltage is provided by using
auxiliary winding of transformer, the overvoltage
conditions such as output voltage d etection circuit open
can be detected because the VCC pin voltage is
proportional to output voltage. The approxima te val ue o f
output volt age V
by using Equation (7).
where,
V
OUT(NORMAL)
V
CC(NORMAL)
: VCC pin voltage in normal operation
= 29 V or more, OVP function i s
CC(OVP)
, the bias assist function is
CC(BIAS)
, or by dropping the BR pin voltage below
OUT(OVP)
in OVP condition is calculated
29 (V)
(7)
: Output voltage in normal o peration
9.12 Thermal Shutdown Function (TSD)
When the temperature of control circuit increases to
= 135 °C (min.) or more, Thermal Shutdown
T
j(TSD)
function (TSD) is activated, the IC stops switching
operation at the latched state. In order to keep the
latched state, when VCC pin voltage decreases to
V
pin voltage is kept to over the V
Figure 9-16. FB/OLP Pin Peripheral Circuit
Releasing the latched state is done by turning off the
input voltage and by dropping the VCC pin voltage
below V
V
Take care to use properly rated, including derating as
necessary and proper type of components.
Figure 10-1. The IC Peripheral Circuit
• Input and Output Electrolytic Capacitor
Apply proper derating to ripple current, voltage, and
temperature rise. Use of high ripple current and low
impedance types, designed for switch mode power
supplies, is recommended.
• FB/OLP Pin Peripheral Circuit
C3 is for high frequency noise reduction and phase
compensation, and should be connected close to these
pins. The value of C3 is recommended to be about
2200 pF to 0.01µF, and should be selected based on
actual operation in the application.
•VCC Pin Peripheral Circuit
The value of C2 in Figure 10-1 is generally
recommended to be 10µ to 47μF (refer to Section 9.1
Startup Operation, because the startup time is
determined by the value of C2).
In actual power supply circuits, there are cases in
which the V CC p in vo lta ge fluc tua tes i n pr opo rti on to
the output current, I
(see Figure 10-2), and the
OUT
Overvoltage Protection function (OVP) on the VCC
pin may be activated. This happens because C2 is
charged to a peak voltage on the auxiliary winding D,
which is caused by the transie nt surge voltage c o upl ed
fro m the pri mary winding wh en the power MOSFET
turns off.
For alleviating C2 peak charging, it is effective to add
some value R2, of several tenths of ohms to several
ohms, in series with D2 (see Figure 10-1). The
optimal value of R2 should be determined using a
transformer matching what will be used in the actual
application, because the variation of the auxiliary
winding voltage is affected by the transformer
structural design.
• S/OCP Pin Peripheral Circuit
• BR pin peripheral circuit
Because R
voltage and are high resistance, t he following should be
considered according to the requirement of the
application:
See the section 9.8 about the AC input voltage
detection function and the components around BR pin.
When the detection resistor (R
decreased and the C4 value is increased to prevent
unstable operation resulting from noise at the BR pin,
pay attention to the low efficiency and the slow
response of BR pin.
detection. A high frequency switching current flows
to R
, and may cause poor operation if a high
OCP
inductance resistor is used. Choose a low inductance
and high surge-tolerant type.
a nd RB (see Figure 10-1) are app lied high
A
▫ Select a resistor designed against electromigration,
or
▫ Use a combination of resistors in series for that to
reduce each applied voltage
, RB, RC) value is
A
Figure 10-2. Variation of VCC Pin Volta ge and Power
•Snubber Circuit
In case the surge voltage of V
is large, the circuit
DS
should be added as follows (see Figure 10-1);
・ A clamp snubber circuit of a capacitor-resistor-
diode (CRD) combination should be added on the
primary wi nding P.
・ A damper snubber circuit of a capacitor (C) or a
resistor-capacitor (RC) combination should be
added between the D/ST pin and the S/OCP pin.
In case the damper snubber circuit is added, this
components should be connected near D/ST pin
and S/OCP pin.
Page 22
STR-A6000 Series
D
51
C51
R51
R52
U51
R54
R56
C52
S
PC1
R53
R55
L51
C53
VOUT
(-)
T1
(+)
Margin tape
Margin tape
Margin tape
Margin tape
P
1 S1 P2 S2
D
P1 S
1 D S
2 S1 P2
Winding structural example
(a)
Winding structural example (b
)
BobbinBobbin
•Peripheral circuit of secondary side shunt regulator
Figure 10-3 shows the secondary side dete c tion circuit
with the sta ndard shunt regulator IC (U51).
C52 and R53 are for phase compensation. The value
of C52 and R53 are recommended to be around
0.047μF to 0.47μF and 4.7 kΩ to 470 kΩ, respectively.
They should be selected based on actual operation in
the application.
Figure 10-3. Peripheral Circuit of Secondary Side
Shunt Regulator (U51)
▫ The coupling of the winding P and the secondary
output winding S should be maximized to reduce the
leakage inductance.
▫ The coupling of the winding D and the winding S
should be maximized.
▫ The coupling of the winding D and the winding P
should be minimized.
In the case of multi-output power supply, the
coupling of the secondary-side stabilized output
winding, S1, and the others (S2, S3…) should be
maximized to improve the line-regulation of those
outputs.
Figure 10-4 shows the winding st ructural e xamples
of two outputs.
Winding structural example (a):
S1 is sandwiched between P1 and P2 to
maximize the coupling of them for surge
reduction of P1 and P2.
D is placed far from P1 and P2 to minimize the
coupling to the primary for the surge reduction of
D.
Winding structural example (b )
P1 and P2 are placed close to S1 to maximize the
coupling of S1 for surge reduction of P1 and P2.
D and S2 are sandwiched by S1 to maximize the
coupling of D and S1, and that of S1 and S2.
This structure reduces the surge of D, and
improves the line-regulation of outputs.
•Transformer
Apply proper design margin to core temperature rise
by core loss and copper loss.
Because the switching currents contain high
frequency currents, the skin effect may become a
consideration.
Choose a s uitable wire gauge in considerati on of the
RMS current and a current density of 4 to 6 A/mm
If measures to further reduce temperature are still
necessary, the following should be considered to
increase the total surface area of the wiring:
▫ Increase the number of wires in parallel.
▫ Use litz wires.
▫ Thicken the wire gauge.
In the following cases, the surge of VCC pin
voltage bec omes high.
▫ The surge voltage of primary main winding, P, is
▫ The winding structure of auxiliary winding, D, is
When the surge voltage of winding D is hi gh, the
VCC pin voltage increases and the Overvoltage
Protection function (OVP) may be activated. In
transformer design, the following should be
considered;
2
.
high (low output voltage and high output current
power supply designs)
susceptible to the noise of winding P.
Figure 10-4. Winding Structural Examples
10.2 PCB Trace Layout and Component
Placement
Since the PCB circuit trace design and the component
layout significantly affects operation, EMI noise, and
power dissipation, the high frequency PCB trace should
be low impedance with small loop and wide t race.
the IC should be as close to the
IC as possible, and should be
connected as short as possible
In additi o n, the ground traces affect radia ted EMI noi se,
and wide, short traces should be taken into account.
Figure 10-5 shows the circuit design example.
(1) Main Circuit Trace Layout
This is the ma in trace co ntaining s witching c urrents,
and thus it should be as wide trace and small loop as
possible.
If C1 and the IC are distant from each other, placing
a capacitor such as film capacitor (about 0.1 μF and
with prope r voltage rating) clo se to the transformer
or the IC is recommended to reduce impedance of
the high frequency current loop.
(4) R
(5) Peripheral components of the IC
Trace Layout
OCP
should be placed as close as possible to the
R
OCP
S/OCP pin. The connection between the power
ground of the main trace and the I C ground should
be at a single po int ground (poi nt A in Figure 10-5)
which is close to the base of R
OCP
.
The components for control connected to the IC
should be placed as close as possible to the IC, and
should be connected as short as possible to the each
pin.
(2) Control Ground Trace Layout
Since the operation of IC may be affected from the
large current of the main trace that flows in control
ground trace, the control ground trace should be
separated from main trace and connected at a single
point ground ing o f poi nt A in Figure 10-5 as close to
the R
pin as possible.
OCP
(3) VCC Trace Layout
This is the trace for supplying power to the IC, and
thus it should be as small loop as possible . If C2 and
the IC are distant from each other, placing a
capacitor such as film capacitor C
(about 0.1 μF to
f
1.0 μF) close to the VCC pin and the GND pin is
recommended.
(6) Secondary Rectifier Smoothing Circuit Trace
Layout:
This is the trace of the rectifier smoothing loop,
carrying t he switchin g current, and thus it should b e
as wide trace and small loop as possible. If this trace
is thin and long, inductance result ing from the loop
may increase surge voltage at turning off the po wer
MOSFET. Proper rectifier smoothing trace layout
helps to increase margin against the power MOSFET
breakdown voltage, and reduces stress on the clamp
snubber circuit and losses in it.
(7) Thermal Considerations
Because the power MOSFET has a positive thermal
coefficient of R
, consider it in thermal design.
DS(ON)
Since the copper area under the IC and the D/ST pin
trace act as a heatsink, its traces should be as wide as
possible.
Figure 10-5. Peripheral Circuit Example Around the IC
Page 24
STR-A6000 Series
3
CN1
C3
T1
D51
R52
U51
D1
P1
S1
PC1
4
L51
L2
C52
R53
C4
F1
1
3
C1
TH1
L1
NC
124
D/ST D/ST
BR
S/OCPFB/OLP
VCC
87
5
STR-A6000
U1
GND
3
1
2
OUT2(+)
C5
C7
C6
C8
C10
C11
D2
D3
D4
D1
D7
D8
R3
R4
R1
R5
R7
R6
D52
C51C53
C55
R51
R54
R55
R56
R57
R58
R59
R60
R61
JW51JW52
JW2
JW3
CP1
C54
C57
CN51
C2
C9
JW4
OUT2(-)
OUT1(+)
OUT1(-)
1
2
OUT3(+)
D21
C21
R21
OUT3(-)
IN OUT
GND
1
2
3
U21
C22
D2
1
2
OUT4(+)
D31
C31
R31
OUT4(-)
C32
JW31
JW21
CN21
CN31
R2
L52
C56
C12
C13
JW6
JW7
JW8
JW9
JW10
JW11
JW53
JW54
11. Pattern Layout Example
The following show the PCB pattern layout example and the schematic of circuit using STR-A6000 series.
The above circuit symbols correspond to these of Figure 11-1.Only the parts in the schematic are used. Other parts
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