This Service Manual is a property of Samsung Electronics Co.,Ltd.
Any unauthorized use of Manual can be punished under applicable
International and/or domestic law.
ⓒ
Samsung Electronics Co.,Ltd. December. 2005
Printed in Korea.
Code No.: GH68-08926A
BASIC.
1. Specification
1-1. GSM General Specification
GSM900
Phase 1
Freq. Band[MHz]
Uplink/Downlink
ARFCN range1~124
Tx/Rx spacing45MHz45MHz95MHz80MHz
Mod. Bit rate/
Bit Period
Time Slot
Period/Frame Period
Modulation0.3GMSK0.3GMSK0.3GMSK0.3GMSK
MS Power33dBm~5dBm33dBm~5dBm30dBm~0dBm30dBm~0dBm
890~915
935~960
270.833kbps
3.692us
576.9us
4.615ms
EGSM900
Phase 2
880~915
925~960
0~124 &
915~1023
270.833kbps
3.692us
576.9us
4.615ms
DCS1800
Phase 1
1710~1785
1805~1880
512~885512~810
270.833kbps
3.692us
576.9us
4.615ms
Phase 1
1850~1910
1930~1990
270.833kbps
4.615ms
PC1900
3.692us
576.9us
Power Class5pcl ~ 19pcl5pcl ~ 19pcl0pcl ~ 15pcl0pcl ~ 15pcl
Sensitivity-102dBm-102dBm-100dBm-100dBm
TDMAMux8888
Cell Radius35Km35Km2Km2Km
1-1
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Specification
1-2. GSM TX power class
TX Power
control level
533±3 dBm
631±3 dBm
729±3 dBm
827±3 dBm
925±3 dBm
1023±3 dBm
1121±3 dBm
GSM900
TX Power
control level
030±3 dBm
128±3 dBm
226±3 dBm
324±3 dBm
422±3 dBm
520±3 dBm
618±3 dBm
DCS1800
TX Power
control level
030±3 dBm
128±3 dBm
226±3 dBm
324±3 dBm
422±3 dBm
520±3 dBm
618±3 dBm
PCS1900
1219±3 dBm
1317±3 dBm
1415±3 dBm
1513±3 dBm
1611±5 dBm
179±5dBm
187±5 dBm
195±5 dBm
716±3 dBm
814±3 dBm
912±4 dBm
1010±4 dBm
118±4dBm
126±4 dBm
134±4 dBm
142±5 dBm
716±3 dBm
814±3 dBm
912±4 dBm
1010±4 dBm
118±4dBm
126±4 dBm
134±4 dBm
142±5 dBm
150±5 dBm
1-2
150±5 dBm
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2. Circuit Description
2-1. SGH-X490 RF Circuit Description
2-1-1. RX PART
- ASM(U100)→Switching Tx, Rx path for GSM900, DCS1800, PCS1900 by logic controlling.
- FILTER
To convert Electromagnetic Field Wave to Acoustic Wave and then pass the specific frequency band.
- GSM FILTER (F101)→For filtering the frequency band between 925 and 960 MHz
- DCS FILTER (F102)→For filtering the frequency band between 1805 and 1880 MHz.
- PCS FILTER (F100)→For filtering the frequency band between 1930 and 1990 MHz.
- VC-TCXO (OSC101)
This module generates the 26MHz reference clock to drive the logic and RF. After division by two a reference clock of
13MHz is supplied to the other parts of the system through the pin CLKOUT. After additional process, the reference
clock applies t o the U100 Rx IQ demodulator and Tx IQ modulator. And then, the oscillator is controlled by serial data
to select channel and use fast lock mode for GPRS high class operation.
→
Truth Table
VC1VC2VC3
- Transceiver (U101)
The receiver front-end which amplifies the GSM, DCS, PCS aerial signal, converts the chosen channel down to a low IF
signal of 100 kHz. The first stages are symmetrical low noise amplifiers (LNAs). The LNAs are followed by an IQ down
mixer. It consists of two mixers in parallel but driven by quadrature out of phase LO signals. The In phase (I) and
Quadrature phase (Q) IF signals are low pass filtered to provide protection from high frequency offset interferes. The low
IF I and Q signals are then fed into the channel filter. The front-end low IF I and Q outputs enter the integrated
bandpass channel filter with provision for five 8 dB gain steps in front of the filter.
2-1-2. TX PART
I and Q baseband signals are applied to the IQ modulator that shifts the modulation spectrum up to the transmit IF. It is
designed for low harmonic distortion, low carrier leakage and high image rejection to keep the phase error as small as
possible.
2-1
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Circuit Description
The modulator is loaded at its IF output by an integrated low pass filter that suppress unwanted spurs prior to get into
the phase detector. The clock drive is generated by division of the RFLO signal provided for the transmit offset mixer.
Baseband IQ signal fed into offset PLL, this function is included inside of U101 chip. OSC100 chip generates modulator
signal which power level is about 6.5dBm and fed into Power Amplifier(U102). The PA output power and power ramping
are well controlled by Auto Power Control circuit. We use offset PLL below table.
GSM-36dBm
DCS-36dBm
GSM-36dBm
DCS-36dBm
GSM-51dBm
DCS-56dBm
Modulation Spectrum
200kHz offset
30 kHz bandwidth
400kHz offset
30 kHz bandwidth
600kHz ~ 1.8MHz offset
30 kHz bandwidth
2-2. Baseband Circuit description of SGH-X490
2-2-1. PCF50601
- Power Management
Ten low-dropout regulators designed specifically for GSM applications power the terminal and help ensure optimal system
performance and long battery life. A programmable boost converter provides support for 1.8V, 3.0VSIMs, while a selfresetting, electronically fused switch supplies power to external accessories. Ancillary support functions, such as RTC
module and High Voltage Charge pump, Clock generator, aid in reducing both board area and system complexity.
I2C BUS serial interface provides access to control and configuration registers. This interface gives a microprocessor full
control of the PCF50601 and enables system designers to maximize both standby and talk times.
Supervisory functions. including a reset generator, an input voltage monitor, and a temperature sensor, support reliable
system design. These functions work together to ensure proper system behavior during start-up or in the event of a fault
condition(low microprocessor voltage, insufficient battery energy, or excessive die temperature).
-Backlight Brightness Modulator
The Backlight Brightness Modulator (BBM) contains a programmable Pulse-width
to modulate the intensity of a series of LED’s or to control a DC/DC converter that drives LCD backlight.
This phone (SGH-X490) use PWM control to contrast the backlight brightness.
Clock Generato
-
The Clock Generator (CG) generates all clocks for internal and external usage. The 32768 Hz crystal
oscillator provides an accurate low clock frequency for the PCF50601 and other circuitry.
r
2-2
modulator (PWM) and FET
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Circuit Description
2-2-2. LCD Connector
LCD is consisted of main LCD(color 65K UFB LCD) and sub LCD (B/W LCD).
Chip select signals LCD_MAIN_CS and LCD_SUB_CS, can enable Each LCD. BACKLIGHT signal enables white LED
of main LCD. "LCD_RESET" signal initiates the reset process of the LCD.
16-bit data lines(HD(0)~HD(15)) transfers data and commands to LCD. Data and commands use "HA(1)" signal. If this
signal is low, inputs to LCD are commands. If it is high, inputs to LCD are data.
The signal which informs the state of LCD is whether input or output, is required. But in this system, there is no input
state from LCD. So only "HA(1)" signal is used to indicate write data or command to LCD. Power signals for LCD are
"VBAT and "VDD3".
"SPK_P" and "SPK_N" are used for audio speaker containing voice or melody. And "VDD_VIB" from PCF50601
enables the motor.
2-2-3. Key
This is consisted of key interface pins among OM6359, KBIO(0:7). These signals compose the matrix. Result of matrix
informs the key status to key interface in the OM6359. Power on/off key is separated from the matrix. So power on/off
signal is connected with PCF50601 to enable PCF50601. Twelve key LEDs are use the "VDD_KEY" as supply voltage.
"FLIP" informs the status of folder (open or closed) to the OM6359. This uses the hall effect IC, A321ELH-SAMSUNG.
A magnet under main LCD enables A321ELH-SAMSUNG.
2-2-4. EMI ESD Filter
This system uses the EMI ESD filter, EMIF09 to protect noise from IF CONNECTOR part.
2-2-5. IF connetor
It is 18-pin connector. They are designed to use VBAT, V_EXT_CHARGE, TXD0, RXD0, RTS0, CTS0, JIG_REC,
CHARGER_OK, RXD1, TXD1, AUX_MIC, AUX_SPK and GND. They connected to power supply IC, microprocessor
and signal processor IC.
2-2-6. Battery Charge Management
A complete constant-current/constant-voltage linear charger is used for single cell lithium-ion batteries.
If TA connected to phone, "+DCVOLT" enable charger IC and supply current to battery.
When fault condition caused, "CHG_ON" signal level change low to high and charger IC stop charging
process.
2-2-7. Audio
EARP_P and EARP_N from OM6359 are connected to the main speaker. MIC_P and MIC_N are connected to the main
MIC. YMU788 is a synthesizer LSI for mobile phones. It is a LSI as an input/output device for sound sources, which is
the mobile phones, such as MP3, AAC, etc, in addition to ringing-melodies.
As a synthesis, YMU788 is equipped 32 voices with different tones. Since the device is capable of simultaneously
generating up to synchronous with the play of the FM synthesizer, various sampled voices can be used as sound effects.
Since the play data of YMU788 are interpreted at anytime through FIFO, the length of the data(playing period) is not
limited, so the device can flexibly support application such as incoming call melody music distribution service.
2-3
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Circuit Description
The hardware sequencer built in this device allows playing of the complex music without giving excessive load to the
CPU of the portable telephones.
For the purpose of enabling YMU788 to demonstrate its full capabilities, Yamaha purpose to use "SMAF:Synthetic music
Mobile Application Format" as a data distribution format that is compatible with multimedia. Since the SMAF takes a
structure that sets importance on the synchronization between sound and images, various contents can be written into it
including incoming call melody with words that can be used for training karaoke, and commercial channel that combines
texts, images and sounds, and others. The hardware sequencer of YMU788 directly interprets and plays blocks relevant to
synthesis (playing music and reproducing ADPCM with FM synthesizer) that are included in data distributed in SMAF.
2-2-8. Memory
Signals in the OM6359 enable two memories. They use two volt supply voltage, VDD3 in the PCF50601 & VDD_1.9V
with a LDO. This system uses Intel's memory, RD38F3050LOZTQ0. It is consisted of 128M bits flash NOR memory and
64M bits SRAM. It has 16 bit data line, HD[0~15] which is connected to OM6359. It has 26 bit address lines,
HA[1~26]. NCSFLASH & NCSRAM signals are chip select. Writing process, HWR_N is low and it enables writing
process to flash memory and SRAM. During reading process, HRD_N is low and it enables reading process to flash
memory and SRAM. Reading or writing procedure is processed after HWR_N or HRD_N is enabled.
2-2-9. OM6359
OM6359 is consisted of ARM core and DSP core. It has
on-chip program ROM
of KBS, JTAG, EMI and UART. ARM core is consisted of EMI, PIC(Programmable Interrupt Controller),
reset/power/clock unit, DMA controller, TIC(Test Interface Controller), peripheral bridge, PPI, SSI(Synchronous Serial
Interface), ACC(Asynchronous communications controllers), timer, ADC, RTC(Real-Time Clock) and keyboard interface.
KBIO(0:7), address lines of DSP core and HD[0~15]. HA[1~26], address lines of ARM core and HD[0~15], data lines of
ARM core are connected to memory, YMU788.
NCSRAM, NCSFLASH in the ARM core are connected to each memory. HWR_N and HRD_N control the process of
memory. External IRQ(Interrupt ReQuest) signals from each units, such as, PMU need the compatible process.
KBIO[0~7] receive the status from key and RXD0/TXD0 are used for the communication using data link
cable(DEBUG_DTR/RTS/TXD/RXD/CTS/DSR).
It has JTAG control pins(TDI/TDO/TCK) for ARM core and DSP core. It receives 13MHz clock in CKI pin from
external TCXO. ADC(Analog to Digital Convertor) part receives the status of temperature, battery type and battery voltage.
in the DSP. It has 4K*32bits ROM and 2K*32bits RAM in the ARM core. DSP is consisted
8x1Kword on-chip program/data RAM, 55 Kwords
2-2-10. TOH2600DGI4KRA(26MHz)
This system uses the 26MHz TCXO, TOH2600DGI4KRA, SEM. AFC control signal from OM6359 controls frequency
from 26MHz x-tal. The clock output frequency of UAA3536 is 13MHz. This clock is connected to OM6359, YMU788.
2-4
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3. Exploded View and Parts List
3-1. Exploded View
QFU01
QLC01
QSP01
QFR01
QSC14
QVO01
QKP01
QMP01
QME01
QVK01
QMI01
QAN02
QRE01
QMO01
QFL01
QCR53
QSC01
QMW02
QCR11
QRF01
QBA01
QRF03
QMI03
QIF01
3-1
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