Page 1
Samsung Electronics 13-1
13. Circuit Operating Description
13-1 Summary
13-1-1 Purpose
The document which sees with System Design specification of Digital Camcorder “VP-D353 System“,
it was hereafter maked for setting the direction of business propulsion by standardizing the system structure
and Hard ware and the Soft ware plan specification.
13-1-2 Range
The low rank system which constitutes VP-D353 is classified by Main PCB, Camera Lens Ass’y, Left Function
Ass’y, Front Ass’y, Deck Ass’y, Rear Ass’y, etc..
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Circuit Operating Description
13-2 Samsung Electronics
13-2 Digital Camcorder Summary
13-2-1 Digital Camcorder Definition
Digital Camcorder is SAMPLING FREQUENCY 13.5MHZ (CHROMA 6.75MHZ) and 8Bit.
Adopted-child-ized VIDEO SIGNAL, SAMPLING FREQUENCY 48KHZ 16BIT and SAMPLING FREQUENCY
DV FORMAT EWI of AUDIO SIGNAL of 32KHZ 12BIT is carried out. About 1/carries out DATA compression by
5. 6.35mm the thing which carry out record reproduction at TAPE and on which it crawls — the high definition
of the level resolution of about 520 LINE(s), and reason tone quality of a PCM system PROTOCOL like IEEE1394,
USB, or RS232C — PC or other DIGITAL equipments, and DATA transmission It is an equipment with the
possible feature.
- High Resolution Picture Quality : About 520 LINE holigental
- High Sound Quality by PCM Method : Sampling Frequency 48khz 16bits
Sampling Frequency 32khz 12bits
- EASY EDIT & EASY CONNECTION WITH PC& OTHER DV EQUIPMENT
13-2-2 Set System practical use
- Other A/V equipments and connection edits.
- DATA transmitting edit using PC and other DIGITAL equipments, IEEE1394, USB, and Protocol.
- They are JPEG / MPEG4 preservation DISPLAY to MEMORY STICK.
Fig. 13-1
Page 3
Circuit Operating Description
Samsung Electronics 13-3
13-3 Set Explanation
13-3-1 Consideration matter at the time of a design
(1) Environment condition: Astandard is carried out to a CAMCORDER reliability examination rule (6CA-1001).
1) Operating Conditions
Œ Temperature : 0° ~ +40°
´ Humidity : 10% ~ 80%
2) Storage Temperature
Œ Temperature : -20° ~ +60°
(2) DVC Pattery Format
Fig. 13-2 DVC Pattery Format
Fig. 13-3 Sector arrangement on helical track
H2
H1
Tp=10um
SUB CODE
VIDEO
AUDIO
ITI
Lr=32.89mm
OPTIONAL TRACK
We=5.24mm
HO=5.8mm
Wt=6.35mm
TAPE
a=9.1668°
TAPE LOWER EDGE
PRE4
1200bits
PRE3
500bits
PRE1
1400bits
S S A
1830bits
TIA
90bits
POS1
280bits
G1
625bits
PRE2
500bits
AUDIO
(14 Sync blocks)
G2
700bits
POS2
550bits
POS3
975bitsG21550bits
VIDEO
(149 Sync blocks)
SUBCODE
1200bits
POS4
1200bits
OVERWRITE
MARGIN
1250bits
HEAD
VIDEO SECTOR
TRACK PAIR
AUDIO SECTOR
ITI SECTOR
ATF
SUBCODE SECTOR
HEAD
(3) Sector Arrangement on helical track
Page 4
(4) Ampling structue of ITU-R656 (4:2:2)
Circuit Operating Description
13-4 Samsung Electronics
NO Item 525/60 System 625/50 System
1 SAMPLING frequency
luminunse (Y) frequency 13.5MHz
chrominance (Cr,Cb,) frequency 6.75MHz
2 pixel/line
luminunse (Y)frequency 858 864
chrominance (Cr,Cb,) frequency 429 432
3 ACTIVE PIXEL / LINE
luminunse (Y) frequency 720
chrominance (Cr,Cb,) frequency 360
4 ACTIVE LINE / FRAME 480 576
5 ACTIVE LINE No.
FIELD1 23~262 285~524
FIELD2 23~310 335~622
6 quantum Y, Cr, Cb, etc. are by carrying out, and they are 8bits straight lines
quantum.
7A relation with level which scale 1~254
serves as the analog picture level: Y LEVEL 220 : WHITE LEVEL=235
signal level quantum BLACK LEVEL=16
Cr,Cb LEVEL 225 : GRAY LEVEL =128
Mode Channel Sampling Frequency Quantization
48K mode 2 48KHz 16Bits linear
44.1K mode - 44.1KHz 32K mode - 32KHz -
32k 4ch mode 4 32KHz 12Bits nonlinear
<Table 13-1 Sampling structure of ITU-R656 (4:2:2)>
<Table 13-2 Audio Encoding mode>
(5) Audio Encoding mode
Page 5
Circuit Operating Description
Samsung Electronics 13-5
(6) Video Signal
Fig. 13-4 Video Signal
Blanking
IRE
(714mv)
40 IRE
(286 mv)
Ref Sync Amplitude
Ref White
Blanking
Level
Color
Back
Porch
Front
porch
40IRE
(Ref Burst
Amptd)
4 IRE
20
IR E
4 IRE
7.5 IRE
Z
Z
0.7 Vpp
0 Vpp
- 0.15 Vpp
- 0.3 Vpp
100% (0.3Vpp)
ntsc timing
pal timing
10.9µs ± 0.2µs
SYNC to Blanking End
9.4µs ± 1µs
SYNC to Burst End
7.8µs
Breezeway
Burst
2.5µs
1.6µs
SYNC
4.7µs±1µs
6µs
tr, tf 250ns ± 50ns
tr, tf 200ns ± 50ns
2.25µs ± 0.2µs (10cycles)
5.6µs ± 0.1µs
4.7µs ± 0.2µs
FP 1.5 + 0.3µs
12 ± 0.3µs
1.5µs±.1
100µs
50%
Page 6
Circuit Operating Description
13-6 Samsung Electronics
(7) Safe standard
1) SAFETY
UL1492 U.S.A. Standard for Audio and video products
CSA Std. C22.2 Canada Standard for Audio and video products
EN60065 Europe Standard for Audio and video products
GOST-R Russia Standard for Audio and video products
Safety Assurance Regulation No. 776 (Adapter only)
<Table 13-3 Safety>
FCC Part 15B USA Standard (Class B Radio Frequency Devices)
EN 55013 Europe Standard (EMI Part of CE)
EN 55020
EN 61000-3-2
Europe Standard (EMS part of CE)
EN61000-3-3
EN61000-4-3
GOST R 51515-99 Russia Standard (EMI /EMS)
AS/NZS 1053 Australia Standard (EMI)
Domestic electromagnetic
Domestic electromagnetic wave conformity registration
wave conformity registration
<Table 13-4 EMC>
2) EMC
Page 7
Circuit Operating Description
Samsung Electronics 13-7
13-4 H/W demand matter
13-4-1 Main PCB H/W demand matter
Main PCB carries out record reproduction of the input of the signal into which the optical signal was
electrically changed from CCD of CAMERA LENS ASS’Y, and an AUDIO signal by DV FORMAT at
6.35mm Tape.
It consists of circuits PCB which save or DISPLAY by JEPG and MPEG4 to MEMORY STICK. It constitutes
from the CAMERA circuit BLOCK, SYSCON/SERVO BLOCK, DV_1_CHIP BLOCK, DC/DCBLOCK,
PREAMP BLOCK, PRML BLOCK, and AUDIO/VIDEO I/F BLOCK.
13-4-2 Camera circuit Block H/W requirement
The CAMERA circuit BLOCK carries out CDS->AGC->10 Bits A/D conversion of Ccd_out Signal by
which electronic conversion was carried out from Camera Lens Ass’y.
LUMINANCE and CHROMINANCE are transformed by ITU-R 656 Format.
It is made to output by DV-1 CHIP.
It was inputted into ITU-R 656 FORMAT from DV-1 CHIP. A DIGITAL EFFECT function (PB ZOOM,
PB MOSAIC, PB MIRROR) is carried out for a VIDEO signal.
Signal inputted from CAMERA LENS or DV-1 CHIP MEMORY STICK preservation / DISPLAY is
carried out by JPEG and MPEG4 FORMAT.
S5C7376X (ICM01)
DSP6
DIS/JPEG/MPEG4/USB
54MHz
K4S283233F-EE75
64M DSRAM
MBM29LV160BE
(ICA03)
4M FLASH MEMORY
SMC/MS
TLV990B(ICP02)
CDS/AGC/ADC
uPD168103(ICP03)
ZOOM/FOCUS
MOTOR DRIVER
DV1 CHIP(IC201)
GLOBALi
TMP1962(IC501)
MICOM
CCD-OUT
ZOOM MOTOR
FOCUS MOTOR
BU7806-01KV
(IC601)
AUDIO I/F
Fig. 13-5 Camera Circuit Block Diagram
Page 8
Circuit Operating Description
13-8 Samsung Electronics
13-4-3 SYSCON/SERVO Block H/W demand matter
At SYSTEM/SERVO BLOCK, it is TMP1962. It is each BLOCK at 32BIT 1MByte MICRO
PROCESSOR.CONTROL(ing) IC and a circuit, MAIN CLOCK uses 13.5Mhz(es).
RTC use of the exception way for SUB CLOCK LITHIUM BATTERY 3V BACK UP functional execution is
carried out. MICOM to PWM PULSE for MOTOR control and an ON/OFF CONTROL signal are
inputted, and the phase and speed of DRUM of DD-10 DECK and CAPSTAN MOTOR are controlled by
SERVO Block.
Moreover, input of the various kinds SENSOR of DECK (TOP/END, T/S REEL, Media Interface
Connector SW, RECPROOF, CC LOCK Etc) is carried out, and micom is made to print out.
Made to REGULATION LOADING MOTOR 4.7V VS.
DCDC
BLOCK
PRML
BLOCK
PREAMP
BLOCK
DV1_Chip
BLOCK
AV I/F
BLOCK
CAMERA
BLOCK
TMP1962F10
(IC501)
MICOM
LB11993W
(IC401)
MOTOR
DIRVER
T/S SENSOR
REEL SENSOR
MIC SENSOR
DRUM
MOTOR
CAP.
MOTOR
LOAGDING
MOTOR
RS5C372A
(IC502)
RTC IC
RESET-IC
XC6413FY01MR
(IC503)
EEPROM
524AB0X91
(IC505)
W
U
V
FG/PF
W
U
V
FG
Fig. 13-6 VCR Circuit Block Diagram
Page 9
Circuit Operating Description
Samsung Electronics 13-9
13-4-4 DV-1 Chip Block H/W demand matter
DV_1 CHIP BLOCK is AV I/F BLOCK to a CAMERA circuit or a VIDEO signal at the time of Record MODE.
Function . which inputs by ITU-R 656 FORMAT, SHUFFLING(s), and sends RECODING DATA by PREAMP
Block.
At the time of TAPE reproduction, PRML BLOCK to 41.5 Mhz PB_CLK and PB_DATA are inputted, and ECC
DECODING, DECOMPRESSION, and a DESHUFFLE function are carried out, and it is again inputted into the
CAMERA circuit BLOCK after output VIDEO DATA by ITU-R 656 FORMAT, and is with VIDEO Y/C SIGNAL
to AV I/F BLOCK. You have to carry out the DATA communication function which sent and carried out
IEEE1394 PROTOCOL EWI of AUDIO CLOCK/DATA.
DV1 CHIP
(GLOBALi)
IC201
BU7806
(IC601)
IC-AUDIO I/F
NJM2538
(IC301)
IC-VIDEO I/F
S5C7376X
(ICM01)
DSP6
LDV5000
(IC101)
IC-PRML
LD3502
(IC101)
IC-PREAMP
41.85MHz
TMP1962
(IC501)
MICOM
ITU-R656
54MHz/
27MHz
Y/C
CLK/DATA
TSB41AB1
(IC204)
PHY. LAYER
54MHz
REC DATA
PB CLK/ DATA
Fig. 13-7 DV-1 Chip Block Diagram
Page 10
Circuit Operating Description
13-10 Samsung Electronics
13-4-5 PRML Block H/W Demand matter
At PRML BLOCK, it is Control Signal of Micro Processor to Serial Enable/Data/Clock. In each mode star (SPPB, LP gas-PB, SP-Forward/Reverse Search, LP gas-Search, SP-Slow, LP gas-slow etc) You must be made to
carry out data control. moreover, Head S/W Pulse is inputted, the signal of the High section of an incoming
signal (Envelope Output) and the Low section is divided at the time of reproduction, and signal processing is
realized continuously as You have to become Control. In response to the control signal of Power Down from
DV-1chip (Channel Block), PB-High, and Adaptive High, operation is stopped between Recording Time
(Power Down), and normal signal processing operation is control(ed) between Playback Time. You have to
perform Playback operation by making and supplying 41.85MHz PB Clock and PB Data by DV-1chip (Channel
Block). When the unstable incoming signal by the 41.85MHz signal is inputted from a PREAMP way from DV1chip (Channel Block) (Search Mode or tape damage etc), this signal and it is made to perform stable in
reproduction operation. PREAMP to Differential Function(s), such as the supply receptacle AGC, Dropout,
Analog qualizer, Digital Equalizer, 1+D, and Viterbi, are carried out for the reproduction print-out signal of
input (DIP, DIN). PB data of 41.85Mbps(es) is supplied by DV-1chip (Channel Block). X2 process must be
performed for 20.925MHz which is the highest frequency of a reproduction signal to a reproduction signal,
and 41.85MHz PB clock must be supplied by DV-1chip (Channel Block). ATF Signal Processor is performed
from a reproduction print-out signal, and it is ATF of F0/F1 (465kHz)/F2 (697.5kHz).ATF Error Signal for
coltrol is made.It supplies by Micro Processor and must be made to have to use by the object for Capstan
Control.A two-sort power supply (3.3Vdc and 1.8Vdc) is supplied from DC/DC.
It uses with a power supply of operation and the standard power supply of block required for control of the
signal for control with the exterior. Internal 1.8V regulator can be operated by Exterior option (pull up or pull
down). At this time, the external country can be used in the 3.3V single country.
Page 11
Circuit Operating Description
Samsung Electronics 13-11
13-4-6 PREAMP Block H/W Demand matter
With PREAMP Block Amp_cs from DV-1chip (Channel Block) and a PB-High signal perform Recording and
Playback operation.
In response to Recording Data of 3 Vp-p, after DRUM performing amplification operation, each signal must be
printed out in Head S/W High and the Low section, and you have to perform Recording operation. Micro
Processor to Head S/W Pulse is used, and it is Head S/W at the time of recording and playback operation.
You have to divide and output each signal in the High and Low section.
From DRUM After performing operation which amplifies 51dB of signals which became pick up, you have to
output Differential signal output in PRML Block.
13-4-7 AV I/F Block H/W Demand matter
AUDIO/VIDEO I/F BLOCK carries out a 16 BITS AD/DA input-and-output INTERFACE function for an
AUDIO signal. You have to form BEEP SOUND and a SPEAKER output signal at the time of KEY INPUT.
COLOR OSD and a MENU DISPLAY function are carried out by the function.
Y/C SIGNAL is MIXING(ed) with an input OSD signal by DV-1 CHIP BLOCK, and VIDEO COMPOSITE
SINGAL must be output by FRONT Block.
It is at ITU-R 656 about the VIDEO input SIGNAL inputted from VIDEO JACK or SUPER JACK. DV-1 CHIP It
output by Block.
LINE IN
EXT. MIC
INT. MIC
SPEAKER
LINE OUT
S-JACK
AV JACK
BU7806
(IC601)
AUDIO IF-IC
NJM2538
(IC301)
VIDEO IF-IC
DV1 CHIP
(GLOBALi)
IC201
TMP1962F10
(IC501)
MICOM
Fig. 13-8 AV Interface Block Diagram
Page 12
Circuit Operating Description
13-12 Samsung Electronics
13-4-9 CAMERA LENS ASS’Y H/W Demand matter
CAMEAR LENS ASS’Y is a function which makes an image for the light (Data) emitted with a photographic
subject to a focal side (CCD). It carries out.
LENS It consists of 4part(s), such as Zoom, Relay, and Focus.
Although Front and Relay LENS are being fixed, Zoom and Focus Part must carry out the use drive of
Zooming and the Auto Focusing harm Stepping Motor. It is automatic and light is made to adjust. Auto Iris is
used for a sake.
It is generated for the regularity of Ccd, and a photographic subject’s regularity.noise ingredient
It loses.In order to intercept White Balance and infrared rays, you have to adopt Optical Low Pass Filter.
13-4-8 DC/DC Block H/W Demand matter
DC/DC BLOCK receives BATTERY 7.4V or ADAPTER 8.4V, and is the use country according to BLOCK.The
function supplied stably is carried out.
BLOCK another use power supply CAM5V, CAM15V, CAM-7.5V, and DIG3V, DIG1.8V, SS3.0V, SS5.0V, and
SS1.8V LCD BL5V it carries V.LIGHT 5.0V
In response to DRUM ERROR and a CAPSTAN ERROR signal, you have to supply DRUM VS and CAPSTAN
VS to a SERVO circuit from MICOM BLOCK.
BATT.&
ADAPTER
TMP1962
(IC501)
MICOM
BD9833KV
(IC701)
PWM-IC
LPF
DRUM VS
LPF CAPSTAN VS
LPF SS 3.0V
LPF SS 5.0V
LPF SS 1.8V
LPF LCD BL5V
LPF
CCD/LCD
-7.5V,-15V,+15V
LPF V.LOGHT5.0V
LPF
LPF
VTR DDON
CAM DD ON
D.ERR
C.ERR
Fig. 13-9 DC/DC Block Diagram
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