Samsung Sdc-33 Reference Information
2. Reference Information
2-1 Circuit description
2-1-1 DSC
Digital camera(SDC-30/33), is an image-input device that connects to a PC. It’s small and light welght, supplies high quality images and has a large capacity (4MB/2MB). The digital camera consists of 3 sections: Camera, signal processing and storage.
1. Camera
The camera is similar to a camcorder but adapts a scanning method of 525/30 (which can read an entire image of in one frame, whereas the camcorder’s scanning method is 525/60.
Photo-exposure is controlled by the electronic shutter through timing generator and CCD driver IC (where as a camcorder controls the exposure using an IRIS).
Main function of this part is to control the photo-exposure in accordance with the brightness, and to store the image in DRAM.
2. Digital Signal Processing
Image information of 1 frame is temporarily stored in DRAM. Image information stored in DRAM is the digitalized CCD signal from the camera. It needs additional image signal processing by the 32-bit microprocessor. The image signal processing done by the microprocessor includes white balance, shape adjustment and Y/C signal conversion.
3. Storage
After image signal processing, an image signal compression technique allows more image to be stored in the limited memory. In the case of SDC-30/33, 10:1 compression is normally executed for standard JPEG specification. After compression, the image information is stored in the nonvolatile flash memory : Max. 45/22 frame for VGA(640*480), and max 180/90 frame for QVGA(320*240).
The image can be stored, edited, and printed by the PC image editing program that is supplied with the camera.
2-1-2 Power
LCD MICOM generates the control signal that turns on the system (5V). When the power is on, the signal turns on IC140 PWM IC which outputs 5V through T141.
When shot key is pressed, the signal for output is generated from MICOM, which turns on IC120 PWM IC and outputs 5V, -7V, and 15V through T121. After the shot, the camera control signal turns off the power supply within. 5sec (through T121).
2-1-3 DC/DC block operation description
2-1-3(A) DC/DC BLOCK CONSISTS OF THREE COMPONENTS AS BELOW.
1. EVER5V
EVER5V consists of S8420 (IC100) IC and the assocciat battery circuitry (CN101 Pin2) is input to
IC100 (S8420). Pin 8 and 5V voltage are generated internally and are output to pins 1 and 7. EVER5V power (Pin 1) is input to the function board for LCD MICOM (IC601) drive, POWER S/W (LED01) driving power, and
PULL-UPvoltage. RESET output of IC100 Pin 5, which changes from low to high at the power input, is connected to LCD MICOM RESET PIN (and resets LCD MICOM).
Samsung Electronics |
2-1 |
Reference Information
2. Camera power
Camera power block consists of IC120 (PWM IC MB3800), Q121 (INVERTER TR DTC144EU), Q122 (SWITCHING TR KSD1621), and rectifier circuit.
When CAM5V control pin of LCD MICOM 10PIN is high, it is converted at Q121 and IC 120. Pin 4 becomes low; then IC120 Pin 7 starts oscillating and the PWM output from IC120 Pin 5 switches Q122. Pin 6 generates the 15V output by a switching pulse and this output is rectified by D121, L123, C127, and C128 to generate 15V power for the drive of CCD (IC201) and V DRIVE IC (MN3112SA).
The pulse for -7V (which is generated at T121 pin 10), is rectified by D121, C129, L124, C130 and becomes -7V power for the drive of CCD and V DRIVE IC.
The pulse for 5V power, which is output from T121 pin 7, becomes CAMERA 5V power by D122, C133, L127, and C134. The 5V power is divided by D5V for the drive of IC204(MN5246) and IC202(MN3112SA) and A5V for the drive of IC203, IC205, and IC206 through L125.
3. SYS 5V
Using the same technique as with camera 5V (L141, IC140, Q142, and T141), the SYS 5V power drives IC301, IC302, IC303, IC304 and IC307, and is generated by SYS 5V CONT from the LCD micom.
EVER5V power is always output when battery and adapter are connected; SYS 5V power is output only when power is turned on. CAM power is output for 0.5 second (only during shot operation).
2-1-4 Camera |
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1/3" 35 |
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CDS out |
AGC IN |
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D7~D0 |
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D15~D0 |
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CCD |
Vout |
CDS |
Vout |
A/D |
Data 8 |
8-16 CONV. |
Data 16 |
DRAM |
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AGC |
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(8bit) |
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DRAM CTRL |
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4Mb |
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16 |
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V1~V4 |
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SMD |
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Address |
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H1 |
SHP |
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A9~A1 |
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VSUB |
H2 |
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LENS |
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V-Drive |
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Timing |
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D Data, DCLK |
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Gen |
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HD, VD |
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Camera |
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S/W |
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Ctrl |
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DSCP |
RISC Chip
1. Camera operation
Fig. 2-1
The image from the lens is converted to an electrical signal by the photoelectric conversion component, CCD (MN3776PE). Each pulse used to extract CCD signal is generated by the timing geneartor IC(MN5246), converted to actual driving voltage by V Drive IC(MN3112SA), and supplied to CCD. After noise elimination (CDS) and amplification (AGC) at analog process IC(NN2038FAQ), CCD output signal is converted to a digital signal by A/D converter. The 8-bit digital data is changed to 16-bit by DRAM control IC(SMA9606), and stored in the DRAM.
2-2 |
Samsung Electronics |
Reference Information
2. Lens
SDC-30/33 lens uses a fixed focus method, and can take a photograph clearly at over 1 meter distance (optimal quality is between 1.5 and 3 meters).
3. Color Filter |
R |
G |
R |
G |
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Color filter, which remove, the color information on CCD, adapts RGB method |
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G |
B |
G |
B |
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for best color characteristics and Bayer method for best. |
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4. CCD(MN3776PE) and V Driver(MN3112SA) |
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G |
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G |
B |
G |
B |
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CCD converts the optical image to an electrical signal and is similar to an |
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– |
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existing camcorder (except for the scanning method). The camcorder method |
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uses interlace scanning, which outputs a field image every 1/60 second. (First |
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field consists of odd lines, the second field consists of even line, and a complete |
picture consists of two fields. However, SDC-30/33 uses a the progressive
scanning method, which outputs a frame every 1/30 second (and has excellent vertical resolution).
The image is output at Pin 1 of CCD, and is input to Pin39 of analog signal process IC (IC203) through TR (Q201). V Driver IC (MN3112SA) mixes each CCD driving pulse from Timing Generator IC, and converts it to
the required voltage.
P W 16 
V O 1 1
(Bias) L G 2
V O 2 5
O D 4
<BLOCK>
Ø |
Ø |
Ø |
Ø |
V |
V |
V |
V |
1 |
3 |
2 |
4 |
15 |
13 |
14 |
12 |
V e r t i c a l
S h i f t
R e g i s t e r
Horizontal Shift Register 1
Horizontal Shift Register 2
3 |
6 |
8 |
7 |
Ø R |
O G |
Ø H 1 |
Ø H 2 |
Fig. 2-2
9 S U B
11 P T
10
S G
Samsung Electronics |
2-3 |
Reference Information
5. Timing Generator (MN5246)
A timing generator generates each clock, synchronized signal, and CCD driving pulse for the system. Also, it receives the shutter speed information for the photo-exposure control (from the microprocessor).
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CCD |
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CDS |
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Signal |
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Image signal |
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process |
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Ø V1 |
Ø V2 |
Ø V3 |
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Ø V4 |
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ØSUB |
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ØSG |
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H1 |
H2 |
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R |
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V1 |
V2 |
V3 V4 |
SUB |
CH1 |
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SG |
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DS1,DS2 |
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CLK |
CSYNC |
VDO,HDO |
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bias |
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MN5246
VDLIDE
2fck=24.5Mhz
Fig. 2-3
6. Analog processing IC (MN2038FAQ)
After eliminating the noise (CDS) from the CCD output signal (which is input to Pin39, to DS1/DS2 signal
of TG), Analog processing IC outputs it to Pin 46, and then it is input to pin 2 through C232 (for Row Clip and primary amplificationAGC). Then it is output to Pin 35 and Pin 37 of EVR (IC206), which is input to pin 36, which controls AGC. Pin 35 output signal is input to Pin 26 through C218, and is amplified second time at the main amplifier. The offset adjust (pin 16 input) is activated by EVR output signal (Pin 4) and the output (Pin 21) is sent to A/D converter.
Fig. 2-4 |
2-4 |
Samsung Electronics |
Reference Information
7. A/D converter (KAD0228) and DRAM Controller (SMA9606)
A/D converter converts the analog signal which is output from Analog processing IC to the 8-bit digital signal (24.54Mhz). DRAM Controller is synchronized with Vsync, converts the 8-bit data which is output from A/D converter to 16-bit data, and stores it in DRAM (controlled by the 32-bit microprocessor).
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Data Register |
SO |
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MODE |
& |
SCK |
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SIO |
SI |
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SCS |
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AE Data Detect. |
AD_IN(9:0) |
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D_OUT(15:0) |
2 & Knee, |
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– |
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8bit to 16bit Convert |
ADCK IN(12.27MHz) |
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TRI |
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STATE |
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WND1 OUT |
OUTPUT |
RAS– |
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WND2 OUT |
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(High Z |
CASU– |
DRAM |
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when |
CASL– |
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VD/HD |
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Address |
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Power Off) |
WR– |
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GEN |
EXT VD IN |
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Generator |
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OE– |
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EXT HD IN |
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A–OUT(9:1) |
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CLK IN(24.54MHz) |
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EOC– |
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H ADJ |
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V ADJ |
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R/B |
ADDR/DATA |
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– |
BUS |
OE |
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BREQ |
– |
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CONTROL |
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BACK |
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– |
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Fig. 2-5 |
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Samsung Electronics |
2-5 |
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