Samsung S6A0074 Datasheet
34COM/80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0074
INTRODUCTION
S6A0074 is a dot matrix LCD driver & controller LSI which is fabricated by low power CMOS technology. It can
display 1, 2, or 4 lines with 5 x 8 or 6 x 8 dots format.
FUNCTIONS
• Character type dot matrix LCD driver & controller
• Internal driver: 34 common and 80 segment signal output
• Easy interface with 4-bit or 8-bit MPU
• Clock synchronized serial Interface
• 5 x 8 dots matrix possible
• 6 x 8 dots matrix possible
• Bi-directional shift function
• All character reverse display
• Display shift per line
• Voltage converter for LCD drive voltage: 13V max (2 times/3 times)
• Various instruction functions
• Automatic power on reset
FEATURES
• Internal memory
- Character Generator ROM (CGROM): 9,600 bits (240 characters x 5 x 8 dot)
- Character Generator RAM (CGRAM): 64 x 8 bits (8 characters x 5 x 8 dot)
- Segment Icon RAM (SEGRAM): 16 x 8 bits (96 icons max.)
- Display Data RAM (DDRAM): 80 x 8 bits (80 characters max.)
• Low power operation
- Power supply voltage range: 2.7 - 5.5V (VDD)
- LCD Drive voltage range: 3.0 - 13.0V (VDD - V5)
• CMOS process
• Programmable duty cycle: 1/17, 1/33
• Internal oscillator with an external resistor
• Low power consumption
• Bare chip available
1
S6A0074 34COM/80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
PROGRAMMABLE DUTY CYCLES
5-dot Font Width
Display Line Duty Ratio Single Chip Operation
Numbers Displayable Characters Possible Icons
1 1/17 1 line of 32 characters 80
2 1/33 2 lines of 32 characters 80
4 1/33 4 lines of 16 characters 80
6-dot Font Width
Display Line Duty Ratio Single Chip Operation
Numbers Displayable Characters Possible Icons
1 1/17 1 line of 26 characters 78
2 1/33 2 lines of 26 characters 78
4 1/33 4 lines of 13 characters 78
2
34COM/80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0074
BLOCK DIAGRAM
OSC1 OSC2IE
RESET
RS/CS
E/SCLK
RW/SID
DB4-DB7
DB3-DB1
DB0-SOD
Power on Reset
(POR)
IM
Instruction
8
System
Interface
Serial
4-bit
8-bit
Input/
Output
Buffer
Register
(IR)
7
Data
8 8
Register
(DR)
8
Busy Flag
Oscillator
Instruction
Decoder
Address
Counter
7
3 7 8
Timing Generator
7
Display Data
RAM (DDRAM)
80 x 8-bit
8
8
80-bit
Shift
Register
34-bit
Shift
Register
80-bit
Latch
Circuit
Common
Driver
Segment
Driver
LCD Driver
Voltage Selector
COM0COM33
COM1COM80
V5OUT2
V5OUT3
VDD
GND(VSS)
Vci
C1
C2
Voltage Converter
Segment
RAM
(SEGRAM)
16 bytes
Character
Generator
RAM
(CGRAM)
64 bytes
5/6
Parallel/Serial Converter and
Smooth Scroll Circuit
Character
Generator
ROM
(CGROM)
9600 bits
5
Cursor and
Blink
Controller
V1 - V5
3
S6A0074 34COM/80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
DB0/SOD
PAD CONFIGURATION
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
1
2
3
4
5
6
7
8
9
X
(0, 0) Y
Chip size: 6450 x 4870
PAD size: 100
Unit : µm
S6A0074
×
100
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
4344454647484950515253545556575859606162636465666768697071
IE
OSC1
RESET
IM
SS1
V
RS/CS
RW/SID
DB1
E/SCLK
DB2
DB3
DB4
DB5
DB6
DB7
Vci
C2
C1
SS2
V
V5OUT2
V5V4V3V2V1
V5OUT3
DD
V
OSC2
4
34COM/80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0074
PAD CENTER COORDINATES
Table 1. Pad Location
Pad
No.
X Y X Y X Y
1 SEG56 -2475 -2269 32 COM15 1512 -2269
2 SEG57 -2350 -2269 33 COM16 1637 -2269
3 SEG58 -2225 -2269 34 COM25 1762 -2269
4 SEG59 -2100 -2269 35 COM26 1887 -2269
5 SEG60 -1975 -2269 36 COM27 2012 -2269
6 SEG61 -1850 -2269 37 COM28 2137 -2269
7 SEG62 -1725 -2269 38 COM29 2262 -2269
8 SEG63 -1600 -2269 39 COM30 2387 -2269
9 SEG64 -1475 -2269 40 COM31 2512 -2269
10 SEG65 -1350 -2269 41 COM32 2637 -2269 72 COM24
11 SEG66 -1225 -2269 42 COM33 2762 -2269 73 COM23
12 SEG67 -1100 -2269 43 VDD 3059 -1778 74 COM22
13 SEG68 -975 -2269 44 OSC2 3059 -1653 75 COM21
14 SEG69 -850 -2269 45 OSC1 3059 -1528 76 COM20
15 SEG70 -725 -2269 46 RESET 3059 -1403 77 COM19
16 SEG71 -600 -2269 47 IM 3059 -1278 78 COM18
17 SEG72 -425 -2269 48 IE 3059 -1153 79 COM17
18 SEG73 -350 -2269 49 VSS1 3059 -1028 80 COM8 1762 2269
19 SEG74 -225 -2269 50 RS/CS 3059 -903 81 COM7 1637 2269
20 SEG75 -100 -2269 51 RW/SID 3059 -778 82 COM6 1512 2269
21 SEG76 24 -2269 52 E/SCLK 3059 -653 83 COM5 1387 2269
22 SEG77 149 -2269 53 DB0/SOD 3059 -528 84 COM4 1262 2269
23 SEG78 274 -2269 54 DB1 3059 -403 85 COM3 1137 2269
24 SEG79 399 -2269 55 DB2 3059 -278 86 COM2 1012 2269
25 SEG80 524 -2269 56 DB3 3059 -153 87 COM1 887 2269
26 COM9 762 -2269 57 DB4 3059 -28 88 COM0 762 2269
27 COM10 887 -2269 58 DB5 3059 97 89 SEG1 524 2269
28 COM11 1012 -2269 59 DB6 3059 222 90 SEG2 399 2269
29 COM12 1137 -2269 60 DB7 3059 347 91 SEG3 274 2269
30 COM13 1262 -2269 61 Vci 3059 472 92 SEG4 149 2269
31 COM14 1387 -2269 62 C2 3059 597 93 SEG5 24 2269
Pad
Name
Coordinate Pad
No.
Pad
Name
Coordinate Pad
No.
63 C1 3059 722
64 VSS2 3059 847
65 V5OUT2 3059 972
66 V5OUT3 3059 1097
67 V5 3059 1222
68 V4 3059 1347
69 V3 3059 1472
70 V2 3059 1597
71 V1 3059 1722
Pad
Name
Coordinate
2762 2269
2637 2269
2512 2269
2387 2269
2262 2269
2137 2269
2012 2269
1887 2269
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S6A0074 34COM/80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
Table 1. Pad Location (Continued)
Pad
No.
X Y X Y X Y
94 SEG6 -100 2269 127
95 SEG7 -225 2269 128
96 SEG8 -350 2269 129
97 SEG9 -475 2269 130
98 SEG10 -600 2269 131
99 SEG11 -725 2269 132
100 SEG12 -850 2269 133
101 SEG13 -975 2269 134
102 SEG14 -1100 2269 135
103 SEG15 -1225 2269 136
104 SEG16 -1350 2269 137
105 SEG17 -1475 2269 138
106 SEG18 -1600 2269 139
107 SEG19 -1725 2269 140
108 SEG20 -1850 2269 141
109 SEG21 -1975 2269 142
110 SEG22 -2100 2269 143
111 SEG23 -2225 2269
112 SEG24 -2350 2269
113 SEG25 -2475 2269
114 SEG26 -3059 1812
115 SEG27 -3059 1687
116 SEG28 -3059 1562
117 SEG29 -3059 1437
118 SEG30 -3059 1312
119 SEG31 -3059 1187
120 SEG32 -3059 1062
121 SEG33 -3059 937
122 SEG34 -3059 812
123 SEG35 -3059 687
124 SEG36 -3059 562
125 SEG37 -3059 437
126 SEG38 -3059 312
Pad
Name
Coordinate Pad
No.
Pad
Name
SEG39 -3059
SEG40 -3059
SEG41 -3059
SEG42 -3059
SEG43 -3059
SEG44 -3059
SEG45 -3059
SEG46 -3059
SEG47 -3059
SEG48 -3059
SEG49 -3059 -1062
SEG50 -3059 -1187
SEG51 -3059 -1312
SEG52 -3059 -1437
SEG53 -3059 -1562
SEG54 -3059 -1687
SEG55 -3059 -1812
Coordinate Pad
No.
187
62
-62
-187
-312
-437
-562
-687
-812
-937
Pad
Name
Coordinate
6
34COM/80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0074
times), these pins must be connected to
PAD DESCRIPTION
Table 2. Pad Description
Pad (No) Input/
Output
VDD (43) - Power supply for logical circuit(+3V,+5V) Power supply
VSS1, VSS2
(49, 64)
V1 - V5
(71- 67)
Vci (61) Input Input voltage to the voltage converter
SEG1 – SEG80
(89-143, 1-25)
COM0 – COM33
(72-88, 26-42)
OSC1, OSC2
(45, 44)
C1, C2
(63, 62)
RESET (46) Input Reset pin Initialized to Low IE (48) Input Select pin of
V5OUT2 (65) Output Two times
V5OUT3 (66) Three times
IM (47) Input Interface mode
0V(GND)
Output Segment output Segment signal output for LCD drive. LCD
Output Common output Common signal output for LCD drive. LCD
Input
(OSC1),
Output
(OSC2)
Input External
Name Description Interface
Bias voltage level for LCD driving.
to generate LCD drive voltage
(Vci = 2.5 - 4.5V).
Oscillator When use internal oscillator, connect
capacitance input
instruction set
converter output
converter output
selection
external Rf resistor.
If external clock is used, connect it to
OSC1.
To use the voltage converter (2 times/3
the external capacitance.
When IE = "High", Instruction set is
selected as Table 6. When IE = "Low",
Instruction set is selected as Table 10.
The value of Vci is converted two
times. To use three times converter,
the same capacitance as that of C1-C2
should be connected here.
The value of Vci is converted three
times.
Select Interface mode with the MPU.
When IM = "Low" : Serial mode,
When IM = "High" : 4-bit/8-bit bus
mode.
resistor/oscillator
External
(OSC1)
External
capacitance
-
V5
capacitance
V5
-
7
S6A0074 34COM/80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
Table 2. Pad Description (Continued)
Pad (No) Input/
Name Description Interface
Output
RS/CS (50) Input Register elect/
Chip select
RW/SID (51) Input Read/Write/Serial
input data
E/SCLK (49) Input Read/Write
enable/Serial
clock
DB0/SOD (53) Input.-
Output/
DB1- DB3
(54 - 56)
DB4 - DB7
Output
Input.
Output
When 8-bit bus mode, used as high
Data bus 0 bit/
Serial output data
Data bus 1 - 7 When 8-bit bus mode, used as low
(57- 60)
When bus mode, used as register
selection input.
When RS/CS = "High", Data register is
selected.
When RS/CS = "Low", Instruction
register is selected.
When serial mode, used as chip
selection input.
When RS/CS = "Low", selected.
When RS/CS = "High", not selected.
(low access enable)
When bus mode, used as read/write
selection input.
When RW/SID = "High", read
operation.
When RW/SID = "Low", write
operation.
When serial mode, used for data input
pin.
When bus mode, used as read/write
enable signal. When serial mode, used
as serial clock input pin.
When 8-bit bus mode, used as lowest
bi-directional data bit. During 4-bit bus
mode, Open this pin. When serial
mode, used as serial data output pin. If
not in read operation, open this pin.
order bi-directional data bus.
During 4-bit bus mode or serial mode,
open these pins.
order bi-directional data bus. In case of
4-bit bus mode, used as both high and
low order.
DB7 used for busy flag output.
During serial mode, open these pins.
MPU
MPU
MPU
MPU
MPU
MPU
8
34COM/80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0074
FUNCTION DESCRIPTION
SYSTEM INTERFACE
This chip has all three kinds interface type with MPU: serial, 4-bit bus and 8-bit bus. Serial and bus (4-bit/8-bit) is
selected by IM input, and 4-bit bus and 8-bit bus is selected by DL bit in the instruction register. During read or
write operation, two 8-bit registers are used. one is data register (DR), the other is instruction register (IR). The
data register (DR) is used as temporary data storage place for being written into or read from
DDRAM/CGRAM/SEGRAM,
target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into
RAM, is done automatically.
So to speak, after MPU reads DR data, the data in the next DDRAM/CGRAM/SEGRAM address is transferred
into DR automatically. Also after MPU writes data to DR, the data in DR is transferred into
DDRAM/CGRAM/SEGRAM automatically.
The Instruction register (IR) is used only to store instruction code transferred from MPU. MPU cannot use it to
read instruction data. To select register, use RS/CS input pin in 4-bit/8-bit bus mode (IM = "High") or RS bit in
serial mode (IM = "Low").
RS R/W Operation
0 0 Instruction write operation (MPU writes Instruction code into IR)
0 1 Read busy flag (DB7) and address counter (DB0 - DB6)
1 0 Data write operation (MPU writes data into DR)
1 1 Data read operation (MPU reads data from DR)
BUSY FLAG (BF)
When BF = "High", it indicates that the internal operation is being processed. So during this time the next
instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation),
through DB7 Before executing the next instruction, be sure that BF is not High.
9
S6A0074 34COM/80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
COM16
COM16
COM16
DISPLAY DATA RAM (DDRAM)
DDRAM stores display data of maximum 80 x 8 bits (80 characters). DDRAM address is set in the address
counter (AC) as a hexadecimal number. (refer to Figure 1.)
MSB LSB
AC6 AC5 AC4 AC3 AC2 AC1 AC0
Figure 1. DDRAM Address
Display of 5-dot Font Width Character
5-dot 1-line Display
In case of 1-line display with 5-dot font, the address range of DDRAM is 00H-4FH (Refer to Figure 2).
Display Position
COM1
COM8
1 2 3 4 5
00 01 02 03 04
SEG1
6 7 8 9 10 11 12 13 14 15
05 06 07 08 09 0A 0E 0F1610 11 12
S6A0074
0B 0C 0D
17 18 19 20
SEG80SEG1
21 22 23 24
13 14 15 16
25 26
17 18
19 1A 1B 1C
DDRAM Address
S6A0074
27 28 29 30
1D 1E
31 32
SEG80
COM9
1F
COM1
COM8
COM1
COM8
1 2 3 4 5
01 02 03 04
1 2 3 4 5
01 02 03 04
4F 00 0F 10
6 7 8 9 10 11 12 13 14 15
05 06 07 08 09 0A 0E 0F
6 7 8 9 10 11 12 13 14 15
05 06 07 08 09 0A 0E
0B 0C 0D
0B 0C 0D
Figure 2. 1-line X 32 ch. Display
16
17 18 19 20
11 12
10 20
(After Shift Left)
16
17 18 19 20
(After Shift Right)
21 22 23 24
13 14 15 16
21 22 23 24
11 12
13 14 15 16
17 18
25 26
27 28 29 30
19 1A 1B 1C
25 26
27 28 29 30
17 18
19 1A 1B 1C
1D 1E
31 32
1F
31 32
1D 1E
COM9
COM9
10
34COM/80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0074
5-dot 2-line Display
In case of 2-line display with 5-dot font, the address range of DDRAM is 00H-27H, 40H-67H (refer to Figure 3).
Display Position
COM1
COM8
COM17
COM24
1 2 3 4 5
00 01 02 03 04
40 41 42 43 44
SEG1
6 7 8 9 10 11 12 13 14 15
05 06 07 08 09 0A 0E 0F1610 11 12
S6A0074
0B 0C 0D
4B 4C 4D45 46 47 48 49 4A 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F
17 18 19 20
SEG80 SEG1
21 22 23 24
13 14 15 16
25 26
17 18
19 1A 1B 1C
DDRAM Address
S6A0074
27 28 29 30
1D 1E
31 32
SEG80
1F
COM9
COM16
COM25
COM32
COM1
COM8
COM17
COM24
COM1
COM8
COM17
COM24
1 2 3 4 5
01 02 03 04
41 42 43 44 4B 4C 4D45 46 47 48 49 4A 4E 4F 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F50 60
1 2 3 4 5
01 02 03 04
27 00 0F 10
41 42 43 44 4B 4C 4D45 46 47 48 49 4A 4E 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E67 40 4F 50
6 7 8 9 10 11 12 13 14 15
05 06 07 08 09 0A 0E 0F
6 7 8 9 10 11 12 13 14 15
05 06 07 08 09 0A 0E
0B 0C 0D
0B 0C 0D
(After Shift Right)
16
17 18 19 20
11 12
10 20
(After Shift Left)
16
17 18 19 20
21 22 23 24
13 14 15 16
21 22 23 24
11 12
13 14 15 16
17 18
25 26
27 28 29 30
19 1A 1B 1C
25 26
27 28 29 30
17 18
19 1A 1B 1C
1D 1E
31 32
1F
31 32
1D 1E
Figure 3. 2-line X 32ch. Display (5-dot Font Width)
COM9
COM16
COM25
COM32
COM9
COM16
COM25
COM32
11
S6A0074 34COM/80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
5-dot 4-line Display
In case of 4-line display with 5-dot font, the address range of DDARM is 00H-13H, 20H-33H, 40H-53H, 60H-73H.
(refer to Figure 4)
COM1
COM8
COM9
COM16
COM17
COM24
COM25
COM32
COM1
COM8
COM9
COM16
COM17
COM24
COM25
COM32
COM1
COM8
COM9
COM16
COM17
COM24
COM25
COM32
1 2 3 4 5
00 01 02 03 04
21 22 23 24 25 26 27 28 2F2D 2E2B 2C2A2920
40 41 42 43 44
61 62 63 64 65 66 67 68 6F6D 6E6B 6C6A6960
SEG1
1 2 3 4 5
01 02 03 04
21 22 23 24 25 26 27 28 2F 302D 2E2B 2C2A29
41 42 43 44
61 62 63 64 65 66 67 68 6F 70
1 2 3 4 5
01 02 03 04
00
13
33 20
21 22 23 24 25 26 27 28
41 42 43 44
61 62 63 64 65 66 67 68
6 7 8 9 10 11 12 13 14 15
05 06 07 08 09 0A 0E 0F
S6A0074
6 7 8 9 10 11 12 13 14 15
05 06 07 08 09 0A 0E 0F
(After Shift Left)
6 7 8 9 10 11 12 13 14 15
05 06 07 08 09 0A 0E
(After Shift Right)
0B 0C 0D
4B 4C 4D45 46 47 48 49 4A 4E 4F
SEG80
0B 0C 0D 10
4B 4C 4D 5045 46 47 48 49 4A 4E 4F
6D 6E6B 6C6A69
0B 0C 0D
2D 2E2B 2C2A29
4B 4C 4D45 46 47 48 49 4A 4E53 40
6D 6E6B 6C6A6973 60
16
16
16
Display Position
DDRAM Address
Figure 4. 4-line X 16ch. Display (5-dot Font Width)
12
34COM/80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0074
Display of 6-dot Font Width Character
When this device is used in 6-dot font width mode, SEG79 and SEG80 must be open
6-dot 1-line Display
In case of 1-line display with 6-dot font, the address range of DDRAM is 00H-4FH. (refer to Figure 5)
Display Position
COM1
COM8
1 2 3 4 5
00 01 02 03 04
SEG1
6 7 8 9 10 11 12 13
05 06 07 08 09 0A 10 11 12
S6A0074 S6A0074
0B 0C
SEG78 SEG1
14 15 16
0D 0E 0F
17 18 19 20
13 14 15 16
DDRAM Address
21 22 23 24
17 18
25
SEG78
26
19
COM9
COM16
COM1
COM8
COM1
COM8
1 2 3 4 5
01 02 03 04
1 2 3 4 5
4F 00 0F 10
01 02 03 04
6 7 8 9 10 11 12 13
05 06 07 08 09 0A 11 12
6 7 8 9 10 11 12 13
05 06 07 08 09 0A 11 12
0B 0C 0D
(After Shift Left)
(After Shift Right)
0B
14 15 16
0E 0F
14 15 16
0C 0D
17 18 19 20
10
17 18 19 20
0E
Figure 5. 1-line X 26ch. Display
21 22 23 24
13 14 15 16
21 22 23 24
13 14 15 16
17 18
25 26
19 1A
25 26
17 18
COM9
COM16
COM9
COM16
13
S6A0074 34COM/80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
6-dot 2-line Display
In case of 2-line display with 6-dot font, the address range of DDRAM is 00H-27H, 40H-67H (refer to Figure 6).
Display Position
COM1
COM8
COM17
COM24
1 2 3 4 5
00 01 02 03 04
40 41 42 43 44
SEG1
6 7 8 9 10 11 12 13 14 15
05 06 07 08 09 0A 0E 0F1610 11 12
S6A0074 S6A0074
0B 0C 0D
4B 4C 4D45 46 47 48 49 4A 4E 4F 50 51 52 53 54 55 56 57 58 59
SEG78 SEG1
17 18 19 20
13 14 15 16
DDRAM Address
21 22 23 24
25 26
17 18
SEG78
19
COM9
COM16
COM25
COM32
COM1
COM8
COM17
COM24
COM1
COM8
COM17
COM24
1 2 3 4 5
01 02 03 04
41 42 43 44 4B 4C 4D45 46 47 48 49 4A 4E 4F 51 52 53 54 55 56 57 58 59 5A50
1 2 3 4 5
27 00 0F 10
01 02 03 04
41 42 43 44 4B 4C 4D45 46 47 48 49 4A 4E 51 52 53 54 55 56 57 5867 40 4F 50
6 7 8 9 10 11 12 13 14 15
05 06 07 08 09 0A 0E 0F
6 7 8 9 10 11 12 13 14 15
05 06 07 08 09 0A 0E
0B 0C 0D
(After Shift Left)
0B 0C 0D
(After Shift Right)
16
17 18 19 20
11 12
10
16
17 18 19 20
Figure 6. 2-line X 26h. Display (6-dot Font Width)
21 22 23 24
13 14 15 16
21 22 23 24
11 12
13 14 15 16
17 18
25 26
19 1A
25 26
17 18
COM9
COM16
COM25
COM32
COM9
COM16
COM25
COM32
14
34COM/80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0074
6-dot 4-line Display
In case of 4-line display with 6-dot font, the address range of DDARM is 00H-13H, 20H-33H, 40H-53H, 60H-73H
(refer to Figure 7).
COM1
COM8
COM9
COM16
COM17
COM24
COM25
COM32
COM1
COM8
COM9
COM16
COM17
COM24
COM25
COM32
COM1
COM8
COM9
COM16
COM17
COM24
COM25
COM32
1 2 3 4 5
00 01 02 03 04
21 22 23 24 25 26 27 28 2B 2C2A2920
40 41 42 43 44
61 62 63 64 65 66 67 68 6B 6C6A6960
SEG1
1 2 3 4 5
01 02 03 04
21 22 23 24 25 26 27 28 2D2B 2C2A29
41 42 43 44
61 62 63 64 65 66 67 68
1 2 3 4 5
01 02 03 04
00
13
33 20
21 22 23 24 25 26 27 28
41 42 43 44
61 62 63 64 65 66 67 68
6 7 8 9 10 11 12 13
05 06 07 08 09 0A
S6A0074
6 7 8 9 10 11 12 13
05 06 07 08 09 0A
(After Shift Left)
6 7 8 9 10 11 12 13
05 06 07 08 09 0A
(After Shift Right)
0B 0C
4B 4C45 46 47 48 49 4A
SEG78
0B 0C 0D
4B 4C 4D45 46 47 48 49 4A
6D6B 6C6A69
0B
2B2A29
4B45 46 47 48 49 4A53 40
6B6A6973 60
Display Position
DDRAM Address
Figure 7. 4-line X 13ch. Display (6-dot Font Width)
15
S6A0074 34COM/80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
TIMING GENERATION CIRCUIT
Timing generation circuit generates clock signals for the internal operations.
ADDRESS COUNTER (AC)
Address Counter (AC) stores DDRAM/CGRAM/SEGRAM address, transferred from IR.
After writing into (reading from) DDRAM/CGRAM/SEGRAM, AC is automatically increased (decreased) by 1.
When RS = "Low" and R/W = "High", AC can be read through DB0-DB6
CURSOR/BLINK CONTROL CIRCUIT
It controls cursor/blink ON/OFF and black/white inversion at cursor position.
LCD DRIVER CIRCUIT
LCD Driver circuit has 34 common and 80 segment signals for LCD driving. Data from
SEGRAM/CGRAM/CGROM is transferred to 80-bit segment latch serially, and then it is stored to 80-bit shift
latch. When each com is selected by 34-bit common register, segment data also output through segment driver
from 80-bit segment latch. In case of 1-line display mode, COM0-COM17 have 1/17 duty, and in 2-line or 4-line
mode, COM0-COM33 have 1/33 duty ratio.
16
34COM/80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0074
CGROM (CHARACTER GENERATOR ROM)
CGROM has 5 X 8-dot 240 character pattern.
CGRAM (CHARACTER GENERATOR RAM)
CGRAM has up to 5 × 8 dots 8 characters. By writing font data to CGRAM, user defined character can be used
(refer to Table 4).
5 × 8 dots Character Pattern
Table 4. Relationship Between Character Code (DDRAM) and Character Pattern (CGRAM)
Character Code (DDRAM data) CGRAM Address CGRAM Data
D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 P7 P6 P5 P4 P3 P2 P1 P0
0 0 x0 0 0 0 0 0 0 0 0 0
0 0
0 0
.
.
.
.
.
.
.
0 0 0 x0 1 1 1 1 1 1 0 0 0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
0
1 1
0 0
1
0
1 1
1 1
1 1 1
.
.
0 0
0 0
1
0
1 1
0 0
1
0
1 1
1 1
1 1 1
B1 B0 x 0 0
1
.
.
.
.
0
1
0
.
B1 B0 x
.
.
.
.
.
1 1 10
1
0 0 0
1
0 0 0
1
1 1 1 1
1
0 0 0
1
0 0 0
1
0 0 0
0
0 0 0 0
.
.
01 10 0
1
0 0 0
1
0 0 0
1
1 1 1 1
1
0 0 0
1
0 0 0
1
0 0 0
0
0 0 0 0
Pattern
Number
Pattern 1
1
1
1
1
1
.
.
Pattern 8
1
1
1
1
1
17
S6A0074 34COM/80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
6 x 8 dots Character Pattern
Character Code (DDRAM data) CGRAM Address CGRAM Data
D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 P7 P6 P5 P4 P3 P2 P1 P0
0 0 x0 0 0 0 0 0 0 0 0 0
0 0
0 0
.
.
.
.
.
.
.
0 0 0 x0 1 1 1 1 1 1 0 0 0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
0
1 1
0 0
1
0
1 1
1 1
1 1 1
.
.
0 0
0 0
1
0
1 1
0 0
1
0
1 1
1 1
1 1 1
B1 B0 0 0 0
1
0
B1 B0 0
1
0
0
0
.
0
.
.
0
.
0
.
0
0
0
0
.
0
.
.
0
.
0
.
0
0
1 1 10
1
0 0 0
1
0 0 0
1
1 1 1 1
1
0 0 0
1
0 0 0
1
0 0 0
0
0 0 0 0
.
.
01 10 0
1
0 0 0
1
0 0 0
1
1 1 1 1
1
0 0 0
1
0 0 0
1
0 0 0
0
0 0 0 0
Pattern
Number
Pattern 1
1
1
1
1
1
.
.
Pattern 8
1
1
1
1
1
1. When BE (Blink Enable bit) = "High", blink is controlled by B1 and B0 bit.
In case of 5-dot font width, when B1 = "1", enabled dots of P0-P4 will blink, and when B1 = "0" and B0 = "1", enabled
dots in P4 will blink, when B1 = "0" and B0 = "0", blink will not happen.
In case of 6-dot font width, when B1 = "1", enabled dots of P0-P5 will blink, and when B1 = "0" and B0 = "1", enabled
dots of P5 will blink, when B1 = "0" and B0 = "0", blink will not happen.
2. "X": Don't care
18
34COM/80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0074
SEGRAM (SEGMENT ICON RAM)
SEGRAM has segment control data and segment pattern data. During 1-line display mode, COM0 (COM17)
makes the data of SEGRAM enable to display icons. When used in 2/4-line display mode COM0 (COM33) does
that. Its higher 2-bits are blinking control data, and lower 6-bits are pattern data (refer to Table 5 and Figure 8).
Table 5. Relationship between SEGRAM Address and Display Pattern
SEGRAM Address
5-dot Font Width 6-dot Font Width
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 B1 B0 X S1 S2 S3 S4 S5 B1 B0 S1 S2 S3 S4 S5 S6
0 0 0 1 B1 B0 X S6 S7 S8 S9 S10 B1 B0 S7 S8 S9 S10 S11 S12
0 0 1 0 B1 B0 X S11 S12 S13 S14 S15 B1 B0 S13 S14 S15 S16 S17 S18
0 0 1 1 B1 B0 X S16 S17 S18 S19 S20 B1 B0 S19 S20 S21 S22 S23 S24
0 1 0 0 B1 B0 X S21 S22 S23 S24 S25 B1 B0 S25 S26 S27 S28 S29 S30
0 1 0 1 B1 B0 X S26 S27 S28 S29 S30 B1 B0 S31 S32 S33 S34 S35 S36
0 1 1 0 B1 B0 X S31 S32 S33 S34 S35 B1 B0 S37 S38 S39 S40 S41 S42
0 1 1 1 B1 B0 X S36 S37 S38 S39 S40 B1 B0 S43 S44 S45 S46 S47 S48
1 0 0 0 B1 B0 X S41 S42 S43 S44 S45 B1 B0 S49 S50 S51 S52 S53 S54
1 0 0 1 B1 B0 X S46 S47 S48 S49 S50 B1 B0 S55 S56 S57 S58 S59 S60
1 0 1 0 B1 B0 X S51 S52 S53 S54 S55 B1 B0 S61 S62 S63 S64 S65 S66
1 0 1 1 B1 B0 X S56 S57 S58 S59 S60 B1 B0 S67 S68 S69 S70 S71 S72
1 1 0 0 B1 B0 X S61 S62 S63 S64 S65 B1 B0 S73 S74 S75 S76 S77 S78
1 1 0 1 B1 B0 X S66 S67 S68 S69 S70 - - - - - - - 1 1 1 0 B1 B0 X S71 S72 S73 S74 S75 - - - - - - - 1 1 1 1 B1 B0 X S76 S77 S78 S79 S80 - - - - - - - -
SEGRAM Data Display Pattern
1. B1, B0: Blinking control bit
Control Bit Blinking Port
BE B1 B0 5-dot font width 6-dot font width
0 X X No blink No blink
1 0 0 No blink No blink
1 0 1 D4 D5
1 1 X D4 - D0 D5 - D0
2. S1-S80: Icon pattern ON/OFF in 5-dot font width
S1-S78: Icon pattern ON/OFF in 6-dot font width
3. "X": Don't care
19
S6A0074 34COM/80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
SEG80
SEG10
SEG11
SEG69
SEG70
SEG71
SEG72
SEG74
SEG75
SEG76
SEG77
SEG12
SEG73
SEG78
SEG67
SEG68
5-Dot Font Width (FW = 0)
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
6-Dot Font Width (FW = 1)
S1 S2 S3 S4 S5 S7 S8 S9 S10 S11
S6
SEG10
S12
. . .
S71 S72 S73 S74 S75
SEG71
SEG72
SEG73
SEG74
S67 S68 S71 S72 S74 S75 S76 S77
S69 S70
S76 S77 S78 S79 S80
SEG76
SEG75
S73
SEG77
SEG78
SEG79
S78
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
. . .. . .
Figure 8. Relationship between SEGRAM and Segment Display
20
34COM/80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0074
INSTRUCTION DESCRIPTION
OUTLINE
To overcome the speed difference between internal clock of S6A0074 and MPU clock, S6A0074 performs
internal operation by storing control information to IR or DR. The internal operation is determined according to the
signal from MPU, composed of read/write and data bus. (refer to Table 6/10)
Instruction can be divided largely four kinds;
• S6A0074 function set instructions (set display methods, set data length, etc.)
• Address set instructions to internal RAM
• Data transfer instructions with internal RAM
• Others
The address of internal RAM is automatically increased or decreased by 1.
When IE = "High", S6A0074 is operated according to Instruction Set 1(Table 6) and
when IE = "Low", S6A0074 is operated according to Instruction Set 2 (Table 10).
NOTE: During internal operation, Busy Flag (DB7) is read high. Busy Flag check must be proceeded the next instruction.
Busy flag check must be proceeded the next instruction.
When an MPU program with Busy Flag (DB7) checking is made, 1/2 Fosc (is necessary) for executing the next
instruction by the falling edge of the “E” signal after the Busy Flag (DB7) goes to “Low”.
21
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