34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0073
INTRODUCTION
S6A0073 is a dot matrix LCD driver & controller LSI which is fabricated by low power CMOS technology. It can
display 1, 2 or 4 lines with 5 × 8 or 6 × 8 dots format.
FUNCTIONS
• Character type dot matrix LCD driver & controller
• Internal driver : 34 common and 60 segment signal output
• Easy interface with 4-bit or 8-bit MPU
• Clock synchronized serial Interface
• 5 × 8 or 6 × 8 dots matrix possible
• Extension driver interface possible
• Bi-directional shift function
• All character reverse display
• Display shift per line
• Voltage converter for LCD drive voltage : 13V max (2 times / 3 times)
• Various instruction functions
• Automatic power on reset
FEATURES
• Internal Memory
- Character Generator ROM (CGROM) : 9,600 bits (240 characters × 5 × 8 dot)
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0073
PIN DESCRIPTION
Pin (No) I/O Name Description Interface
VDD(35) for logical circuit (+3V, +5V)
VSS1, VSS2
(46, 61)
V1-V5 (68 - 64)
Vci (58) I Input voltage to the voltage converter to
SEG1 - SEG60
(86 -128, 1- 17)
COM0 - COM33
(85 - 69, 18 - 34)
OSC1, OSC2
(37, 36)
CLK1, CLK2
(38, 39)
C1, C2
(60, 59)
M (41) O Alternated signal
D(40) O Display data
EXT(44) I Extension driver
RESET (42) I Reset pin Initialized to Low -
IE (45) I Selection pin of
- Power supply 0V (GND) Power Supply
Bias voltage level for LCD driving
generate LCD drive voltage
(Vci = 1.0 to 4.5V).
O Segment output Segment signal output for LCD drive. LCD
O Common output Common signal output for LCD drive LCD
I(OSC1),
O(OSC2)
Oscillator When using internal oscillator, connect
external Rf resistor.
If external clock is used, connect it to
External
resistor/oscilla
tor (OSC1)
OSC1.
O Latch (CLK1)/
Shift (CLK2) clock
I External
capacitance input
When EXT = "High", each outputs latch
clock and shift clock for extension driver.
To use the voltage converter (2 times /3
times), these pins must be connected to
Extension
External
capacitance
the external capacitance.
for LCD driver
output
interface
When EXT = "High", outputs the
alternating signal to convert LCD driver
waveform to AC for Extension driver.
When EXT = "High", outputs extension
driver data (the 61th dot's data)
Extension
Extension
When EXT = "High", makes extension
control signal
driver control signal enable, When EXT
= "Low", suppress extra current
consumption and CLK1,CLK2,M,D
should be open.
When IE = "High", instruction set is
instruction set.
selected as Table 6.
When IE = "Low", instruction set is
selected as Table 10.
driver
driver
driver
-
-
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S6A0073 34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
PIN DESCRIPTION (continued)
Pin(No) I/O Name Description Interface
V5OUT2 (62) O Two times
converter output
V5OUT3 (63) Three times
converter output
IM (43) I Interface mode
selection
RS/CS (47) I Register select
/Chip select
RW/SID (48) I Read, write
/Serial input data
E/SCLK (49) I Read, write enable
/Serial clock
DB0/SOD (50) I/O, O Data bus 0 bit
/Serial output data
DB1 - DB3
I/O
Data bus 1- 7
(51 - 53)
DB4 - DB7
In 8-bit bus mode, used as high order
(54 - 57)
The value of Vci is converted two times.
To use three times converter, the same
capacitance as that of C1-C2 should be
connected here.
The value of Vci is converted three
times.
Select Interface mode with the MPU.
When IM = "Low" : serial mode,
When IM = "High" : 4-bit/8-bit bus mode.
When bus mode, used as register
selection input. When RS/CS = "High",
Data register is selected. When RS/CS =
"Low", Instruction register is selected.
In serial mode, used as chip selection
input. When RS/CS = "Low", selected.
When RS/CS = "High", not selected.(Low
access enable)
In bus mode, used as read/write
selection input.
When RW/SID = "High", read operation
When RW/SID = "Low", write operation.
In serial mode, used for data input pin.
When bus mode, used as read, write
enable signal.
When serial mode, used as serial clock
input pin.
In 8-bit bus mode, used as lowest
bidirectional data bit. During 4-bit bus
mode, Open this pin.
In serial mode, used as serial data output
pin. If not in read operation, open this
pin.
In 8-bit bus mode, used as low order
bidirectional data bus.
During 4-bit bus mode or serial mode,
open these pins.
bidirectional data bus. In case of 4-bit
bus mode, used as both high and low
order.
DB7 used for Busy Flag output.
During serial mode, open these pins.
V5 /
capacitance
V5
-
MPU
MPU
MPU
MPU
MPU
MPU
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34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0073
FUNCTION DESCRIPTION
System Interface
This chip has all three kinds of interface type with MPU : serial, 4-bit bus and 8-bit bus. Serial and bus(4-bit/8-bit)
are selected by IM input, and 4-bit bus and 8-bit bus are selected by DL bit in the instruction register. During read
or write operation, two 8-bit registers are used. one is data register (DR), the other is instruction register(IR). The
data register(DR) is used as temporary data storage place for being written into or read from
DDRAM/CGRAM/SEGRAM, target RAM is selected by RAM address setting instruction. Each internal operation,
reading from or writing into RAM, is done automatically. Hence, after MPU reads DR data, the data in the next
DDRAM/CGRAM/SEGRAM address is transferred into DR automatically. Also after MPU writes data to DR, the
data in DR is transferred into DDRAM/CGRAM/SEGRAM automatically. The Instruction register(IR) is used only
to store instruction code transferred from MPU. MPU cannot use it to read instruction data. To select register, use
RS/CS input pin in 4-bit/8-bit bus mode(IM = "High") or RS bit in serial mode(IM = "Low").
Table 2. Various Kinds of Operations according to RS and R/W Bits
RS R/W Operation
L L Instruction Write operation (MPU writes Instruction code into IR)
L H Read Busy flag(DB7) and address counter (DB0 – DB6)
H L Data Write operation (MPU writes data into DR)
H H Data Read operation (MPU reads data from DR)
Busy Flag (BF)
When BF = "High", it indicates that the internal operation is being processed. So during this time the next
instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation),
through DB7. Before executing the next instruction, be sure that BF is not High.
Display Data RAM (DDRAM)
DDRAM stores display data of maximum 80 × 8 bits (80 characters). DDRAM address is set in the address
counter (AC) as a hexadecimal number. (refer to Figure 1.)
MSBLSB
AC6
AC5AC4AC3AC2AC1AC0
Figure 1. DDRAM Address
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S6A0073 34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
1) Display of 5-dot Font Width Character
(1) 5-dot 1-line Display
In case of 1 line display with 5-dot font, the address range of DDRAM is 00H - 4FH (refer to Figure 2). When EXT
= "High", extension driver will be used. Figure 3 shows the example that 40 segment extension driver is added
Display position
1
COM1
COM8
COM1
COM8
COM1
COM8
2345678
00
01 02 03 04 05 06 07
SEG1S6A0073SEG60
1
2345678109
01 02 03 04 05 06 07
1
2345678089
00
4F
01 02 03 04 05 06 07
08
10 11 1213 14 15 161017
08909 0A 0B0C 0D 0E 0F
SEG1S6A0073SEG60
10 11 1213 14 15 161817
09 0A 0B 0C0D 0E 0F
(After Shift Left)
10 11 1213 14 15 161017
09 0A0B 0C 0D 0E 0F
(After Shift Right)
18 19 20 21 22 23 24
11 12 13 14 15 16 17
DDRAM Address
18 19 20 21 22 23 24
11 12 13 14 15 16 17
18 19 20 21 22 23 24
11 12 13 14 15 16
COM9
COM16
COM9
COM16
COM9
COM16
Figure 2. 1-line × 24ch. Display (5-dot font width)
1
COM1
COM8
COM1
COM8
COM1
COM8
2 3 4 5 6 7 8089
00
01 02 03 04 05 06 07
SEG1S6A0073SEG60SEG40
1
2 3 4 5 6 7 8089
01 02 03 04 05 06 07
1
2 3 4 5 6 7 8089
00
01 02 03 04 05 06 07
4F
10 11 1213 14 15 161017
09 0A 0B0C 0D 0E 0F
SEG1S6A0073SEG60SEG1
10 11 1213 14 15 161017
09 0A 0B 0C0D 0E 0F
(After Shift Left)
10 11 1213 14 15 161017
09 0A0B 0C 0D 0E 0F
(After Shift Right)
18 19 20 21 22 23 24
11 12 13 14 15 16 17
18 19 20 21 22 23 24
11 12 13 14 15 16 17
18 19 20 21 22 23 24
11 12 13 14 15 1617
25 26 27 28 29 30 31 32
18 19 1A 1B 1C 1D 1E 1F
Extension Driver (40SEG)
25 26 27 28 29 30 31 32
1819 1A 1B 1C 1D 1E 1F
25 26 27 28 29 30 31 32
18 19 1A 1B 1C 1D 1E
Figure 3. 1-line × 32ch. Display with 40 SEG. extension driver (5-dot font width)
COM9
COM16
COM9
20
COM16
COM9
COM16
12
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0073
(2) 5-dot 2-line Display
In case of 2 line display with 5-dot font, the address range of DDRAM is 00H - 27H,40H - 67H (refer to Figure 4).
When EXT = "High", extension driver will be used. Figure 5 shows the example that 40 segment extension driver
is added.
Figure 11. 2-line × 26ch. Display with 40 SEG. Extension Driver (6-dot Font Width)
18 19
25 26
18 19
25 26
1A
5A
COM9
COM16
COM25
COM32
COM9
COM16
COM25
COM32
COM9
COM16
COM25
COM32
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S6A0073 34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
(3) 6-dot 4-line Display
In case of 4 line display with 6-dot font, the address range of DDARM is 00H-13H, 20H-33H, 40H-53H, 60H-73H
(refer to Figure 12). When EXT = "High", extension driver will be used. Figure 13 shows the example that 40
segment extension driver is added.
COM1
COM8
COM9
COM16
COM17
COM24
COM25
COM32
COM1
COM8
COM9
COM16
COM17
COM24
COM25
COM32
COM1
COM8
COM9
COM16
COM17
COM24
COM25
COM32
1
23456780890910
00
01 02 03 04 05 06 07
20 21 22 23 24 25 26 27 28 29
40 41 42 43 44 45 46 47 48 49
60 61 62 63 64 65 66 67 68 69
SEG60S6A0073SEG1
1
2345678089
01 02 03 04 05 06 07
21 22 23 24 25 26 27 28 29 2A
41 42 43 44 45 46 47 48 49 4A
61 62 63 64 65 66 67 68 69 6A
(After Shift Left)
1
2345678089 10
00
13
33
53
73
01 02 03 04 05 06 07
20 21 22 23 24 25 26 27 28
40 41 42 43 44 45 46 47 48
60 61 62 63 64 65 66 67 68
(After Shift Right)
10
09 0A
Display position
DDRAM Address
Figure 12. 4-line × 10 ch. Display (6-dot Font Width)
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34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0073
COM1
COM8
COM9
COM16
COM17
COM24
COM25
COM32
COM1
COM8
COM16
COM17
COM24
COM25
COM32
COM1
COM8
COM9
COM16
COM17
COM24
COM25
COM32
1
2345678089
00
01 02 03 04 05 06 07
20 21 22 23 24 25 26 27 28 292A 2B
40 41 42 43 44 45 46 47 48 494A 4B
60 61 62 63 64 65 66 67 68 696A 6B
1
2345678089
01 02 03 04 05 06 07
21 22 23 24 25 26 27 28 29 2A
41 42 43 44 45 46 47 48 49 4A
61 62 63 64 65 66 67 68 69 6A
(After Shift Left)
1
234567808910
00
13
33
53
73
01 02 03 04 05 06 07
20 21 22 23 24 25 26 27 28
40 41 42 43 44 45 46 47 48
60 61 62 63 64 65 66 67 68
(After Shift Right)
1011 12
090A 0B
SEG60S6A0073SEG1
10
09 0A
SEG1SEG36
11 12
0B
0C 0D 0E 0F
2B
2C 2D 2E 2F
4B
4C 4D 4E 4F
6B
6C 6D 6E 6F
11 12
0A 0B
09
2A 2B
29
4A 4B
49
6A 6B
69
13 14 15 16
0C 0D 0E 0F
2C 2D 2E 2F
4C 4D 4E 4F
6C 6D 6E 6F
Extension Driver (40SEG)
13 14 15 16
10
30
50
70
13 14 15 16
0C 0D 0E
2C 2D 2E
4C 4D 4E
6C 6D 6E
Display position
DDRAM Address
Figure 13. 4-line × 16ch. Display with 40 SEG. Driver (6-dot Font Width)
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S6A0073 34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
Timing Generation Circuit
Timing generation circuit generates clock signals for the internal operations.
Address Counter (AC)
Address Counter(AC) stores DDRAM/CGRAM/SEGRAM address, transferred from IR. After writing into (reading
from) DDRAM/CGRAM/SEGRAM, AC is automatically increased (decreased) by 1. When RS = "Low" and R/W =
"High", AC can be read through DB0-DB6 ports.
Cursor/Blink Control Circuit
It controls cursor/blink ON/OFF and black/white inversion at cursor position.
LCD Driver Circuit
LCD Driver circuit has 34 common and 60 segment signals for LCD driving. Data from
SEGRAM/CGRAM/CGROM is transferred to 60-bit segment latch serially, which is then stored to a 60-bit shift
latch. When each com is selected by 34-bit common register, segment data also output through segment driver
from 100-bit segment latch. In case of 1-line display mode, COM0 - COM17 have a 1/17 duty ratio, and in 2-line
or 4-line mode, COM0-COM33 have a 1/33 duty ratio.
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34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0073
CGROM (Character Generator ROM)
CGROM has 5 × 8-dot 240 character pattern.
CGRAM (Character Generator RAM)
CGRAM has up to 5 × 8-dot 8 characters. By writing font data to CGRAM, user defined character can be used
(refer to Table 4).
Table 4. Relationship between Character Code (DDRAM) and Character Pattern (CGRAM)
1) 5 × 8 dots Character Pattern
Character Code (DDRAM data)CGRAM AddressCGRAM Data
1. When Be(Blink Enable bit) = "High", blink is controlled by B1 and B0 bit. In case of 5-dot font width, when B1 = "1",
enabled dots of P0 - P4 will blink, and when B1 = "0" and B0 = "1", enabled dots in P4 will blink, when B1 = "0" and
B0 = “0", blink will not happen.
In case of 6-dot font width, when B1 = "1", enabled dots of P0-P5 will blink, and
when B1 = "0" and B0 = "1", enabled dots of P5 will blink, when B1 = "0" and
B0 = "0", blink will not happen.
2. "X" : don't care
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34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0073
SEGRAM (Segment Icon RAM)
SEGRAM has segment control data and segment pattern data. During 1-line display mode, COM0(COM17)
makes the data of SEGRAM enable to display icons. When used in 2/4-line display mode COM0(COM33) does
that. Its higher 2-bits are blinking control data, and lower 6-bits are pattern data (refer to Table 5 and Figure 8).
Table 5. Relationship between SEGRAM Address and Display Pattern