Samsung S6A0071 Datasheet
32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0071
INTRODUCTION
The S6A0071 is a dot matrix LCD controller & driver LSI which is fabricated by low power CMOS technology. It
can display 1 line × 24 characters or 2 line × 24 characters with 5 × 7 dots format.
FUNCTION
• Character type dot matrix single chip LCD controller & driver
• Internal driver: 32 common and 60 segment signal output
• Easy interface with 4-bit or 8-bit MPU
• Display character pattern: 5 × 7 dots format (240 kinds)
• The Special character pattern is programmable by character generator RAM directly.
• A customer character pattern is programmable by mask option.
• Various instruction functions
• Built-in automatic power on reset
• Driving method is B-type (frame inversion)
FEATURES
Internal Memory
• Character Generator ROM (CGROM): 8,400 bits (240 characters × 5 × 7 dots)
• Character Generator RAM (CGRAM): 64 × 8 bits (8 characters × 5 × 8 dots)
• Display Data RAM (DDRAM): 80 × 8 bits ( 80 characters max.)
Low Power Operation
• Power supply voltage range (VDD): 2.4 to 5.5V
• LCD drive voltage range (VDD - V5): 3.0 to 12.0V
Voltage doubler generates about double from signals power supply
On chip generation of LCD supply voltage from voltage doubler (external supply also possible)
Programmable duty cycle
• 1/16 duty: 1 line × 5 × 7 dots + cursor × 24 characters
• 1/32 duty: 2 lines × 5 × 7 dots + cursor × 24 characters
Internal oscillator with an external resistor
118 TCP or bare chip available
1
S6A0071 32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
BLOCK DIAGRAM
VDD
GND
R/W
RS
E
DB0-DB3
DB4-DB7
OSC1
OSC2
V1
V2
V3
V4
V5
Input/
Output
Buffer
Timing
Generator
Circuit
Busy
Flag
8
8
Data
Register
(DR)
Instruction
Register
(IR)
Parallel/Serial
Data Conversion Circuit
55
Character
Generator
ROM
(CGROM)
8400 bits
8
Character
Generator
RAM
(CGRAM)
512 bits
8
8
8
Instruction
7
Decoder
7
7
Address
Counter (AC)
Voltage Doubler
Vci C1 C2 V5out T1 T2
Cursor
& Blink
Controller
Circuit
8
Display
Data RAM
(DDRAM)
640 bits
60-bit
Shift
Register
32-bit
Shift
Register
60-bit
Latch
Circuit
Common
Driver
Segment
Driver
32
COM1COM32
60
SEG1SEG60
D
2
32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0071
PAD DIAGRAM
118 SEG44
117 SEG43
116 SEG42
115 SEG41
114 SEG40
113 SEG39
112 SEG38
111 SEG37
110 SEG36
109 SEG35
108 SEG34
107 SEG33
106 SEG32
105 SEG31
104 SEG30
103 SEG29
102 SEG28
101 SEG27
100 SEG26
99 SEG25
98 SEG24
97 SEG23
96 SEG22
95 SEG21
94 SEG20
93 SEG19
92 SEG18
91 SEG17
SEG45 1
SEG46 2
SEG47 3
SEG48 4
SEG49 5
SEG50 6
SEG51 7
SEG52 8
SEG53 9
SEG54 10
SEG55 11
SEG56 12
SEG57 13
SEG58 14
SEG59 15
SEG60 16
COM9 17
COM10 18
COM11 19
COM12 20
COM13 21
COM14 22
COM15 23
COM16 24
COM25 25
COM26 26
COM27 27
COM28 28
COM29 29
COM30 30
COM31 31
COM32 32
Y
(0, 0)
Chip size: 3920 ×
5080
Pad size: 100 × 100
Unit: µm
S6A0071
X
90 SEG16
89 SEG15
88 SEG14
87 SEG13
86 SEG12
85 SEG11
84 SEG10
83 SEG9
82 SEG8
81 SEG7
80 SEG6
79 SEG5
78 SEG4
77 SEG3
76 SEG2
75 SEG1
74 COM1
73 COM2
72 COM3
71 COM4
70 COM5
69 COM6
68 COM7
67 COM8
66 COM17
65 COM18
64 COM19
63 COM20
62 COM21
61 COM22
60 COM23
59 COM24
NOTE:
VSS 33
OSC1 34
OSC2 35
C2 43
V5OUT 41
VCI 44
VDD 45
RS 46
R/W 47
V1 36
V2 37
V3 38
V4 39
V5 40
C1 42
"S6A0071" marking is to make the PAD No. 95 easy to find.
3
E 48
DB0 49
DB1 50
DB2 51
DB3 52
DB4 53
DB5 54
DB6 55
DB7 56
T2 57
T1 58
S6A0071 32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
PAD CENTER COORDINATES
PAD PAD COORDINATE PAD PAD COORDINATE PAD
NUM. NAME
1 SEG45 -1794 2170
2 SEG46 -1794 2030
3 SEG47 -1794 1890
4 SEG48 -1794 1750
5 SEG49 -1794 1610
6 SEG50 -1794 1470
7 SEG51 -1794 1330
8 SEG52 -1794 1190
9 SEG53 -1794 1050
10 SEG54 -1794
11 SEG55 -1794
12 SEG56 -1794
13 SEG57 -1794
14 SEG58 -1794
15 SEG59 -1794
16 SEG60 -1794
17 COM9 -1794
18 COM10 -1794 -210 58 T1 1562 -2374
19 COM11 -1794 -350 59 COM24 1794 -2170
20 COM12 -1794 -490 60 COM23 1794 -2030 100 SEG26
21 COM13 -1794 -630 61 COM22 1794 -1890 101 SEG27
22 COM14 -1794 -770 62 COM21 1794 -1750 102 SEG28
23 COM15 -1794 -910 63 COM20 1794 -1610 103 SEG29
24 COM16 -1794 -1050
25 COM25 -1794 -1190
26 COM26 -1794 -1330
27 COM27 -1794 -1470
28 COM28 -1794 -1610
29 COM29 -1794 -1750
30 COM30 -1794 -1890
31 COM31 -1794 -2030
32 COM32 -1794 -2170
X Y NUM. NAME
41 V5OUT -562 -2374
42 C1 -438 -2374
43 C2 -312 -2374
44 VCI -188 -2374
45 VDD -62 -2374
46 RS 62 -2374
47 R/W 118 -2374
48 E 312 -2374
49 DB0 438 -2374
910 50 DB1 562 -2374
770 51 DB2 688 -2374
630 52 DB3 812 -2374
490 53 DB4 938 -2374
350 54 DB5 1062 -2374
210 55 DB6 1188 -2374
70 56 DB7 1312 -2374
-70 57 T2 1438 -2374
64 COM19 1794 -1470 104 SEG30
65 COM18 1794 -1330 105 SEG31
66 COM17 1794 -1190 106 SEG32 -189 2374
67 COM8 1794 -1050 107 SEG33 -314 2374
68 COM7 1794 -910 108 SEG34 -439 2374
69 COM6 1794 -770 109 SEG35 -564 2374
70 COM5 1794 -630 110 SEG36 -689 2374
71 COM4 1794 -490 111 SEG37 -814 2374
72 COM3 1794 -350 112 SEG38 -939 2374
X Y NUM. NAME X Y
81 SEG7 1794 910
82 SEG8 1794 1050
83 SEG9 1794 1190
84 SEG10 1794 1330
85 SEG11 1794 1470
86 SEG12 1794 1610
87 SEG13 1794 1750
88 SEG14 1794 1890
89 SEG15 1794 2030
90 SEG16 1794 2170
91 SEG17 1686 2374
92 SEG18 1561 2374
93 SEG19 1436 2374
94 SEG20 1311 2374
95 SEG21 1186 2374
96 SEG22 1061 2374
97 SEG23
98 SEG24
99 SEG25
PAD COORDINATE
936 2374
811 2374
686 2374
561 2374
436 2374
311 2374
186 2374
61 2374
-64 2374
4
32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0071
PAD CENTER COORDINATES
PAD PAD COORDINATE PAD PAD COORDINATE PAD PAD COORDINATE
NUM. NAME
33 VSS -1562 -2374
34 OSC1 -1438 -2374
35 OSC2 -1312 -2374
36 V1 -1188 -2374
37 V2 -1062 -2374
38 V3 -938 -2374
39 V4 -812 -2374
40 V5 -688 -2374
X Y NUM. NAME
(Continued)
X Y NUM. NAME X Y
73 COM2 1794 -210 113 SEG39 -1064 2374
74 COM1 1794 -70 114 SEG40 -1189 2374
75 SEG1 1794 70 115 SEG41 -1314 2374
76 SEG2 1794 210 116 SEG42 -1439 2374
77 SEG3 1794 350 117 SEG43 -1564 2374
78 SEG4 1794 490 118 SEG44 -1689 2374
79 SEG5 1794 630
80 SEG6 1794 770
5
S6A0071 32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
PAD DESCRIPTION
PAD
Pad No. I/O NAME Description Interface
( No.)
VDD
VSS
V1-V5 36-40
S1-S60 75-118,
45 For logical circuit (+3V, 5V)
33 Supply voltage Ground (0V) Power supply
Bias voltage level for LCD driving
O Segment output Segment signal output for LCD drive LCD
1-16
C1-C8
C9-C16
C17-C24
C25-C32
74-67,
17-24,
66-59,
25-32,
O Common output Common signal output for LCD drive LCD
OSC1 34 I Oscillator When using internal oscillator, connect
external Rf resistor.
OSC2 35 O Oscillator If external clock is used, connect it to
OSC1
RS 46 I Register select Used as register selection input.
When RS = 1, Data register is selected.
When RS = 0, Instruction register is
selected.
R/W 47 I Read/write Used as read/write selection input.
When RW = 1, read operation.
When RW = 0, write operation.
E 48 I Read/write
Used as read/write enable signal. MPU
Enable
DB0 - DB3 49 - 52 I/O Data bus 0-7 In 8-bit bus mode, used as low order
bidirectional data bus.
In 4-bit bus mode, open these pins.
DB4 - DB7
53 - 56 I/O Data bus 0-7 In 8-bit bus mode, used as high order
bidirectional data bus.
In 4-bit bus mode, used as both high and
Vci 44 I Voltage doubler
output
low order. DB7 used for busy flag output.
Input terminal for voltage doubler.
(normally Vci = VDD)
External resistor
OSC/OSC2
External clock
(OSC1)
MPU
MPU
MPU
MPU
Power supply
C1,C2 42, 43 I Capacitor Capacitor for voltage doubler connecting
Capacitor
terminal (+).
Capacitor for voltage doubler connecting
terminal(-).
V5OUT 41 O Voltage doubler
output
Voltage doubler output terminal
connected to LCD supply voltage
V5
T1, T2 58, 57 I Test pin Maker testing terminal (normally open)
6
32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0071
FUNCTION DESCRIPTION
System Interface
This chip has both kinds of interface type with MPU: 4-bit bus and 8-bits bus. 4-bit bus and 8-bit bus are selected
by the DL bit in the instruction register.
During read or write operation, two 8-bit registers are used. One is the data register (DR), and the other is the
instruction register (IR).
The data register (DR) is used as a temporary data storage place for being written into or read from
DDRAW/CGRAM . Target RAM is selected by RAM address setting instruction. Each internal operation, reading
from or writing into RAM, is done automatically. Thus, after MPU reads DR data, the data in the next
DDRAM/CGRAM address is transferred into DR automatically. Also, after MPU writes data to DR, the data in DR
is transferred into DDRAM/CGRAM automatically. The instruction register (IR) is used only to store instruction
codes transferred from MPU. MPU cannot use it to read instruction data. To select a register, you can use the RS
input pin in 4-bit/8-bit bus mode.
Table 1. Various Kinds of Operations to RS and R/W Bits
RS R/W Operation
0 0 Instruction Write operation (MPU writes instruction code into IR)
0 1 Read Busy flag (DB7) and address counter (DB0 - DB7)
1 0 Data Write operation (MPU writes data into DR)
1 1 Data Read operation (MPU reads data into DR)
Busy Flag (BF)
When BF = 1, it indicates that the internal operation is being processed. So during this time the next instruction
cannot be accepted. BF can be read through DB7 port, when RS = 0, and R/W = 1. (Read Instruction Operation).
Before executing the next instruction, be sure that BF is not 1.
Address Counter (AC)
The Address Counter (AC) stores DDRAM/CGRAM addresses, transferred from IR. After writing into (reading
from) DDRAM/CGRAM. AC is automatically increased (decreased) by 1. When RS = 0 and R/W = 1, AC can be
read through ports DB0 - DB6.
7
S6A0071 32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
Display Data RAM (DDRAM)
The DDRAM stores display data of maximum 80 × 8 bits (80 characteristics). The DDRAM address is set in the
address counter (AC) as a hexadecimal number. (Refer to fig-1).
MSB LSB
AC6
AC5 AC4 AC3 AC2 AC1 AC0
Figure 1. DDRAM Address
1) 1-line Display
In case of a 1-line display, the address range of DDRAM is 00H - 04H.
1
COM1
COM8
COM1
COM8
COM1
COM8
2 3 4 5 6 7 8
00
01 02 03 04 05 06 07
SEG1 S6A0071 SEG60
1
2 3 4 5 6 7 8109
01 02 03 04 05 06 07
1
2 3 4 5 6 7 8089
00
4F
01 02 03 04 05 06 07
08
Figure 2. 1-line × 24 char. Display
10 11 12 13 14 15 161017
08909 0A 0B 0C 0D 0E 0F
SEG1 S6A0071 SEG60
10 11 12 13 14 15 161817
09 0A 0B 0C 0D 0E 0F
(After Shift Left)
10 11 12 13 14 15 161017
09 0A 0B 0C 0D 0E 0F
(After Shift Right)
Display position
18 19 20 21 22 23 24
11 12 13 14 15 16 17
DDRAM Address
18 19 20 21 22 23 24
11 12 13 14 15 16 17
18 19 20 21 22 23 24
11 12 13 14 15 16
COM9
COM16
COM9
COM16
COM9
COM16
8
32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0071
2) 2-line Display
In case of a 2-line display, the address range of DDRAM is 00H - 27H and 40H - 67H.
Display position
1
COM1
COM8
COM17
COM24
COM1
COM8
COM17
COM24
2 3 4 5 6 7 8089
00
01 02 03 04 05 06 07
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57
SEG1 S6A0071 SEG60 S6A0071SEG1 SEG60
1
2 3 4 5 6 7 8089
01 02 03 04 05 06 07
41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57
10 11 12 13 14 15 161017
09 0A 0B 0C 0D 0E 0F
10 11 12 13 14 15 161017
09 0A 0B 0C 0D 0E 0F
18 19 20 21 22 23 24
11 12 13 14 15 16 17
DDRAM Address
18 19 20 21 22 23 24
11 12 13 14 15 16 17
18
58
COM9
COM16
COM25
COM32
COM9
COM16
COM25
COM32
COM1
COM8
COM17
COM24
(After Shift Left)
1
2 3 4 5 6 7 8089
00
27
67
01 02 03 04 05 06 07
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56
10 11 12 13 14 15 161017
09 0A 0B 0C 0D 0E 0F
(After Shift Right)
18 19 20 21 22 23 24
11 12 13 14 15 16
Figure 3. 2-line × 24 char. Display with 60 SEG. Extension Driver
COM9
COM16
COM25
COM32
9
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