Samsung S5T8809X01-R0B0 Datasheet
PLL FREQUENCY SYNTHESIZER FOR PAGER S5T8809
INTRODUCTION
16-TSSOP-0044
S5T8809 is a superior low-power-programmable PLL frequency
synthesizer which can be used in high performance / Simple
application for a Wide Area Pager system.
S5T8809 consists of 2 kinds of divider block including a 19-bit Shift
register, 16/18-bit Latch, 13/15bits R-counter and 16/18-bit NCounter, 32/33 Prescaler, and a phase detector block including a
Phase detector, Lock detector and a Charge pump.
S5T8809 also has a battery saving mode which can control each
register block by serial control data from the µ-controller (MICOM)
and it also has boost up signal output for fast locking.
( Magnification = 1 : 4 )
FEATURES
• Maximum operating frequency: 330MHz @ 300mV
• On-chip reference oscillator supports external crystal which oscillates up to 23MHz
• Superior supply current:
— F
• Operating voltage: V
= 310MHz, I
FIN
= 0.8mA (Typ.) @ V
DD1
= 0.95 to 1.5V and V
DD1
DD1
DD2
• Excellent Divider range:
, V
P-P
= 1.0V, V
= 1.0V, V
DD1
DD2
= 2.0 to 3.3V
= 3.0V
DD2
= 3.0V
— Ref. Divider:
FRC (0): 1 / 40 to 1 / 65528 (Multiple): Default
FRC (1): 1 / 5 to 1 / 32767
— Rx Divider:
PBC (0): 1 / 1056 ~ 1 / 65535: Default
PBC (1): 1 / 1056 ~ 1 / 262143
• Boost-up signal output for Fast Locking
• In the Standby mode, VDD1 block can be controlled by BSB Pin status
— Standby current consumption: 10µA (Max.)
• Programmable control the output of LD to reduce internal noise
• Programmable 17 / 19-bit shift register value controlled by PBC
• Charge pump output circuitry for passive filter
• Package type: 16−TSSOP (0.65mm)
ORDERING INFORMATION
Device Package Operating Temperature
+S5T8809X01-R0B0 16−TSSOP−0044 −25°C to +75°C
+: New Product
1
S5T8809 PLL FREQUENCY SYNTHESIZER FOR PAGE
BLOCK DIAGRAM
OSCO
V
BSB
EN
DATA
CLK
VSS
VDD1
OSCI
DD2
Fin
1
2
3
14
13
12
11
6
8
Amp
VDD1
V
DD2
Schmitt
Trigger
7
Amp
V
DD1
1 / 8
Prescaler
16 or 18Bit Latch
16 or 18Bit Latch
32/33
Prescaler
13 or 15 Bit
Divider
( R - counter )
FRC
16 / 18
Shift Register
17 or 19 Bit
18
18
Swallow
Counter
*
5 Bit
13 / 15
(Test1. LDC)
Phase
Detector
11 or 13 bit
Main Counter
Schmitt
Trigger
Lock
Detector
2
Charge
Pump
Fast
Lock
Schmitt
Trigger
POR
Schmitt
Trigger
16
10
15
9
LD
5
PDO
4
FL
FLC
PBC
2
PLL FREQUENCY SYNTHESIZER FOR PAGER S5T8809
PIN CONFIGURATION
OSCI
OSCO
V
DD2
FL
PDO
V
SS
Fin
VDD1
1
2
3
4
5
6
7
8
KS8809D
S5T8809
16
15
14
13
12
11
10
9
TEST
FLC
BSB
EN
DATA
CLK
LD
PBC
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S5T8809 PLL FREQUENCY SYNTHESIZER FOR PAGE
PIN DESCRIPTION
Pin No Symbol Description
1 OSCI These input / output pins generate the reference frequency.
2 OSCO
In case of OSCI Pin, external reference frequency can be used through the AC coupling.
3 V
DD2
The highest potential supply terminal that can be supplied up to 2.0 ~ 3.3V.
4 FL Booster signal output for fast locking.
5 PDO The output of RX phase detector terminal for passive loop filter.
There are 3-kinds of output signal states according to Rx loop error.
6 V
SS
Ground terminal
7 Fin Input terminal for the frequency from VCO.
Output frequency from VCO was inputted through AC coupling
8 V
DD1
Voltage supply terminal for Oscillator and Fin block.
This pin can be supplied up to 0.95 ~ 1.5V from VSS.
9 PBC This is an input for programmable bit control which has Schmitt Trigger architecture,
Internally biased pull-up.
High = 16 Bits N-Divider (Default: ND0 ~ ND15)
Low = 18 Bits N-Divider (ND0 ~ ND7)
cf) R-divider bits will be changed by the FRC bit of program
10 LD The output of phase detector can be controlled by R-counter register. When the LDC bit
of R-counter set to Low, the output will be disabled to reduce a noise problem, but if it is
set to High, the output will be enabled to show an lock / unlock status that is the error
width between to Ref. signal and the VCO output signal.
11 CLK These pins are controlled by the µ-controller which has Schmitt Trigger architecture,
12 DATA
13 EN
Internally biased pull-down. The features of these pins are as follows; Clock input for 17
or 19-bit Shift Register, Serial data input (it include TEST1, FRC and LDC), and Latch
enable input.
14 BSB In the BS mode (set to Low), the VDD1 block will be powered off, but the internal latch
data is still valid because the VDD2 is supplied continuously. This input has Schmitt
Trigger architecture & internally biased pull-up.
15 FLC This is the input pin for Fast Locking Control (FLC) which has Schmitt Trigger
architecture, Internally biased pull-down.
Low = The Current of PDO Charge pump output is Normal (Default: x1)
High = The Current of PDO Charge pump output is increase (x 1.5)
16 TEST This is the input pin for TEST which has Schmitt trigger architecture, Internally biased
Pull-down.
Low = All block will be operated as normal state (Default)
High = LD and FL state will be TES mode
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PLL FREQUENCY SYNTHESIZER FOR PAGER S5T8809
ABSOLUTE MAXIMUM RATINGS
Characteristic Symbol Value Unit
Supply Voltage V
Input Voltage V
Power Dissipation P
Operating Temperature T
Storage Temperature T
DD
~ V
I
D
OPR
STG
DD2
−0.3 ~ +4.0 V
V
−0.3 ~ V
SS
+ 0.3 V
DD
350 mW
−25 ~ +75 °C
−40 ~ +125 °C
ELECTRICAL CHARACTERISTICS
(Ta = 25°C, V
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Operating voltage V
Operating current IDD F
Standby current ISB1 V
Input voltage
(DATA, CLK, EN, BS)
Input voltage
(TEST, PBC)
Input current
(Fin, Xin)
Input frequency F
Output current
(PDO, FL)
Output current
(LD)
Setup-time
(DATA-CLK, CLK-EN)
= 1.0V, V
DD1
= 3.0V, unless otherwise specified)
DD2
− 0.95 1.0 1.5 V
− 2.0 3.0 3.3
− 0.8 − mA
P-P
= 3.0V, BSB=High
DD2
= 3.0V, BSB=Low − 0.1 10 µA
DD2
− − − 0.3 V
− V
-0.3 − −
DD2
− − − 0.2 V
− V
, V
= 1.0V 40 − 330 MHz
DD1
, V
P-P
= 1.0V 7 12.8 23
DD1
-0.2 − −
SS1
V
F
I
I
I
I
DD1
DD2
V
IL
V
IH
V
IL
V
IH
I
IH
I
IL
FIN
OSCI
OH1
OL1
OH2
OL2
= 12.8MHz
OSCI
F
= 310MHz @ 0.3V
FIN
V
= 1.0V, V
DD1
= 0.0V, V
DD1
VIH = V
, BSB = High − − 20 µA
DD1
VIL = 0V, BSB = High − − 20
V
= 0.3V
V
FIN
OSCI
P-P
= 0.3V
VOH = 0.4V 1.0 − − mA
VOL = V
- 0.4V 1.0 − −
DD2
VOH = 0.4V 0.1 − − mA
VOL = V
- 0.4V 0.1 − −
DD2
ts − 2 − − µS
Hold time t
H
− 2 − − µS
5
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