Samsung S5T8808A01-R0B0 Datasheet
PLL FREQUENCY SHNTHESIZER FOR PAGER S5T8808A
INTRODUCTION
16−TSSOP−0044
S5T8808A is a superior low-power-programmable PLL frequency
synthesizer which can be used in a high performance Wide Area
Pager system.
S5T8808A consists of 2 kinds of divider block including a 17bit Shift
register, 16-bit Latch, 14/16-bits Counter, Prescaler, and a phase
detector block including a Phase detector, Lock detector and a
Charge pump.
FEATURES
( Magnification = 1 : 4 )
• Maximum operating frequency:
120MHz @ 500mV
165MHz @ 500mV
P-P
P-P
, V
, V
DD1
DD1
= 0.95V, V
= 1.0V, V
DD2
DD2
= 3.0V
= 3.0V
• On-chip reference oscillator supports external crystal which oscillates up to 18MHz
• Superior supply current:
F
= 90MHz, I
FIN
F
= 150MHz, I
FIN
• Operating voltage: V
= 0.6mA (Typ.) @ V
DD1
= 0.9mA (Typ.) @ V
DD1
= 0.95 ~ 2.0V and V
DD1
= 1.0V, V
DD1
DD1
= 1.0V, V
= 2.0 ~ 3.3V
DD2
DD2
DD2
= 3.0V
= 3.0V
• Reference frequency counter divider range: 1 / 28 ~ 1 / 65532 (Multiple 4)
But, the Divider range with FRC_High state: 1 / 7 ~ 1 / 16383
• RX frequency counter divider range: 1 / 28 ~ 1 / 65535
• Package type: 16−TSSOP (0.65mm)
ORDERING INFORMATION
Device Package Operating Temperature
+S5T8808A01-R0B0 16−TSSOP−0044 −25°C to +75°C
+: New Product
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S5T8808A PLL FREQUENCY SHNTHESIZER FOR PAGE
BLOCK DIAGRAM
OSCO
V
NC
EN
DATA
CLK
V
OSCI
DD2
SS
1
2
3
16
13
12
11
6
Amp
14-Bit Divider
( R - counter )
Lock
V
DD1
V
DD2
FRC
14
16-Bit Latch
FnFr
Detector
15
10
Fr
LDT
16
Schmitt
Trigger
Shift Register
17- Bit
16
*
Phase
Detector
Charge
Pump
4
PDA
5
PDP
16-Bit Latch
16
FnFr
9
NC
Fin
VDD1
7
8
Amp
V
DD1
16-Bit Divider
( N - counter )
14
¢º
Fn
2
PLL FREQUENCY SHNTHESIZER FOR PAGER S5T8808A
PIN CONFIGURATION
OSCI
OSCO
V
DD2
PDA
PDP
V
SS
Fin
VDD1
1
2
3
4
S5T8808A
KS8808AD
5
6
7
8
16
15
14
13
12
11
10
9
NC
Fr
Fn
EN
DATA
CLK
LDT
NC
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S5T8808A PLL FREQUENCY SHNTHESIZER FOR PAGE
PIN DESCRIPTION
Pin No Symbol I/O Description
1 OSCI I These input / output pins generate the reference frequency.
2 OSCO O
In case of OSCI Pin, external reference frequency can be used through the AC
coupling.
3 V
DD2
− The highest potential supply terminal that can be supplied up to 2.0 ~ 3.3V,
except for V
DD1
.
4 PDA O The Output of RX Phase detector terminal for active loop filter
There are 3-kinds of output signal states according to Rx Loop Error;
− If Fr > Fn (Fr is leading), the output is negative pulse state,
− If Fr < Fn (Fr is lagging), the output is positive pulse state,
− If Fr = Fn (the same phase), the output is high impedance state.
5 PDP O The Output of RX Phase detector terminal for passive loop filter
There are 3-kinds of output signal states according to Rx Loop Error;
− If Fr > Fn (Fr is lagging), the output is negative pulse state,
− If Fr < Fn (Fr is leading), the output is positive pulse state,
− If Fr = Fn (the same phase), the output is high impedance state.
6 V
SS
− Ground terminal
7 Fin I Input terminal for 16 bit Divider from VCO.
Mostly, VCO output should be input through the AC coupling and the minimum
8 V
DD1
input level is 500mV
− Voltage supply terminal for Oscillator and Fin block.
(in case of 90MHz)
P-P
This pin can be supplied up to 0.95 ~ 2.0V from VSS.
9 NC − No Connection
10 LDT O Lock detector is also on output of the Phase Detector.
The LOW state of this output shows unlock status, which is the error width
between the Ref. signal and the VCO output signal.
11 CLK I These pins are controlled by the µ-controller and it also has Schmitt Trigger
12 DATA I
13 EN I
architecture.
Internally biased pull-down.
The features of these pins are as follows:
Clock input for 17-bit Shift Register, Serial data input (it include FnFr-on / off and
FRC), and Latch enable input (User selectable EN1 or EN2).
14 Fn O Output terminal for divider value of N-counter. To control the output On/Off, the
FnFr bit of the Reference register can be programmed.
When FnFr bit is set to High, this output shows low level.
15 Fr O Output terminal of divider value of N-counter. To control the output On/Off, the
FnFr bit of the Reference register can be programmed.
When FnFr bit is set to High, this output shows low level.
16 NC − No Connection. Internally biased pull-up.
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