Samsung S5T8554B01-D0B0, S5T8554B01-S0B0, S5T8554B02-L0B0, S5T8557B01-D0B0, S5T8557B01-S0B0 Datasheet

1 CHIP CODEC S5T8554B/7B

INTRODUCTION

16-CERDIP

The S5T8554B/7B are single-chip PCM encoders and decoders
(PCM CODECs) and PCM line filters. These devices provide all the
functions required to interface a full-duplex voice telephone circuit
with a time-division-multiplex (TDM) system.
These devices are designed to perform the transmit encoding and
receive decoding as well as the transmit and receive filtering
functions in PCM system. They are intended to be used at the
analog termination of a PCM line or trunk.
These devices provide the bandpass filtering of the analog signals
prior to encoding and after decoding. These combination devices
perform the encoding and decoding of voice and call progress tones
as well as the signalling and supervision information.

16-DIP-300A

8−DIP−300

FEATURES

• Complete CODEC and filtering system

• Meets or exceeds AT&T D3/D4 and CCITT specifications
µ-Law: S5T8554B, A-Law: S5T8557B

• On-chip auto zero, sample and hold, and precision voltage references

• Low power dissipation: 60mW (operating), 3mW (standby)

• ± 5V operation

• TTL or CMOS compatible

• Automatic power down

ORDERING INFORMATION

Device Package Operating Temperature

S5T8554B02-L0B0
S5T8557B02-L0B0

S5T8554B01-D0B0
S5T8557B01-D0B0

S5T8554B01-S0B0
S5T8557B01-S0B0

16-CERDIP −25°C to 125°C

16-DIP-300A −25°C to +70°C

16-SOP-BD300 −25°C to +70°C

1

S5T8554B/7B 1 CHIP CODEC

X

PIN CONFIGURATION

+

V

GNDA

1

BB

2

VFXI

16

-

VFXI

15

VFRO

V

FS

D

BCLKR/CLKSEL

MCLKR/PDN

3

4

CC

5

R

6

R

7

8

KT8554/7

S5T8554B/7B

14

13

12

11

10

9

PIN DISCRIPTION

Pin No Symbol Description

1 V

BB

2 GNDA Analog ground.
3 VFRO Analog output of the receive power Amp.
4 V
5 FS
6 D

CC

R

R

7 BLCKR/

CLKSEL

VBB = −5V ± 5%

VCC = +5 V ± 5%
Receive frame sync pulse. 8kHz pulse train
PCM data input.
Logic input which selects either 1.536MHz/1.544MHz or 2.048MHz for master clock

in normal operation and BCLKX is used for both TX and RX directions.
Alternately direct clock input available, vary from 60kHz to 2.048MHz.

GS

X

TS

X

FSXS

D

X

BCLK

MCLK

X

8 MCLKR/

9 MCLK

10 BLCK

11 D
12 FS
13 TS
14 GS
15 VFXI
16 VFXI

2

PDN

X

When MCLKR is connected continuously high, the device is powered down.
Normally connected continuously low, MCLKX is selected for all DAC timing.
Alternately direct 1.536MHz/1.544MHz or 2.048MHz clock input available.

Must be 1.536MHz/1.544MHz or 2.048MHz.

X

May be vary from 64kHz to 2.048MHz but BCLKX is externally tied with MCLKX in

X

normal operation.
PCM data output.

X
X

TX frame sync pulse. 8kHz pulse train.
Changed from high to low during the encoder timeslot. Open drain output.
Analog output of the TX input amplifier. Used to set gain through external resistor.

X

−

Inverting input stage of the TX analog signal.

+

Non-inverting input stage of the TX analog signal.

1 CHIP CODEC S5T8554B/7B

ABSOLUTE MAXIMUM RATING

Characteristic Symbol Value Unit

Positive Supply Voltage V
Negative Supply Voltage V
Voltage at Any Analog Input or Output V
Voltage at Any Digital Input or Output V

CC

BB
I (A)
I (D)

VCC + 0.3 ~ VBB - 0.3 V

VCC + 0.3 ~ GNDA - 0.3 V

7 V

−7 V

Operating Temperature Range Ta −25 ~ +125 °C
Storage Temperature Range T
Lead Temperature (Soldering, 10 secs) T

STG

LEAD

−65 ~ +150 °C
300 °C

ELECTRICAL CHARACTERISTICS

(Unless otherwise noted, VCC = 5.0V ± 5%, VBB = −5.0V ± 5%, GNDA = 0V, Ta = 0°C to 70°C;
typical characteristics specified at VCC = 5.0V, VBB = −5.0V, Ta=25°C; all signals referenced to GNDA)

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

POWER DISSIPATION

Power-Down Current I
Power-Down Current I

CC (DOWN)
BB (DOWN)

Active Current I
Active Current I

DIGITAL INTERFACE

CC (A)
BB (A)

No Load − 0.5 1.5 mA
No Load − 0.05 0.3 mA
No Load − 6.0 9.0 mA
No Load − 6.0 9.0 mA

Input Low Voltage V
Input High Voltage V
Input Low Current I
Input High Current I
Output Low Voltage V

IL

IH
IL
IH
OL

GNDA≤ VIN ≤ VIL, all digital input −10 − 10 µA
VIH ≤ VIN ≤ V
DX, IL = 3.2mA

SIGR, IL = 1.0mA
TSX, IL = 3.2mA, open drain

Output High Voltage I

O (HZ)

DX, IH = −3.2mA
SIGR, IH = −1.0mA

Output Current in High

I

O (HZ)

DX, GNDA ≤ VO ≤ V

Impedance State (Tri -state)

ANALOG INTERFACE WITH RECEIVE FILTER

Output Resistance R

O

Pin VFRO − 1 3 Ω

− − − 0.6 V

− 2.2 − − V

CC

−10 − 10 µA

− − 0.4

0.4

0.4

2.4

− − V

2.4

CC

−10 − 10 µA

V
V
V

V

3

S5T8554B/7B 1 CHIP CODEC

ELECTRICAL CHARACTERISTICS

(Unless otherwise noted, VCC = 5.0V ± 5%, VBB = −5.0V ± 5%, GNDA = 0V, Ta = 0°C to 70°C;
typical characteristics specified at VCC = 5.0V, VBB = −5.0V, Ta=25°C; all signals referenced to GNDA)

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

Load Resistance R
Load Capacitance C
Output DC Offset Voltage V

OO (RX)

L
L

VFRO = ± 2.5V 600 − − Ω

− − − 500 pF

− −200 − 200 mV

ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER

Input Leakage Current I

LKG

Input Resistance R
Output Resistance R
Load Resistance R
Load Capacitance C
Output Dynamic Range V

OD (TX)

Voltage Gain G

I

O

L
L

V

-2.5V≤V≤+2.5V, VFXI+ or VFXI- −200 − 200 nA

-2.5V≤V≤+2.5V, VFXI+ or VFXI- 10 − − MΩ
Closed loop, unity gain − 1 3 Ω
GS
GS

X
X

10 − − kΩ

− − 50 pF
GSX, RL≤10KW ± 2.8 − − V
VFXI+ to GSX 5,000 − − V/N

Unity Gain Bandwidth BW − 1 2 − MHz
Offset Voltage V
Common-Mode Voltage V

IO (TX)

CM (TX)

CMRRXA > 60dB −2.5 − 2.5 V

− −20 − 20 mV

Common-Mode Rejection Ratio CMRR DC Test 60 − − dB
Power Supply Rejection Ratio PSRR DC Test 60 − − dB

4

1 CHIP CODEC S5T8554B/7B

TIMING CHARACTERISTICS

(Unless otherwise noted, VCC = 5.0V ± 5%, VBB = −5.0V ± 5%, GNDA = 0V, Ta = 0°C to 70°C;
typical characteristics specified at VCC = 5.0V, VBB = −5.0V, Ta=25°C; all signals referenced to GNDA)

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

Frequency of Master Clock f

Rise Time of Bit Clock t
Fall Time of Bit Clock t
Holding Time from Bit Clock

t

Low to Frame Sync
Holding Time from Bit Clock

t

High to Frame Sync
Set-Up Time from Frame Sync

t

SU (FBCL)

to Bit Clock Low
Delay Time from BCLKX High

t

to Data Valid
Delay Time to TSX Low t

Delay Time from BCLKX Low to

D (TSXL)

t

Data Output Disabled
Delay Time to Valid Data from

FSX or BCLKX, Whichever
Comes Later

MCK

Depends on the device used
and the BCLKR/CLKSEL Pin.
MCLKX and MCLK

R (BCK)

F (BCK)tPB
H (LFS)

H (RFS)

tPB = 488ns − − 50 nS

Long frame only 0 − − nS

Short frame only 0 − − nS

Long frame only 80 − − nS

D (HDV)

Load = 150pF plse 2 LSTTL
loads

Load = 150pF plse 2 LSTTL
loads

D (LDD)

t

D (VD)

CL = 0pF to 150pF 20 − 165 nS

− 1.536

− nS

1.544

R

2.048

= 488ns − − 50 nS

0 − 180 nS

− − 140 nS

− 50 − 165 nS

Set-Up Time from DR Valid to
BCLK

Hold Time from FS

R/X

Low

Low to

R/X

DR Invalid
Set-Up Time from FS

BCLK

R/X

Low

R/X

to

Width of Master Clock High t
Width of Master Clock Low t
Rise Time of Master Clock t
Fall Time of Master Clock t
Set-Up Time from BCLKX High

t
(and FSX In Long Frame Sync
Mode) to MCLKX Falling Edge

t

SU (DRBL)

t

H (BLDR)

t

SU (FBLS)

W (MCKH)

W (MCKL)

R (MCK)
F (MCK)

SU (BHMF)

− 50 − − nS

− 50 − − nS

Short frame sync pulse (1 or 2
bit clock periods long) (Note 1)

MCLKX and MCLK
MCLKX and MCLK
MCLKX and MCLK
MCLKX and MCLK

R
R
R
R

First bit clock after the leading
edge FS

X

50 − − nS

160 − − nS
160 − − nS

− − 50 nS

− − 50 nS

− − − −

5