Samsung S5T8554B03-D0B0, S5T8554B03-S0B0 Datasheet
CODEC FOR DIGITAL ANSWERING PHONE S5T8554B03
INTRODUCTION
The S5T8554B03 consists of on-chip PCM encoders, decoders (PCM CODECs)
and PCM line filter. This device provides all the functions required to
interface a full-duplex voice telephone circuit, digital answering phone. This
device is designed to perform the transmit encoding and receive decoding as
well as the transmit and receive filtering function in PCM system. Also it is intended to be used at the analog termination of a PCM line / trunk. This device
provide the Band pass filtering of the analog signals prior to encoding and
after decoding. This combination device performs the encoding and decoding
of voice and call progress tones as well as the signaling and supervision
information.
16−DIP−300
16−SOP−BD300
FEATURES
• Complete CODEC and filtering system
• Encoding / Decoding : 8 bits µ-law PCM
• On-chip auto zero, sample and hold,
and precision voltage references
• Low power dissipation : 60mW ( operating )
3mW ( standby )
• ± 5V operation
• TTL or CMOS compatible
• Automatic power down
ORDERING INFORMATION
Device Package Operating Temperature
S5T8554B03-D0B0 16−DIP−300
S5T8554B03-S0B0 16−SOP−BD300
PIN CONFIGURATION
V
GNDA
VFRO
V
FS
D
BCLKR/CLKSEL
MCLKR/PDN
1
BB
2
3
4
CC
5
R
6
R
7
8
0 ~ + 70°C
S5T8554B03
KS8620
16
15
14
13
12
11
10
VFIXI+
VFXIGS
X
TS
X
FS
X
D
X
BCLK
X
9
MCLK
X
1
S5T8554B03 CODEC FOR DIGITAL ANSWERING PHONE
MCLK
PDN
BCLK
CLKSEL
BLOCK DIAGRAM
R2
14
R1
Analog In
15
16
VFxI-
VFxI+
GSx
+
RC Active
Filter
Switched
Capacitor
B.P.F
comparator
Auto-zero
logic
Sample & Hold
DAC
11
Dx
VFRO
Voltage
Reference
Switched
Capacitor
L.P.F
2
4
Vcc
RC Active
Filter
1
VBB
3
Power
Amplifier
GNDA
A/D
Control
Logic
Sample & Hold
DAC
Timing and Control
9 8
10 7
R /
MCLKx
R /
BCLKx
5
X’mit
register
DE
Receive
register
CLK
FSR
12
FSx
13
6
DR
/TSx
Figure 1.
2
CODEC FOR DIGITAL ANSWERING PHONE S5T8554B03
PIN DESCRIPTION
Pin No Symbol Description
1 V
BB
VBB = −5V ± 5%
2 GNDA Analog ground
3 VFRO Analog output of the receiver filter
4 V
5 FS
6 D
CC
R
R
7 BCLKR /
CLKSEL
Vcc = + 5V ± 5%
Receive frame sync pulse. 8kHz pulse train.
PCM data input
Logic input which selects either 1.536MHz/1.544MHz or 2.048MHz for master clock
in normal operation and BCLKx is used for both TX and RX directions.
Alternately direct clock input available, vary from 64kHz to 2.048MHz.
8 MCLKR /
PDN
When MCLKR is connected continuously high, the device goes powered down .
Normally connected continuously low, MCLKx is selected for all DAC timing.
Alternately direct 1.536MHz/1.544MHz or 2.048MHz clock input is available.
9 MCLKXn 1.536MHz/1.544MHz or 2.048MHz clock input is available
10 BCLK
May be vary from 64kHz 2.048MHz,
X
but BCLKx is externally tied with MCLKx in normal operation.
11 D
12 FS
13 TS
14 GS
X
X
X
X
PCM data output.
TX frame sync pulse. 8kHz pulse train.
Changed from high to low during the encoder timeslot. Open drain output.
Analog output of the TX input amplifier.
Used to set gain through external resistor between pin 14 to pin 15.
15 VFXI− Inverting input stage of the TX analog signal.
16 VFXI+ Non-inverting input stage of the TX analog signal.e
ABSOLUTE MAXIMUM RATINGS ( TA = 25°C )
Characteristic Symbol Value Unit
Positive Supply Voltage Vcc +7 V
Negative Supply Voltage VBB −7 V
Voltage at any Analog Input or Output V I (A) Vcc + 0.3 to VBB − 0.3 V
Voltage at any Digital Input or Output V I (D) Vcc + 0.3 to GNDA − 0.3 V
Operating Temperature Range Ta 0 to 70 °C
Storage Temperature Range TSTG −65 to +150 °C
Lead Temperature Range ( soldering, 10 sec ) TLEAD 300 °C
3
S5T8554B03 CODEC FOR DIGITAL ANSWERING PHONE
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified : Ta = 0°C to 70°C , Vcc = 5V ± 5%, VBB = −5V ± 5%, GNDA = 0V )
Characteristic System Test Conditions Min. Typ. Max. Unit
Power Dissipation
Power down Current I CC ( down ) No Load − 0.5 3.0 mA
Power down Current I BB ( down ) No Load − 0.05 1.0 mA
Active Current I CC ( A ) No Load − 6.0 10 mA
Active Current I BB ( A ) No Load − 6.0 10 mA
Digital Interface
Input Low Voltage V IL − − − 0.6 V
Input High Voltage V IH − 2.2 − − V
Input Low Current I IL GNDA < VIN < VIL , all digital input −15 − 15 µA
Input High Current I IH VIH < VIN < Vcc −15 − 15 µA
Output Low Voltage V OL DX , IL = 3.2 mA
SIGR , IL = 1.0 mA
/TSX , IL = 3.2 mA , open drain
Output High Voltage V OH DX , IH = −3.2mA
SIGR , IH = −1.0mA
Output Current in High
impedance state ( Tri − state )
Analog Interface with Receiver Filter
Output Resistance R O pin VFRO − 1 3 Ω
Load Resistance R L VFRO = ± 2.5V 600 − − Ω
Load Capacitance C L − − − 500 pF
Output Capacitance C L − −200 − 200 mV
Analog Interface with Transmit input Amp
Input Leakage Current I LKG −2.5V<V<+2.5V, VFXI+ or VFXI- −200 − 200 nA
Input Resistance R I −2.5V<V<+2.5V, VFXI+ or VFXI- 10 − − MΩ
Output Resistance R O closed loop , unity gain − 1 3 Ω
Load Resistance R L GSx 10 − − kΩ
Load Capacitance C L GSx − − 50 pF
Output Dynamic Range V OD(TX) GSx , RL < 10kΩ ± 2.8 − − V
Voltage Gain G V VFXI+ to GSx 5000 − − V/V
Unity Gain bandwidth B W − 1 2 − MHz
Offset Voltage V IO(TX) − −20 − 20 mV
Common - mode Voltage V CM(TX) CMRRXA > 60dB −2.5 − 2.5 V
Common mode rejection ratio CMRR DC test 55 − − dB
Power supply rejection ratio PSRR DC test 55 − − dB
I OH (HZ) DX , GNDA < VO < Vcc8 −15 − 15 µA
− − 0.4
2.4
2.4
− − V
0.4
0.4
V
V
V
V
4
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