Samsung S5T3170X01-D0B0, S5T3170X01-S0B0 Datasheet

LOW POWER DTMF RECEIVER S5T3170

INTRODUCTION

The S5T3170 is a complete Dual Tone Multiple Frequency (DTMF)
receiver that is fabricated by low power CMOS and the Switched­Capacitor Filter technology. This LSI consists of band split filters,
which separates counting section which verifies the frequency and
duration of the received tones before passing the corresponding code
to the output bus. It decodes all 16 DTMF tone pairs into a 4bits digital
code. The externally required components are minimized by on chip
provision of a differential input AMP, clock oscillator and latched three
state interface. The on chip clock generator requires only a low cost
TV crystal as an external component.

FEATURES

• Detects all 16 standard tones.

• Low power consumption: 15mW (Typ)

• Single power supply: 5V

• Uses inexpensive 3.58MHz crystal

• Three state outputs for microprocessor interface

• Good quality and performance for using in exchange system

18−DIP−300A

20−SOP−375

• Power down mode/input inhibit

ORDERING INFORMATION

Device Package Operating

S5T3170X01-D0B0 18−DIP−300A
S5T3170X01-S0B0 20−SOP−375

− 25°C — + 75°C

APPLICATIONS

• PABX • Key Phone System

• Central Office • Answering Phone

• Paging Systems • Home Automation System

• Remote Control • Mobile Radio

• Credit Card Systems • Remote Data Entry

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S5T3170 LOW POWER DTMF RECEIVER

PIN CONFIGURATION

IN+

IN-

GS

V

REF

PDN

OSC1

OSC2

GND

1

2

3

4

I

IN

5

S5T3170

6

7

8

9 10

(18-DIP)

18

17

16

15

14

13

12

11

V

DD

SI/GTO

ESO

DSO

Q4

Q3

Q2

Q1

OE

IN+

IN-

GS

V

REF

PDN

NC

OSC1

OSC2

GND

1

2

3

4

I

IN

5

S5T3170

6

7

8

9 12

10

(20-SOP)

20

19

18

17

16

15

14

13

11

V

DD

SI/GTO

ESO

DSO

NC

Q4

Q3

Q2

Q1

OE

PIN DESCRIPTION

Pin No Symbol Description

1 IN + Non inverting input of the internal amp.
2 IN − Inverting input of the internal amp.
3 GS Gain Select.

The output used for gain adjustment of analog input signal with a feedback resistor.

4 V

5 I

REF

IN

6 PDN Control input for the stand-by power down mode.

Reference Voltage output (VDD/2, Typ) can be used to bias the internal amp input of
VDD/2.

Input inhibit.
High input states inhibits the detection of tones. This pin is pulled down internally.

Power down occurs when the signal on this input is in high states. This pin is pulled
down internally.

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LOW POWER DTMF RECEIVER S5T3170

PIN DESCRIPTION (Continued)

Pin No Symbol Description

7, 8 OSC1

OSC2

Clock input/output.
A inexpensive 3.579545MHz crystal connected between these pins completes internal
oscillator. Also, external clock can be used.

9 GND Ground pin.

10 OE Output Enable input.

Outputs Q1-Q4 are CMOS push-pull when OE is High and open circuited (High
impedance) when disabled by pulling OE low. Internal pull up resistor built in.

11 - 14 Q1 - Q4 Three state data output.

When enabled by OE, these digital outputs provide the hexadecimal code
corresponding to the last valid tone pair received.

15 DSO Delayed Steering Output.

Indicates that valid frequencies have been present for the required guard time, thus
constituting a valid signal. Presents a logic high when a received tone pair has been
registered and the output latch is updated.
Returns to logic low when the voltage on SI/GTO falls below VTH.

16 ESO Early Steering Outputs.

Indicates detection of valid tone output a logic high immediately when the digital
algorithm detects a recognizable tone pair.
Any momentary loss of signal condition will cause ESO to return to low.

17 SI/GTO Steering Input/Guard Time Output.

A voltage greater the V

detected at SI causes the device to register the detected

TS

tone pair and update the output latch. A voltage less than VTS frees the device to
accept a new tone pair. The GTO output acts to reset the external steering time

constant, and its state is a function of ESO and the voltage on SI

18 V

DD

Power Supply (+5V, Typ)

ABSOLUTE MAXIMUM RATINGS

Characteristics Symbol Value Unit

Power Supply Voltage V
Analog Input Voltage Range V
Digital Input Voltage Range V
Output Voltage Range V
Current On Any Pin I
Operating Temperature T
Storage Temperature T

DD
I (A)
I (D)

O

I
OPR
STG

6 V

− 0.3 — VDD + 0.3 V

− 0.3 — VDD + 0.3 V

− 0.3 — VDD + 0.3 V

10 V

− 40 — + 85 mA

− 60 — + 150 °C

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