Samsung S5N8951X Datasheet
S5N8951X
G.dmt
ADSL Analog Front End IC
Preliminary Information
(Revision 1.0)
July 2000
SAMSUNG ELECTRONICS CONFIDENTIAL PROPRIETARY
Copyright ©1999-2000 Samsung Electronics, Inc. All Rights Reserved
G.dmt ADSL Analog Front End IC
Contents Page
1 Overview ...................................................................................... 3
1.1 General Description..............................................................3
1.2 Features................................................................................. 3
1.3 Absolute Maximum Ratings.................................................. 4
1.4 Electrical Specifications........................................................ 4
2 Signal description......................................................................... 6
2.1 Functional Block Diagram .................................................... 6
2.2 I/O Pins Descriptions............................................................ 7
2.3 Pin Configurations................................................................ 9
S5N8951X
3 Block Description....................................................................... 10
3.1 ADC/DAC............................................................................ 10
3.2 Tx/Rx LPF........................................................................... 10
3.3 Tx/Rx AGC......................................................................... 10
4 Digital Signal Interface...............................................................11
4.1 Command Signal Interface..................................................11
4.2 Data Signal Interface.......................................................... 18
5 Application Circuit...................................................................... 19
5.1 ATU-R................................................................................. 19
5.2 ATU-C................................................................................. 20
6 Package Information.................................................................... 21
CONFIDENTIAL Preliminary Information (Rev.1.0)
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1. OVERVIEW
This chapter provides an overview of the S5N8951X01 ADSL ATU-C & ATU-R
Analog Front End Chip.
1.1 General
Descriptions
The S5N8951X01 is Analog Front End IC designed for DMT based universal
ADSL(Asymmetric Digital Subscribe Line) modems with 0.35u fully CMOS
technology.
It has 25.875 ~ 138KHz Upstream channel and 142.312 ~ 1104KHz bandwidth
Downstream channel. The S5N8951X01 includes AGC, LPF, ADC, DAC. The
AGC has 42dB gain 0.4dB step in RX mode and –24dB gain 2dB step in TX
mode with 12bit/8bit control bits. Anti alias LPF has 1104KHz passband
frequency in RX path and 138KHz in TX path. Samsung’ s ADSL AFE chip
provides 14bit ADC at 4.416M or 8.832M sample rates and 14bit 4.416MHz,
S5N8951X
G.dmt ADSL Analog Front End IC
1.2 Features
8.832MHz DAC.
An 10bit DAC support VCXO control for timing recovery. The VCXO is divided
into a crystal driver at 35.328MHz.
l Integrated Analog Front End(AFE) for ADSL ATU-C & ATU-R
l Complies with G.dmt and G.lite
l Up to 1104Kbit/s down stream and 138Kbit/s upstream channel
l 14bit 4.416MS/s or 8.832MS/s ADC
l 14bit 4.416MHz or 8.832MHz DAC
th
l 5
-order Low Pass anti-alias Filter TX/RX paths
l RX 42dB 0.4dB step gain range with 12bit control signal
l TX -24dB 2dB step gain range with 8bit control signal
l 10bit 4KHz VCXO DAC
l Fully 0.35um CMOS technology
l 3.3V Power supply operation
l 0.4W Power comsumption
CONFIDENTIAL Preliminary Information (Rev.1.0)
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G.dmt ADSL Analog Front End IC
1.3 Absolute
Maximum Ratings
Symbol Parameter Min Typ Max Units
V
DD
IN
I
IN
T
OPR
T
STG
1.4 Electrical
Specifications
Parameter Min Typ Max Units Notes/Conditions
Power Supply 3.0 3.3 3.6 V
Power Consumption 450 mW Normal Operation
AGC Gain Range 0 42 dB 12bit Control
AGC Step Size 0.4 dB
AGC Step Error 0.2 dB
AGC Input Range 2 Vppd
LPF Cut Off Frequency 1104 KHz 5th Butterworth
LPF Output Range 2 Vppd
LPF Pass Band Ripple -0.5 0.5 dB
LPF Stop Band Attenuation 60 dB at 4.416MHz
AGC Gain Range -24 0 dB 8bit Control
AGC Step Size 2 dB
AGC Step Error 0.2 dB
AGC Output Range 2 Vppd
LPF Cut Off Frequency 138 KHz 5th Chebyshev
LPF Pass Band Ripple -0.5 0.5 dB
LPF Stop Band Attenuation 24 dB at 276KHz
LPF Input Range 2 Vppd
DC Supply Voltage -0.3 3.8 V
DC input Voltage -0.3 VDD+0.3 VV
5V tolerant -0.3 5.5 V
DC input Current -10 10 mA
Operation Temperature -40 85 degree C
Storage Temperature -40 125 degree C
General
Rx Path
THD 70
SNR 70
TX Path
THD 70
SNR 70
ADC
S5N8951X
CONFIDENTIAL Preliminary Information (Rev.1.0)
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G.dmt ADSL Analog Front End IC
Resolution 14 bits
Effective Number Of Bits 13 bits
Sampling Rate 4.416 MHz Selectable 8.832MHz
Full Scale Input Range 2.0 Vppd
DAC
Resolution 14 bits
Effective Number Of Bits 12 bits
Sampling Rate 4.416 MHz Selectable 8.832MHz
Full Scale Output Range 2.0 Vppd
VCXO DAC
Resolution 10 bits
Sampling Rate 4 KHz
Maximum Output Range 2.5 V
Minimum Output Range 0.5 V
S5N8951X
CONFIDENTIAL Preliminary Information (Rev.1.0)
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2. SIGNAL DESCRIPTION
2.1 Functional Block Diagram
TX_DATA
[13:0]
MCLK
AUXCLK
14bit DAC TX LPF TX AGC
S5N8951X
G.dmt ADSL Analog Front End IC
TX_OUTP
TX_OUTN
CONT_DAX
SCLK
SEN
SDIN
SDOUT
RESETN
RX_DATA
[13:0]
10bit DAC
AUTO
TUNNING
BANDGAP
&
VI REF
CONTROL
LOGIC &
REGISTER
14bit ADC RX LPF RX AGC
Figure 2.1.1 S5N8951X01 Functional Block Diagram
CBG
REXT
RX_INP
RX_INN
RX_INPG
RX_INNG
CONFIDENTIAL Preliminary Information (Rev.1.0)
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S5N8951X
G.dmt ADSL Analog Front End IC
2.2 I/O Pins Description
Signal Name Num Type I/O Description
General Pins
RESETN 48 CMOS I System Reset. Active Low
CS1 49 CMOS I Chip Select
CS0 50 CMOS I Chip Select
TM1 51 CMOS I Digital Interface Selection “0” = 14bits , “1”=7bits*2
TM0 52 CMOS I “0” = RT , “1” = CO
DAC Interface
TX_DATA[13:0] 94~100,
1~7
MCLK 8 CMOS I Master Clock 8.832MHz(Selectable 17.664MHz)
AUXCLK 11 CMOS I In 7bits Data Interface mode, AUXCLK=MCLK/2
TX_DACOP 90 Analog - DAC Current Positive Output for TX path
TX_DACON 89 Analog - DAC Current Negative Output for TX path
COMP_DAC 88 Analog - Compensation Capacitor 0.1uF Connection for TX path
IREF_DAC 87 Analog - External Resistor 1.24k Connection
RX_DATA[13:0] 12 ~ 25 CMOS O ADC 14bit Data Outputs ( If TM1=1, [13:7] is always low)
RX_ADCIP 28 Analog - ADC Positive Input
RX_ADCIN 29 Analog - ADC Negative Input
BGR_ADC 32 Analog - ADC Band gap Reference Output
REFT_ADC 33 Analog - ADC Top Reference Output
REFB_ADC 34 Analog - ADC Bottom Reference Output
SCLK 44 CMOS I Serial Data Clock
SEN 45 CMOS I Serial Data Enable
SDOUT 46 CMOS O Serial Data Output
SDIN 47 CMOS I Serial Data Input
TX_OUTP 78 Analog - Tx Analog Positive Output
TX_OUTN 77 Analog - Tx Analog Positive Output
TX_FINP 85 Analog - Tx Filter Analog Positive Input
TX_FINN 86 Analog - Tx Filter Analog Negative Input
RX_INP 58 Analog - Rx Analog Positive Input
RX_INN 57 Analog - Rx Analog Negative Input
RX_INPG 56 Analog - Rx Analog External -14dB Gain Positive Input
RX_INNG 55 Analog - Rx Analog External -14dB Gain Negative Input
RX_FOUTP 31 Analog - Rx Filter Analog Positive Output
RX_FOUTN 30 Analog - Rx Filter Analog Negative Output
CMOS I DAC 14bit Data Inputs
If TM1=1, TX_DATA[13:7] is invalid
In 14bits Data Interface mode, pin is open or ground.
ADC Interface
DSP Interface
TX Pass Interface
RX Pass Interface
Voltage Reference
CONFIDENTIAL Preliminary Information (Rev.1.0)
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