Samsung S5N8950 Datasheet
S5N8950
G.dmt ADSL Transceiver for CO and CPE
Preliminary Information Rev.1.2
Nov. 2000.
SAMSUNG ELECTRONICS CONFIDENTIAL PROPRIETARY
Copyright ¨Ï 2000 Samsung Electronics, Inc. All Rights Reserved.
S5N8950
G.dmt ADSL Transceiver for CO and CPE
1 General Description
The S5N8950 is an optimized chip of ADSL transceiver supporting G.992.1, G.992.2 and T1.413, and
provides a total chipset solution with AFE chip (S5N8951) for both CO and CPE applications. The
S5N8950 consists of the ATM framer, DMT modem, and DSP core. It supports various interfaces of
UTOPIA level 2 for ATM data and serial interface for Non-ATM data, and host controller compatible
with Motorola and Intel. It is fully compatible with G.Lite and G.dmt standards to satisfy interoperability
with compatible other chipsets. For CO/CPE application, evaluation tool kit shall be provided.
S5N8950
ATM
or
STM
DI AI
DMT
S5N8951
Hybrid
Telephone
Line
Host
DSP RAM PLL
Figure 1: ADSL Transceiver configuration for S5N8950.
G.dmt ADSL Transceiver for CO and CPE
2 Main Features
l Power and performance optimized single port DMT.
l Supports ITU-T G.992.1 (G.dmt) , G.992.2 (G.Lite) and T1.413 standards.
l STM serial interface and ATM UTOPIA level 1 and level 2 interface.
l Supports both the FDM-based and EC-based DMT line coding.
l Analog and digital PLL modes.
l Adaptive frequency and time domain equalizing.
l Provides over 10 Mbps downstream data rate and over 640 Kbps upstream data rate
l Flexible host interface for Motorola and Intel Controller
l Reed-Solomon Forward Error Correction with Interleaving.
l 3-D trellis coding and Viterbi algorithm.
l Supports all of the framing modes.
S5N8950
l Supports Rate Adaptive Mode.
l 12-Bit ADC and DAC with Over-sampling
l Downloadable coefficients of rate-conversion filter banks.
l Low power consumption ( less than 0.5 Watt ).
l Power management
l Self-diagnostics
l 0.18 um 1.8 V CMOS technology.
l 3.3 V external interface.
l Operation Temperature : -40 C to 85 C
l Low Cost & Compact Package (160 QFP)
3 External Pin Description
S5N8950
G.dmt ADSL Transceiver for CO and CPE
ATM interface
U_TX_ADDR[4:0]
U_TX_DATA[7:0]
U_TX_ENB
U_TX_SOC
U_TX_CLK
U_TX_CLAV
U_RX_ADDR[4:0]
U_RX_DATA[7:0]
U_RX_ENB
U_RX_SOC
U_RX_CLK
U_RX_CLAV
STM interface
S1_TX_DAV
S1_TX_CLK
S1_TX_DATA
S1_RX_DAV
S1_RX_CLK
S1_RX_DATA
S2_TX_DAV
S2_TX_CLK
S2_TX_DATA
S2_RX_DAV
S2_RX_CLK
S2_RX_DATA
TeakLite interface
T_MS
T_CLK
T_DI
T_DO
T_INTP
UART interface
UA_TX_DATA
UA_RX_DATA
S5N8950
⇒ ⇐
⇒ ←
→ ←
→ ⇒
→ →
← →
⇒ ←
⇐ ←
→ ←
← →
→ →
← →
←
→
← →
← →
→
←
← ←
← ⇒
← ⇐
← ←
→ ←
← ↔
← ←
← ←
→
→
→
→
→ ←
← ⇒
← ⇔
←
←
← ←
→ →
→
→
AFE interface
A_AD_DATA[6:0]
A_AD_REF_CLK
A_AD_AUX_CLK
A_DA_DATA[6:0]
A_DA_REF_CLK
A_DA_AUX_CLK
A_SDI
A_AND
A_BUSY
A_SCLK
A_SDO
A_SEN
A_PME
A_TX_PWR
A_RX_PWR
A_RSTN
Board/PLL interface
B_RSTN
B_GP_OUT[1:0]
B_BMODE[1:0]
B_TMODE
B_NMODE
B_NTR
B_EXT_CLK
P_XTAL_IN
P_XTAL_OUT
P_PLL_FILTER
Host interface
H_SEL
H_ADDR[9:0]
H_DATA[7:0]
H_CSN
H_RDN
H_WRN
H_READY
H_INT
H_WAKEUP
Figure 2: Pin diagram
U_RX_DATA_5
U_RX_DATA_6
U_RX_DATA_7
U_RX_ADDR_0
VDD3O
VSS3O
U_RX_ADDR_1
U_RX_ADDR_2
U_RX_ADDR_3
U_RX_ADDR_4
U_RX_ENB
U_RX_SOC
U_RX_CLK
U_RX_CLAV
VDD1I
VSS1I
P_VDD18A2
P_VSS18A2
P_PLL_FILTER
P_VDD18A1
P_VSS18A1
P_VBBA
S1_TX_DAV
S1_TX_CLK
VDD3P
VSS3P
S1_RX_DATA
S1_RX_DAV
P_XTAL_IN
P_XTAL_OUT
S1_TX_DATA
S1_RX_CLK
S2_TX_DATA
S2_TX_DAV
VDD1I
VSS1I
S2_TX_CLK
S2_RX_DATA
S2_RX_DAV
S2_RX_CLK
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
U_RX_DATA_4
U_RX_DATA_3
U_RX_DATA_2
U_RX_DATA_1
U_TX_CLK
116
117
118
119
120
G.dmt ADSL Transceiver for CO and CPE
1234576
U_TX_CLAV
VDD1I
VSS1I
113
114
115
8209
S5N8950
G.dmt ADSL Transceiver for CO and CPE
U_TX_DATA_7
U_RX_DATA_0
U_TX_DATA_6
U_TX_SOC
U_TX_DATA_4
109
110
111
112
108
U_TX_DATA_5
T_INTP
U_TX_DATA_3
T_MS
U_TX_ENB
103
104
105
106
107
VDD1I
VDD3P
U_TX_DATA_2
T_DO
VSS3P
H_INT
U_TX_DATA_1
99989796959493929190898887868584838281
100
101
102
VSS1I
U_TX_DATA_0
U_TX_ADDR_4
U_TX_ADDR_3
U_TX_ADDR_2
U_TX_ADDR_1
B_EXT_CLK
VDD3O
U_TX_ADDR_0
VSS3O
B_NTR
T_CLK
S5N8950
1011121314151617181921222324252627282930313233343536373839
B_GP_OUT_1
T_DI
B_GP_OUT_0
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
A_SDI
A_AND
A_SEN
VSS1I
VDD1I
A_SDO
A_SCLK
A_BUSY
A_RX_PWR
A_TX_PWR
A_PME
VSS3P
VDD3P
A_RSTN
A_AD_AUX_CLK
A_AD_REF_CLK
A_AD_DATA_6
A_AD_DATA_5
A_AD_DATA_4
VSS1I
VDD1I
A_AD_DATA_3
A_AD_DATA_2
A_AD_DATA_1
A_AD_DATA_0
A_DA_AUX_CLK
A_DA_REF_CLK
VSS3O
VDD3O
A_DA_DATA_6
A_DA_DATA_5
A_DA_DATA_4
A_DA_DATA_3
A_DA_DATA_2
A_DA_DATA_1
VSS1I
VDD1I
A_AD_DATA_0
UA_RX_DATA
UA_TX_DATA
H_SEL
H_CSN
VDD3O
H_RDN
H_WRN
VSS3O
H_ADDR_0
H_ADDR_1
VDD1I
B_NMODE
H_ADDR_2
H_ADDR_3
VSS1I
H_ADDR_4
H_ADDR_5
H_ADDR_6
B_TMODE
H_ADDR_7
VSS3OP
VDD3OP
H_ADDR_8
H_ADDR_9
Figure 3: Pin configuration
B_RSTN
H_DATA_0
H_DATA_1
H_DATA_2
VSS1I
VDD1I
H_DATA_3
H_DATA_4
H_DATA_5
H_DATA_6
B_MSC_CLK
B_BMODE_0
VSS3P
VDD3P
H_READY
H_DATA_7
H_WAKEUP
B_BMODE_1
S5N8950
G.dmt ADSL Transceiver for CO and CPE
Interface
Type
ATM
interface
STM
interface
Mnemonic Type Driver Function
U_TX_ADDR[4:0] I PHTICD Utopia Tx Address
U_TX_DATA[7:0] I PHTICD Utopia Tx Data
U_TX_ENB I PHTICD Utopia Tx Enable
U_TX_SOC I PHTICD Utopia Tx Start of Cell
U_TX_CLK I PHTICD Utopia Tx Clock. 25 MHz
U_TX_CLAV OZ PHTOT4 Utopia Tx Cell Available
U_RX_ADDR[4:0] I PHTICD Utopia Rx Address[4:0]
U_RX_DATA[7:0] OZ PHTOT4 Utopia Rx Data[7:0]
U_RX_ENB I PHTICD Utopia Rx Enable
U_RX_SOC OZ PHTOT4 Utopia Rx Start of Cell
U_RX_CLK I PHTICD Utopia Rx Clock. 25 MHz
U_RX_CLAV OZ PHTOT4 Utopia Rx Cell Available
S1_TX_DAV O PHOB4 Serial Tx data valid signal in the 1-st STM
S1_TX_CLK O PHOB4 Serial Tx clock in the 1-st STM
S1_TX_DATA I PHTICD Serial Tx data in the 1-st STM
S1_RX_DAV O PHOB4 Serial Rx data valid signal in the 1-st STM
S1_RX_CLK O PHOB4 Serial Rx clock in the 1-st STM
S1_RX_DATA O PHOB4 Serial Rx data in the 1-st STM
S2_TX_DAV O PHOB4 Serial Tx data valid signal in the 2-nd STM
S2_TX_CLK O PHOB4 Serial Tx clock in the 2-nd STM
S2_TX_DATA I PHTICD Serial Tx data in the 2-nd STM
S2_RX_DAV O PHOB4 Serial Rx data valid in the 2-nd STM
S2_RX_CLK O PHOB4 Serial Rx clock in the 2-nd STM
S2_RX_DATA O PHOB4 Serial Rx data in the 2-nd STM
Host
Interface
H_SEL I PHTICD Host type : [0]=Motorola / [1]= Intel
H_ADDR[9:0] I PHTICD Host address bus
H_DATA[7:0] B PHTBCDT6SM Host data bus
H_CSN I PHTICD Chip selection
H_RDN I PHTICD
H_WRN I PHTICD
H_READY OZ PHTOT4
H_INT O PHOB4
H_WAKEUP O PHOB4 Host Wakeup
Motorola Not used.
Intel Read enable ( active low )
Motorola [0]=write enable / [1]=read enable
Intel Write Enable ( active low )
Motorola Host CPU DTACK ( active low )
Intel Host CPU Ready (active high )
Motorola Interrupt IRQ ( active low )
Intel Interrupt INT ( active high )
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