Samsung S5F518NZ03-LEB0 Datasheet
1/5 INCH CCD IMAGE SENSOR FOR NTSC CAMERA S5F518NZ03
ORDERING INFORMATION
H-CCD
INTRODUCTION
The S5F518NZ03 is an interline transfer CCD area image
sensor developed for NTSC 1/5 inch optical format PC
cameras, object detector and image pattern recognizer. High
sensitivity is achieved through the adoption of Ye, Cy, Mg and
G complementary color mosaic filter, on-chip micro lenses.
This chip features a field integration read out system and an
electronic shutter with variable charge storage time.
FEATURES
• Optical Size 1/5 inch Format
• Ye, Cy, Mg, G On-chip Complementary
Color Mosaic Filter
• Horizontal Register 3.3V ~ 5V Drive
• 14pin Ceramic DIP Package
• No Adjust Substrate Bias
• Field Integration Read Out System
• No DC Bias on Reset Gate
14Pin Cer - DIP
Device Package Operating
S5F518NZ03-LEB0 14Pin Cer - DIP
-10 °C − +60 °C
STRUCTURE
• Number of Total Pixels: 381(H) × 506(V)
• Number of Effective Pixels: 362(H) × 492(V)
• Chip Size: 3.75mm(H) × 3.30mm(V)
• Unit Pixel Size: 8.10 µm(H) × 4.45 µm(V)
• Optical Blacks & Dummies: Refer to Figure Below
Vertical 1 Line (Even Field Only)
36 2 17
2 492 12
V-CCD
OUTPU T
14 2
E ffective
Imag ing
A rea
Du mmy P ixe l s
Optical Black Pixels
E ffective Pixels
1
S5F518NZ03 1/5 INCH CCD IMAGE SENSOR FOR NTSC CAMERA
BLOCK DIAGRAM
(Top View)
7
V
OUT
8 9 10 11 12 13 14
V
DD
6 5 4 3 2 1
GND NC
Vertical Shift Register CCD
Cy Ye
Mg
Cy
Cy
G
Cy
Mg
GND
Φ
SUB
Φ
V1
Vertical Shift Register CCD
G
Ye
Ye
Mg
Ye Ye
G
Horizontal Shift Register CCD
V
L
Φ
Φ
Cy
Mg
Cy
Cy
Cy
Mg
RG
V2
G
Φ
Vertical Shift Register CCD
Ye
G
Ye
Ye
Mg
G
Φ
H1
V3
Vertical Shift Register CCD
Figure 1. Block Diagram
Φ
Φ
V4
H2
PIN DESCRIPTION
Table 1. Pin Description
Pin Symbol Description Pin Symbol Description
1
2
3
4
Φ
Φ
Φ
Φ
V4
V3
V2
V1
Vertical register transfer clock 4 8
Vertical register transfer clock 3 9 GND Ground
Vertical register transfer clock 2 10
Vertical register transfer clock 1 11
5 NC No connection 12
6 GND Ground 13
7
2
V
OUT
Signal output 14
Φ
V
Φ
Φ
Φ
DD
SUB
V
L
RG
H1
H2
Output stage drain bias
Substrate clock
Protection circuit bias
Reset gate clock
Horizontal CCD transfer clock 1
Horizontal CCD transfer clock 2
1/5 INCH CCD IMAGE SENSOR FOR NTSC CAMERA S5F518NZ03
ABSOLUTE MAXIMUM RATINGS
(NOTE)
Table 2. Absolute Maximum Ratings
Characteristics Symbols Min. Max. Unit
Substrate voltage SUB - GND -0.3 40 V
Vertical clock input voltage ΦV1, ΦV3, - GND
ΦV2, Φ
ΦV1, ΦV3, - V
ΦV2, Φ
V4
V4
- GND
L
- VL
ΦV1, ΦV2, ΦV3, Φ
Horizontal clock input voltage ΦV1, ΦV2, - GND
Voltage difference between vertical and
horizontal clock input pins
ΦH1, ΦH2 - V
ΦV1, - Φ
ΦV2, - Φ
ΦH1, Φ
L
V3
V4
H2
V4
- SUB
-0.3 30 V
-0.3 17 V
-0.3 30 V
-0.3 17 V
-40 10 V
-0.3 16 V
-0.3 16 V
-30 30 V
-16 16 V
-16 16 V
ΦH1, ΦH2 - Φ
V4
Output clock input voltage ΦRG - GND
Protection circuit bias voltage
Operating temperature
Storage temperature
NOTE: The device can be destroyed, if the applied voltage or temperature is higher than the absolute maximum rating voltage
or temperature.
VL - SUB
T
OP
T
STG
-16 16 V
-0.3 16 V
-40 0.3 V
-10 60 °C
-30 80 °C
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S5F518NZ03 1/5 INCH CCD IMAGE SENSOR FOR NTSC CAMERA
DC CHARACTERISTICS
Table 3. DC Characteristics
Item Symbol Min. Typ. Max. Unit Remar
Output stage drain bias
Reset gate voltage adjustment range
Protection circuit bias voltage
Output stage drain current
CLOCK VOLTAGE CONDITIONS
Table 4. Clock Voltage Conditions
Item Symbol Min. Typ. Max. Unit Remark
Read-out clock voltage
Vertical transfer clock voltage V
VM1
V
VL1
V
VT
− V
− V
V
V
I
VM4
VL4
DD
RGL
V
L
DD
14.55 15.0 15.45 V
0 V
The lowest vertical clock level
5 mA
14.55 15.0 15.45 V High level
-0.05 0.0 0.05 V
-8.5 -8.0 -7.5 V
VVH = (VVH1+V
VVH = (VVH1+V
VH2
VH2
)/2
)/2
Horizontal transfer clock voltage V
Charge reset clock voltage V
V
RGLH - VRGLL
Substrate clock voltage
V
ΦH
V
HL
ΦRG
ΦSUB
3.0 5.0 5.25 V High
-0.05 0.0 0.05 V Low
4.75 5.0 5.25 V High
0.8 V Low
21.5 22.5 23.5 V Shutter
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1/5 INCH CCD IMAGE SENSOR FOR NTSC CAMERA S5F518NZ03
V
=
V
-0.3V
DRIVE CLOCK WAVEFORM CONDITIONS
Read Out Clock Waveform
100%
90%
V
VH1,VVH3
10%
0%
Vertical Transfer Clock Waveform
tr twh tf
0V
¥Õ
V V H 1
¥Õ
V VH2
V 1
V 2
V V H H
V V L 1
V VL
V V H H V VHH
V
VHL
V
V
VH
V V H L
V
VL H
V VL 2
V VL L
VL
VVH= (V
VV L = (VV L 3 + VV L 4)/ 2
V¥ÕV= V
V V H H
V
V VL H
¥Õ
V 3
V
V H L
V V HL
V VHH
V V H L
V
VH3
V VL 3
V
VL L
¥Õ
V 4
VH
V
VHL
V
V
V VL
VH
V VH H
VHL
V V H 4
V
VH H
V
VH
V VL H
V
VL L
V
VH H
V
VHL
V VL H
V
VL L
V
VH 1
+ V
VH 2
VL 4
)/2
V
VH H
= VVH+ 0. 3V
V
VL
VVH L = VV H - 0.3V
VH n
- V
VL n (n = 1 ~4)
V
= V
V L
V L
+ 0. 3V
VL H
VL L
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S5F518NZ03 1/5 INCH CCD IMAGE SENSOR FOR NTSC CAMERA
V
Horizontal Transfer Clock Waveform Diagram
90%
10%
HL
Reset Gate Clock Waveform Diagram
RG waveform
V
RGLH
V
RGLL
tr twh
twl
Point A
V¥Õ
tf
H
twl
twh tftr
V
RGH
V
¥Õ
RG
V
+ 0.5V
RGL
V
RGL
¥Õ
H1 waveform
10%
V
is the maximum value and V
RGLH
in the diagram about to RG rise
V
RGL
= (V
RGLH
+ V
RGLL
)/2, V
Substrate Clock Waveform
V
SU B
FRG
100%
90%
10%
0%
is the minimum value of the coupling waveform in the period from Point A
RGLL
= V
RGH
- V
RGL
¥Õ
V
SU B
twhtr tf
6
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