Samsung S3C9424, S3C9428, S3P9428 Datasheet
S3C9424/C9428/P9428 PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
SAM87RI PRODUCT FAMILY
Samsung’s SAM87Ri family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes.
A address/data bus architecture and a large number of bit-configurable I/O ports provide a flexible programming
environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating
modes are included to support real-time operations.
S3C9424/C9428/P9428 MICROCONTROLLER
The S3C9424/C9428/P9428 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is
built around the powerful SAM87Ri CPU core. The S3C9424/C9428/P9428 is a versatile microcontroller, with its
A/D converter, SIO, IIC and a zero-crossing detection capability it can be used in a wide range of general
purpose applications.
Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register
space, the size of the internal register file was logically expanded. The S3C9424/C9428/P9428 have 4K-byte or
8K-byte of program memory on-chip (ROM) and 208-bytes of general purpose register area RAM.
Using the SAM87Ri design approach, the following peripherals were integrated with the SAM87Ri core:
• Four configurable I/O ports (24 pins)
• Nine interrupt sources with one vector and one interrupt level
• Two 8-bit timer/counter with various operating modes
• Analog to digital converter with 12 input channels and 10-bit resolution
• One synchronous SIO module
• One IIC module
• Two 12-bit PWM output
The S3C9424/C9428/P9428 microcontroller is ideal for use in a wide range of electronic applications requiring
simple timer/counter, PWM, ADC, SIO, IIC, ZCD and capture functions. S3C9424/C9428/P9428 is available in a
28/32-pin SOP and a 30-pin SDIP package.
OTP
The S3P9428 is an OTP (One Time Programmable) version of the S3C9424/C9428 microcontroller. The
S3P9428 has on-chip 8-K-byte one-time-programmable EPROM instead of masked ROM. The S3P9428 is fully
compatible with the S3C9424/C9428, in function, in D.C. electrical characteristics and in pin configuration.
1-1
PRODUCT OVERVIEW S3C9424/C9428/P9428
FEATURES
CPU
• SAM87RI CPU core
Memory
• 208-byte general purpose register area (RAM)
• 4K/8K byte internal program memory (ROM)
Instruction Set
• 41 instructions
• The SAM87RI core provides all the SAM87 core
instruction except the word-oriented instruction,
multiplication, division, and some one-byte
instruction
Instruction Execution Time
• 375 ns at 16 MHz fosc(minimum)
Interrupts
• 9 interrupt sources and 1 vector
• One interrupt level
General I/O
• Four I/O ports (total 24pins)
Timer/Counters
• One 8-bit basic timer for watchdog function
• One 8-bit timer/counter with three operating
mode
• One 8-bit timer/counter
PWM module
• 12-bit PWM 2-ch (Max: 250KHz)
• 6-bit base + 6-bit extension frame
• One 8-bit timer/counter
A/D Converter
• 12 analog input pins
• 10-bit conversion resolution
Buzzer Frequency Range
• 200 Hz to 20 kHz signal can be generated
Oscillator Freqeuncy
• 1-MHz to 16-MHz external crystal oscillator
Maximum 16-MHz CPU clock
• RC: 4MHz(typ)
• Bit programmable ports
Serial I/O
• One synchronous serial I/O module
• Selectable transmit and receive rates
Multi-Master IIC-Bus
• Serial peripheral interface
Zero-Crossing Detection Circuit
• Zero crossing detection circuit that generates a
digital signal in synchronism with an AC signal
input
Built-in reset Circuit (LVD)
• Low voltage detector for safe reset
Operating Temperature Range
• – 40°C to + 85°C
Operating Voltage Range
• 3.0 V to 5.5 V (LVD)
• 1.8 V to 5.5 V (No LVD)
OTP Interface Protocol Spec
• Serial OTP
Package Types
• S3C9424/C9428
32-pin SOP-450 (3V LVD)
30-pin SDIP-400 (3V LVD)
28-pin SOP-375
1-2
S3C9424/C9428/P9428 PRODUCT OVERVIEW
BLOCK DIAGRAM
X
X
OUT
T0 (CAP)
T0(PWM)
AD0-AD11
P1.1/BUZ
P0.0-P0.7
SCK,SO, SI, AD8-AD11
Basic
Timer
IN
OSC
Timer 0
Timer 1
ADC
BUZ
Port 0
Port I/O and Interrupt
Control
SAM87RI CPU
P1.0-P1.3
T0, BUZ, INT0, INT1
Port 1
Port 2
Port 3
ZCD
IIC
P2.0-P2.7
AD0-AD7
P3.0-P3.3
ZCD
P2.7/SCLK
P2.6/SDAT
P0.7/PWM0
P1.3/PWM1
PWM
4K/8K ROM
Register File
Figure 1-1. Block Diagram
208-Byte
SIO
P0.0/SCK
P0.1/SO
P0.2/SI
1-3
PRODUCT OVERVIEW S3C9424/C9428/P9428
PIN ASSIGNMENTS
VSS
XIN
XOUT
TEST
P0.1/SO
P0.0/SCK
RESET
P3.0
P3.2
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5
AVSS
1
2
3
4
5
6
7
S3C9424/C9428
8
9
10
11
12
13
14
15
16
32-SOP
(Top View)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
P0.2/SI
P0.3/CLO
P0.4/AD8
P0.5/AD9
P0.6/AD10
P0.7/AD11/PWM0
P3.1
P3.3
P1.0/T0/ZCD
P1.1/BUZ
P1.2/INT0
P1.3/INT1/PWM1
P2.7/AD7/SCLK
P2.6/AD6/SDAT
AVREF
Figure 1-2. Pin Assignment Diagram (32-Pin SOP Package)
1-4
S3C9424/C9428/P9428 PRODUCT OVERVIEW
PIN ASSIGNMENTS (Continued)
VSS
XIN
XOUT
TEST
P0.1/SO
P0.0/SCK
RESETRESET
P3.0
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5
AVSS
1
2
3
4
5
6
S3C9424/C9428
7
8
9
10
11
12
13
14
15
30-SDIP
(Top View)
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
VDD
P0.2/SI
P0.3/CLO
P0.4/AD8
P0.5/AD9
P0.6/AD10
P0.7/AD11/PWM0
P3.1
P1.0/T0/ZCD
P1.1/BUZ
P1.2/INT0
P1.3/INT1/PWM1
P2.7/AD7/SCLK
P2.6/AD6/SDAT
AVREF
Figure 1-3. Pin Assignment Diagram (30-Pin SDIP Package)
VSS
XIN
XOUT
TEST
P0.1/SO
P0.0/SCK
RESETRESET
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5
AVSS
1
2
3
4
5
6
S3C9424/C9428
7
8
9
10
11
12
13
14
28-SOP
(Top View)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
P0.2/SI
P0.3/CLO
P0.4/AD8
P0.5/AD9
P0.6/AD10
P0.7/AD11/PWM0
P1.0/T0/ZCD
P1.1/BUZ
P1.2/INT0
P1.3/INT1/PWM1
P2.7/AD7/SCLK
P2.6/AD6/SDAT
AVREF
Figure 1-4. Pin Assignment Diagram (28-Pin SOP Package)
1-5
PRODUCT OVERVIEW S3C9424/C9428/P9428
PIN DESCRIPTIONS
Table 1-1. S3C9424/C9428/P9428 Pin Descriptions
Pin
Names
P0.0-P0.7 I/O Bit-programmable I/O port for Schmitt trigger input or push-
P1.0-P1.3 I/O Bit-programmable I/O port for Schmitt trigger input or push-
P2.0-P2.7 I/O Bit-programmable I/O port for Schmitt trigger input or push-
Pin
Type
Pin Description Pin
pull, open-drain output. Pull-up resistors are assignable by
software.
pull output.
Pull-up resistors are assignable by software. Port 1 pins can
also be used as alternative functions.
Share
Type
E
Pins
SCK,SO,SI
, CLO,
E-1
AD8-AD11
D T0/ZCD
BUZ
INT0
INT1
E-1 AD0-AD7
pull, open drain output. Pull up resistors are assignable by
software. Port 2 can also be used as external interrupt, A/D
input.
P3.0-P3.3 O Push-pull or open-drain output port.
E-2 –
Pull-up resistors are assignable by software.
XIN, X
OUT
RESET
TEST I Test signal input pin (for factory use only: must be connected
– Crystal/ceramic, or RC oscillator signal for system clock. – –
I
System RESET signal input pin.
B –
– –
to VSS)
AV
REF
VDD, V
, AV
SS
SS
– A/D converter reference voltage input and ground – –
– Voltage input pin and ground – –
SCK I/O Serial interface clock input or output E P0.0
SO O Serial data output E P0.1
SI I Serial data output E P0.2
CLO O System clock output port E P0.3
SCLK
SDAT
I/O IIC CLOCK
IIC DATA
E-1 P2.7
P2.6
BUZ O 200 Hz-20 kHz frequency output for buzzer sound. D P1.1
ZCD I Zero crossing detector input D P1.0
T0 I/O Timer 0 capture input or 10-bit PWM output D P1.0
INT0
INT1
PWM0
PWM1
I External interrupt input D P1.2
P1.3
O 12-bit PWM output E-1
D
P0.7
P1.3
AD0-AD11 I A/D converter input E-1 P2.0-P2.7
P0.4-P0.7
1-6
S3C9424/C9428/P9428 PRODUCT OVERVIEW
PIN CIRCUITS
VDD
P-Channel
In
N-Channel
Figure 1-5. Pin Circuit Type A
VDD
Pull-Up
Resistor
In
Data
Output
DIsable
Resistor
Enable
Output
DIsable
VDD
Figure 1-7. Pin Circuit Type C
VDD
Pull-up
Resistor
P-Channel
Data
Circuit
Type C
P-Channel
Out
N-Channel
I/O
Figure 1-6. Pin Circuit Type B
Data
Figure 1-8. Pin Circuit Type D
1-7
PRODUCT OVERVIEW S3C9424/C9428/P9428
V
DD
DD
V
47K
VDD
PNE
Pull-up
DD
V
Resistor
PNE
Data
Output
Disable
Data
Input
Figure 1-9. Pin Circuit Type E
PNE
V
DD
P-CH
N-CH
P-CH
V
DD
Pull-up
Enable
I/O
Pull-up
Resistor
Pull-up
Enable
I/O
Data
Output
Disable
Pull-up
Enable
Out
Figure 1-11. Pin Circuit Type E-2
Output
Disable
Analog Input
1-8
N-CH
Input
Figure 1-10. Pin Circuit Type E-1
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