Samsung S3F84VB User Manual

USER'S MANUAL

S3F84VB

8-BIT CMOS MICROCONTROLLERS

September, 2008

REV 1.00

Confidential Proprietary of Samsung Electronics Co., Ltd

Copyright © 2008 Samsung Electronics, Inc. All Rights Reserved

Important Notice

The information in this publication has been carefully
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the time of publication. Samsung assumes no
responsibility, however, for possible errors or
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the use of the information contained herein.

Samsung reserves the right to make changes in its
products or product specifications with the intent to
improve function or design at any time and without
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documentation to reflect such changes.

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semiconductor devices described herein any license
under the patent rights of Samsung or others.

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guarantee regarding the suitability of its products for
any particular purpose, nor does Samsung assume
any liability arising out of the application or use of
any product or circuit and specifically disclaims any
and all liability, including without limitation any
consequential or incidental damages.

S3F84VB 8-Bit CMOS Microcontrollers
User's Manual, Revision 1.00
Publication Number: 21.00-S3-F84VB-092008

"Typical" parameters can and do vary in different
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NOTIFICATION OF REVISIONS

ORIGINATOR: Samsung Electronics, LSI Development Group, Gi-Heung, South Korea

PRODUCT NAME: S3F84VB 8-bit CMOS Microcontroller

DOCUMENT NAME: S3F84VB User's Manual, Revision 1.00

DOCUMENT NUMBER: 21.00-S3- S3F84VB -092008

EFFECTIVE DATE: September, 2008

SUMMARY: As a result of additional product testing and evaluation, some specifications

published in S3F84VB User's Manual, Revision 0.00, have been changed.
These changes for in S3F84VB microcontroller, which are
described in detail in the Revision Descriptions section below, are related
to the followings:

— Chapter 4. Control Registers
— Chapter 15. LCD Controller/Driver
— Chapter 22. Electrical Data

DIRECTIONS: Please note the changes in your copy (copies) of the S3F84VB

User’s Manual, Revision 0.00. Or, simply attach the Revision Descriptions of the
next page to S3F84VB User’s Manual, Revision 0.00

REVISION HISTORY

Revision Remark Author(s) Date

0.00 Preliminary Spec for internal release only. Bum-Sun Hong August, 2008

1.00 First edition. Bum-Sun Hong August, 2008

REVISION DESCRIPTIONS (Rev 1.00)

CHAPTHER 22. ELECTRICAL DATA

Table 22-2. D.C. Electrical Characteristics (Continued)

(T

= – 40

A

°

C to + 85

°

C, VDD = 2.0 V to 5.5 V)

Parameter Symbol Conditions Min Typ Max Unit

Supply current

(1)

I

DD5

(4)

Stop mode:

=25°C, VDD = 5.0V

T

A

TA= 85°C, VDD = 5.0V
TA= - 40°C to + 85°C

VDD = 5.0V

–

2.5 6.0

7.5 15.0

–

15.0

LCD CONTROLLER/DRIVER

Added note “The P5.3/VLC3-P5.0/VLC0 must be used as LCD bias pins if the LCD block is used. So, the
LCON.2-.1 must not be set to '00b' when LCON.0=1” in the page 4-18 and page 15-4

Preface

The S3F84VB Microcontroller User's Manual is designed for application designers and programmers who are
using the S3F84VB microcontroller for application development. It is organized in two main parts:

Part I Programming Model Part II Hardware Descriptions
Part I contains software-related information to familiarize you with the microcontroller's architecture, programming

model, instruction set, and interrupt structure. It has six chapters:
Chapter 1 Product Overview

Chapter 2 Address Spaces
Chapter 3 Addressing Modes

Chapter 1, "Product Overview," is a high-level introduction to S3F84VB with general product descriptions, as well
as detailed information about individual pin characteristics and pin circuit types.

Chapter 2, "Address Spaces," describes program and data memory spaces, the internal register file, and register
addressing. Chapter 2 also describes working register addressing, as well as system stack and user-defined
stack operations.

Chapter 3, "Addressing Modes," contains detailed descriptions of the addressing modes that are supported by the
S3F8-series CPU.

Chapter 4, "Control Registers," contains overview tables for all mapped system and peripheral control register
values, as well as detailed one-page descriptions in a standardized format. You can use these easy-to-read,
alphabetically organized, register descriptions as a quick-reference source when writing programs.

Chapter 5, "Interrupt Structure," describes the S3F84VB interrupt structure in detail and further prepares you for
additional information presented in the individual hardware module descriptions in Part II.

Chapter 6, "Instruction Set," describes the features and conventions of the instruction set used for all S3F8-series
microcontrollers. Several summary tables are presented for orientation and reference. Detailed descriptions of
each instruction are presented in a standard format. Each instruction description includes one or more practical
examples of how to use the instruction when writing an application program.

A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in
Part II. If you are not yet familiar with the S3F8-series microcontroller family and are reading this manual for the
first time, we recommend that you first read Chapters 1−3 carefully. Then, briefly look over the detailed
information in Chapters 4, 5, and 6. Later, you can reference the information in Part I as necessary.

Chapter 4 Control Registers
Chapter 5 Interrupt Structure
Chapter 6 Instruction Set

Part II "hardware Descriptions," has detailed information about specific hardware components of the S3F84VB
microcontroller. Also included in Part II are electrical, mechanical, Flash, and development tools data. It has 19
chapters:

Chapter 7 Clock Circuit
Chapter 8 RESET and Power-Down
Chapter 9 I/O Ports
Chapter 10 Basic Timer
Chapter 11 8-bit Timer A/B
Chapter 12 8-bit Timer C
Chapter 13 16-bit Timer D0/D1
Chapter 14 Watch Timer
Chapter 15 LCD Controller/Driver
Chapter 16 10-bit-Analog-to-Digital Converter

S3F84VB_UM_REV1.00 MICROCONTROLLER iii

Chapter 17 Serial I/O Interface
Chapter 18 UART 0
Chapter 19 UART 1
Chapter 20 Pattern Generator Module
Chapter 21 Embedded Flash Memory
Chapter 22 Electrical Data
Chapter 23 Mechanical Data
Chapter 24 S3F84VB Flash MCU
Chapter 25 Development Tools

Table of Contents

Part I − Programming Model

Chapter 1 Product Overview

S3C8-Series Microcontrollers .......................................................................................................................1-1

S3F84VB Microcontroller ..............................................................................................................................1-1

Features ........................................................................................................................................................1-2

Block Diagram...............................................................................................................................................1-4

Pin Assignment .............................................................................................................................................1-5

Pin Descriptions ............................................................................................................................................1-7

Pin Circuits ....................................................................................................................................................1-11

Chapter 2 Address Spaces

Overview........................................................................................................................................................2-1

Program Memory (ROM)...............................................................................................................................2-2

Smart option .........................................................................................................................................2-3

Register Architecture.....................................................................................................................................2-4

Register Set 1.......................................................................................................................................2-8

Register Set 2.......................................................................................................................................2-8

Prime Register Space...........................................................................................................................2-9

Working Registers ................................................................................................................................2-10

Using the Register Points.....................................................................................................................2-11

Register Addressing......................................................................................................................................2-13

Common Working Register Area (C0H−CFH) .....................................................................................2-15

4-bit Working Register Addressing.......................................................................................................2-16

8-bit Working Register Addressing.......................................................................................................2-18

System and User Stack.................................................................................................................................2-20

S3F84VB_UM_REV1.00 MICROCONTROLLER v

Table of Contents (Continued)

Chapter 3 Addressing Modes

Overview....................................................................................................................................................... 3-1

Register Addressing Mode (R)..................................................................................................................... 3-2

Indirect Register Addressing Mode (IR).......................................................................................................3-3

Indexed Addressing Mode (X)...................................................................................................................... 3-7

Direct Address Mode (DA)............................................................................................................................ 3-10

Indirect Address Mode (IA)...........................................................................................................................3-12

Relative Address Mode (RA)........................................................................................................................ 3-13

Immediate Mode (IM).................................................................................................................................... 3-14

Chapter 4 Control Registers

Overview....................................................................................................................................................... 4-1

Chapter 5 Interrupt Structure

Overview....................................................................................................................................................... 5-1

Interrupt Types..................................................................................................................................... 5-2

S3F84VB Interrupt Structure................................................................................................................ 5-3

Interrupt Vector Addresses..................................................................................................................5-5

Enable/Disable Interrupt Instructions (EI, DI) ...................................................................................... 5-7

System-Level Interrupt Control Registers............................................................................................5-7

Interrupt Processing Control Points..................................................................................................... 5-8

Peripheral Interrupt Control Registers.................................................................................................5-9

System Mode Register (SYM) ............................................................................................................. 5-11

Interrupt Mask Register (IMR) ............................................................................................................. 5-12

Interrupt Priority Register (IPR)............................................................................................................ 5-13

Interrupt Request Register (IRQ).........................................................................................................5-15

Interrupt Pending Function Types........................................................................................................ 5-16

Interrupt Source Polling Sequence...................................................................................................... 5-17

Interrupt Service Routines ................................................................................................................... 5-17

Generating interrupt Vector Addresses ............................................................................................... 5-18

Nesting of Vectored Interrupts............................................................................................................. 5-18

Instruction Pointer (IP).........................................................................................................................5-18

Fast Interrupt Processing.....................................................................................................................5-18

Chapter 6 Instruction Set

Overview....................................................................................................................................................... 6-1

Data Types...........................................................................................................................................6-1

Register Addressing............................................................................................................................. 6-1

Addressing Modes...............................................................................................................................6-1

Flags Register (FLAGS)....................................................................................................................... 6-6

Flag Descriptions ................................................................................................................................. 6-7

Instruction Set Notation........................................................................................................................ 6-8

Condition Codes .................................................................................................................................. 6-12

Instruction Descriptions........................................................................................................................ 6-13

vi S3F84VB_UM_REV1.00 MICROCONTROLLER

Table of Contents (Continued)

Part II Hardware Descriptions

Chapter 7 Clock Circuit

Overview........................................................................................................................................................7-1

System clock Circuit .............................................................................................................................7-1

CPU Clock Notation..............................................................................................................................7-1

Main Oscillator Circuits.........................................................................................................................7-2

Sub Oscillator Circuits ..........................................................................................................................7-2

Clock Status During Power-Down Modes............................................................................................7-3

System Clock Control Register (CLKCON)..........................................................................................7-4

STOP CONTROL Register (STPCON)................................................................................................7-6

Switching the CPU Clock......................................................................................................................7-7

Chapter 8 RESET and Power-Down

System Reset................................................................................................................................................8-1

Overview...............................................................................................................................................8-1

Normal Mode Reset Operation.............................................................................................................8-1

Hardware Reset Values........................................................................................................................8-2

Power-Down Modes......................................................................................................................................8-6

Stop Mode ............................................................................................................................................8-6

Idle Mode..............................................................................................................................................8-7

Chapter 9 I/O Ports

Overview........................................................................................................................................................9-1

Port Data Registers ..............................................................................................................................9-3

Port 0 ....................................................................................................................................................9-4

Port 1 ....................................................................................................................................................9-6

Port 2 ....................................................................................................................................................9-9

Port 3 ....................................................................................................................................................9-13

Port 4 ....................................................................................................................................................9-16

Port 5 ....................................................................................................................................................9-20

Port 6 ....................................................................................................................................................9-22

Chapter 10 Basic Timer

Overview........................................................................................................................................................10-1

Basic Timer (BT)...................................................................................................................................10-1

basic Timer Control Register (BTCON)................................................................................................10-2

Basic Timer Function Description.........................................................................................................10-3

S3F84VB_UM_REV1.00 MICROCONTROLLER vii

Table of Contents (Continued)

Chapter 11 8-Bit Timer A/B

8-bit Timer A.................................................................................................................................................11-1

Overview..............................................................................................................................................11-1

Timer A Control Register (TACON).....................................................................................................11-2

Timer A Function Description............................................................................................................... 11-3

Block Diagram...................................................................................................................................... 11-6

8-Bit Timer B.................................................................................................................................................11-7

Overview..............................................................................................................................................11-7

Block Diagram...................................................................................................................................... 11-8

Timer B Pulse Width Calculations ....................................................................................................... 11-9

Chapter 12 8-Bit Timer C

8-bit Timer C................................................................................................................................................. 12-1

Overview..............................................................................................................................................12-1

Timer C Control Register (TCCON).....................................................................................................12-2

Block Diagram...................................................................................................................................... 12-3

Chapter 13 16-Bit Timer D0/D1

16-bit Timer D0............................................................................................................................................. 13-1

Overview..............................................................................................................................................13-1

Timer D0 Control Register (TD0CON)............................................................................................. ....13-2

Timer D0 Function Description ............................................................................................................ 13-3

Block Diagram...................................................................................................................................... 13-6

16-bit Timer D1............................................................................................................................................. 13-7

Overview..............................................................................................................................................13-7

Timer D1 Control Register (TD1CON)............................................................................................. ....13-8

Timer D1 Function Description ............................................................................................................ 13-9

Block Diagram...................................................................................................................................... 13-12

Chapter 14 Watch Timer

Overview....................................................................................................................................................... 14-1

Watch Timer Control Register (WTCON) ............................................................................................ 14-2

Watch Timer Circuit Diagram............................................................................................................... 14-3

viii S3F84VB_UM_REV1.00 MICROCONTROLLER

Table of Contents (Continued)

Chapter 15 LCD Controller/Driver

Overview........................................................................................................................................................15-1

LCD Circuit Diagram.............................................................................................................................15-2

LCD RAM Address Area.......................................................................................................................15-3

LCD Control Register (lCON)...............................................................................................................15-4

LCD Mode Control Register (lMOD).....................................................................................................15-5

Internal Resistor Bias Pin Connection..................................................................................................15-6

External Resistor Bias Pin Connection.................................................................................................15-7

Capacitor Bias Pin Connection.............................................................................................................15-8

Common (COM) Signals ......................................................................................................................15-9

Segment (SEG) Signals .......................................................................................................................15-9

Chapter 16 10-Bit Analog-to-Digital Converter

Overview........................................................................................................................................................16-1

Function Description......................................................................................................................................16-1

Conversion Timing................................................................................................................................16-2

A/D Converter Control Register (ADCON)...........................................................................................16-2

Internal Reference Voltage Levels .......................................................................................................16-3

Block Diagram...............................................................................................................................................16-4

Chapter 17 Serial I/O Interface

Overview........................................................................................................................................................17-1

Programming Procedure ......................................................................................................................17-1

SIO Control Register (SIOCON)...........................................................................................................17-2

SIO Pre-Scaler Register (SIOPS).........................................................................................................17-3

Block Diagram...............................................................................................................................................17-3

Serial I/O Timing Diagram....................................................................................................................17-4

Chapter 18 UART 0

Overview........................................................................................................................................................18-1

Programming Procedure ......................................................................................................................18-1

UART 0 high-byte Control Register (UART0CONH)............................................................................18-2

UART 0 low-byte Control Register (UART0CONL)..............................................................................18-2

UART 0 Interrupt Pending bits..............................................................................................................18-4

UART 0 Data Register (UDATA0)........................................................................................................18-5

UART 0 Baud Rate Data Register (BRDATA0)....................................................................................18-5

Baud Rate Calculations........................................................................................................................18-5

Block Diagram...............................................................................................................................................18-7

UART 0 Mode 0 Function Description..................................................................................................18-8

Serial Port Mode 1 Function Description..............................................................................................18-9

Serial Port Mode 2 Function Description..............................................................................................18-10

Serial Port Mode 3 Function Description..............................................................................................18-11

Serial Communication for Multiprocessor Configurations....................................................................18-12

S3F84VB_UM_REV1.00 MICROCONTROLLER ix

Table of Contents (Continued)

Chapter 19 UART 1

Overview....................................................................................................................................................... 19-1

Programming Procedure......................................................................................................................19-1

UART 1 high-byte Control Register (UART1CONH)...........................................................................19-2

UART 1 low-byte Control Register (UART1CONL).............................................................................19-2

UART 1 Interrupt Pending bits............................................................................................................. 19-4

UART 1 Data Register (UDATA1) ....................................................................................................... 19-5

UART 1 Baud Rate Data Register (BRDATA1)................................................................................... 19-5

Baud Rate Calculations ....................................................................................................................... 19-5

Block Diagram .............................................................................................................................................. 19-7

UART 1 Mode 0 Function Description.................................................................................................19-8

Serial Port Mode 1 Function Description.............................................................................................19-9

Serial Port Mode 2 Function Description.............................................................................................19-10

Serial Port Mode 3 Function Description.............................................................................................19-11

Serial Communication for Multiprocessor Configurations ................................................................... 19-12

Chapter 20 Pattern Generation Module

Overview....................................................................................................................................................... 20-1

PAttern Gneration Flow........................................................................................................................ 20-1

Chapter 21 Embedded Flash Memory Interface

Overview....................................................................................................................................................... 21-1

User Program Mode ..................................................................................................................................... 21-2

Flash Memory Control Registers (User Program Mode)..................................................................... 21-3

TM

(On-Board Programming) Sector....................................................................................................... 21-6

ISP

ISP Reset Vector and ISP Sector Size................................................................................................ 21-7

Sector Erase................................................................................................................................................. 21-8

Programming................................................................................................................................................21-10

Reading ........................................................................................................................................................ 21-12

Hard Lock Protection.................................................................................................................................... 21-13

Chapter 22 Electrical Data

Overview....................................................................................................................................................... 22-1

Chapter 23 Mechanical Data

Overview....................................................................................................................................................... 23-1

x S3F84VB_UM_REV1.00 MICROCONTROLLER

Table of Contents (Concluded)

Chapter 24 S3F84VB Flash MCU

Overview........................................................................................................................................................24-1

On Board Writing...........................................................................................................................................24-5

Chapter 25 Development Tools

Overview........................................................................................................................................................25-1

Target Boards.......................................................................................................................................25-1

Programming Socket Adapter ..............................................................................................................25-1

TB84VB Target Board ..........................................................................................................................25-3

Third parties for Development Tools ....................................................................................................25-8

OTP/MTP Programmer (Writer)............................................................................................................25-9

S3F84VB_UM_REV1.00 MICROCONTROLLER xi

List of Figures

Figure Title Page
Number Number

1-1 Block Diagram............................................................................................................1-4

1-2 S3F84VB Pin Assignments (64-QFP-1420F).............................................................1-5

1-3 S3F84VB Pin Assignments (64-SDIP-750)................................................................1-6

1-4 Pin Circuit Type A.......................................................................................................1-11

1-5 Pin Circuit Type B.......................................................................................................1-11

1-6 Pin Circuit Type C.......................................................................................................1-11

1-7 Pin Circuit Type D-2 (P5.6–P5.7)...............................................................................1-11

1-8 Pin Circuit Type F-16 (P4)..........................................................................................1-12

1-9 Pin Circuit Type F-17 (P5.0 - P5.5) ............................................................................1-12

1-10 Pin Circuit Type H-39 .................................................................................................1-13

1-11 Pin Circuit Type H-43 (P2)..........................................................................................1-13

1-12 Pin Circuit Type H-44 (P0)..........................................................................................1-14

1-13 Pin Circuit Type H-42 (P1, P3, P6).............................................................................1-14

2-1 Program Memory Address Space..............................................................................2-2

2-2 Smart Option...............................................................................................................2-3

2-3 Internal Register File Organization (S3F84VB)..........................................................2-5

2-4 Register Page Pointer (PP)........................................................................................2-6

2-5 Set 1, Set 2, Prime Area Register, and LCD Data Register Map...............................2-9

2-6 8-Byte Working Register Areas (Slices).....................................................................2-10

2-7 Contiguous 16-Byte Working Register Block.............................................................2-11

2-8 Non-Contiguous 16-Byte Working Register Block .....................................................2-12

2-9 16-Bit Register Pair ....................................................................................................2-13

2-10 Register File Addressing ............................................................................................2-14

2-11 Common Working Register Area................................................................................2-15

2-12 4-Bit Working Register Addressing ............................................................................2-17

2-13 4-Bit Working Register Addressing Example .............................................................2-17

2-14 8-Bit Working Register Addressing ............................................................................2-18

2-15 8-Bit Working Register Addressing Example .............................................................2-19

2-16 Stack Operations........................................................................................................2-20

3-1 Register Addressing...................................................................................................3-2

3-2 Working Register Addressing.....................................................................................3-2

3-3 Indirect Register Addressing to Register File.............................................................3-3

3-4 Indirect Register Addressing to Program Memory.....................................................3-4

3-5 Indirect Working Register Addressing to Register File ..............................................3-5

3-6 Indirect Working Register Addressing to Program or Data Memory..........................3-6

3-7 Indexed Addressing to Register File ..........................................................................3-7

3-8 Indexed Addressing to Program or Data Memory with Short Offset..........................3-8

3-9 Indexed Addressing to Program or Data Memory......................................................3-9

3-10 Direct Addressing for Load Instructions .....................................................................3-10

3-11 Direct Addressing for Call and Jump Instructions......................................................3-11

3-12 Indirect Addressing.....................................................................................................3-12

3-13 Relative Addressing....................................................................................................3-13

3-14 Immediate Addressing................................................................................................3-14

S3F84VB_UM_REV1.00 MICROCONTROLLER xiii

List of Figures (Continued)

Figure Title Page
Number Number

4-1 Register Description Format...................................................................................... 4-5

5-1 S3C8-Series Interrupt Types..................................................................................... 5-2

5-2 S3F84VB Interrupt Structure ..................................................................................... 5-4

5-3 ROM Vector Address Area ........................................................................................ 5-5

5-4 Interrupt Function Diagram........................................................................................ 5-8

5-5 System Mode Register (SYM) ................................................................................... 5-11

5-6 Interrupt Mask Register (IMR) ................................................................................... 5-12

5-7 Interrupt Request Priority Groups.............................................................................. 5-13

5-8 Interrupt Priority Register (IPR) ................................................................................. 5-14

5-9 Interrupt Request Register (IRQ)...............................................................................5-15

6-1 System Flags Register (FLAGS) ............................................................................... 6-6

7-1 Crystal/Ceramic Oscillator (fX) .................................................................................. 7-2

7-2 External Oscillator (fX)............................................................................................... 7-2

7-3 RC Oscillator (fX)....................................................................................................... 7-2

7-4 Crystal Oscillator (fxt)................................................................................................. 7-2

7-5 External Oscillator (fxt)............................................................................................... 7-2

7-6 System Clock Circuit Diagram................................................................................... 7-3

7-7 System Clock Control Register (CLKCON)............................................................... 7-4

7-8 Oscillator Control Register (OSCCON) ..................................................................... 7-5

7-9 STOP Control Register (STPCON)............................................................................ 7-6

xiv S3F84VB_UM_REV1.00 MICROCONTROLLER

List of Figures (Continued)

Figure Title Page
Number Number

9-1 Port 0 High-Byte Control Register (P0CONH) ...........................................................9-4

9-2 Port 0 Low-Byte Control Register (P0CONL).............................................................9-5

9-3 Port 1 High-Byte Control Register (P1CONH) ...........................................................9-6

9-4 Port 1 Low-Byte Control Register (P1CONL).............................................................9-7

9-5 Port 1 Pull-up Resistor Enable Register (P1PUR).....................................................9-7

9-6 Port 1 N-Channel Open-drain Mode Register (PNE1)...............................................9-8

9-7 Port 2 High-Byte Control Register (P2CONH) ...........................................................9-10

9-8 Port 2 Low-Byte Control Register (P2CONL).............................................................9-10

9-9 Port 2 High-Byte Interrupt Control Register (P2INTH)...............................................9-11

9-10 Port 2 Low-Byte Interrupt Control Register (P2INTL).................................................9-11

9-11 Port 2 Interrupt Pending Register (P2PND) ...............................................................9-12

9-12 Port 3 High-Byte Control Register (P3CONH) ...........................................................9-13

9-13 Port 3 Middle-Byte Control Register (P3CONM)........................................................9-14

9-14 Port 3 Low-Byte Control Register (P3CONL).............................................................9-14

9-15 Port 3 Pull-up Resistor Enable Register (P3PUR).....................................................9-15

9-16 Port 3 N-Channel Open-drain Mode Register (PNE3)...............................................9-15

9-17 Port 4 High-Byte Control Register (P4CONH) ...........................................................9-17

9-18 Port 4 Low-Byte Control Register (P4CONL).............................................................9-17

9-19 Port 4 High-Byte Interrupt Control Register (P4INTH)...............................................9-18

9-20 Port 4 Low-Byte Interrupt Control Register (P4INTL).................................................9-18

9-21 Port 4 Interrupt Pending Register (P4PND) ...............................................................9-19

9-22 Port 5 High-Byte Control Register (P5CONH) ...........................................................9-20

9-23 Port 5 Low-Byte Control Register (P5CONL).............................................................9-21

9-24 Port 6 High-byte Control Register (P6CONH)............................................................9-22

9-25 Port 6 Low-byte Control Register (P6CONL).............................................................9-23

9-26 Port 6 Pull-up Resistor Enable Register (P6PUR).....................................................9-23

9-27 Port 6 N-Channel Open-drain Mode Register (PNE6)...............................................9-24

S3F84VB_UM_REV1.00 MICROCONTROLLER xv

List of Figures (Continued)

Page Title Page
Number Number

10-1 Basic Timer Control Register (BTCON)..................................................................... 10-2

10-2 Basic Timer Block Diagram ....................................................................................... 10-4

11-1 Timer A Control Register (TACON)...........................................................................11-2

11-2 Simplified Timer A Function Diagram: Interval Timer Mode...................................... 11-3

11-3 Simplified Timer A Function Diagram: PWM Mode................................................... 11-4

11-4 Simplified Timer A Function Diagram: Capture Mode............................................... 11-5

11-5 Timer A Functional Block Diagram............................................................................ 11-6

11-6 Timer B Control Register ........................................................................................... 11-7

11-7 Timer B Functional Block Diagram............................................................................ 11-8

11-8 Timer B Output Flip-Flop Waveforms in Repeat Mode.............................................. 11-10

12-1 Timer C Control Register (TCCON)........................................................................... 12-2

12-2 Timer C Function Block Diagram...............................................................................12-3

13-1 Timer D0 Control Register (TD0CON)....................................................................... 13-2

13-2 Simplified Timer D0 Function Diagram: Interval Timer Mode.................................... 13-3

13-3 Simplified Timer D0 Function Diagram: PWM Mode................................................. 13-4

13-4 Simplified Timer D0 Function Diagram: Capture Mode............................................. 13-5

13-5 Timer D0 Functional Block Diagram.......................................................................... 13-6

13-6 Timer D1 Control Register (TD1CON)....................................................................... 13-8

13-7 Simplified Timer D1 Function Diagram: Interval Timer Mode.................................... 13-9

13-8 Simplified Timer D1 Function Diagram: PWM Mode................................................. 13-10

13-9 Simplified Timer D1 Function Diagram: Capture Mode............................................. 13-11

13-10 Timer D1 Functional Block Diagram.......................................................................... 13-12

14-1 Watch Timer Control Register (WTCON)..................................................................14-2

14-2 Watch Timer Circuit Diagram..................................................................................... 14-3

15-1 LCD Function Diagram .............................................................................................. 15-1

15-2 LCD Circuit Diagram.................................................................................................. 15-2

15-3 LCD Display Data RAM Organization........................................................................ 15-3

15-4 LCD Control Register (LCON)................................................................................... 15-4

15-5 LCD Mode Control Register (LMOD)......................................................................... 15-5

15-6 Internal Resistor Bias Pin Connection....................................................................... 15-6

15-7 External Resistor Bias Pin Connection...................................................................... 15-7

15-8 Capacitor Bias Pin Connection.................................................................................. 15-8

15-9 Select/No-Select Signal in 1/2 Duty, 1/2 Bias Display Mode..................................... 15-10

15-10 Select/No-Select Signal in 1/3 Duty, 1/3 Bias Display Mode..................................... 15-10

15-11 LCD Signal Waveforms (1/2 Duty, 1/2 Bias) ............................................................. 15-11

15-12 LCD Signal Waveforms (1/3 Duty, 1/3 Bias) ............................................................. 15-12

15-13 LCD Signal Waveforms (1/4 Duty, 1/3 Bias) ............................................................. 15-13

15-14 LCD Signal Waveforms (1/8 Duty, 1/4 Bias) ............................................................. 15-14

xvi S3F84VB_UM_REV1.00 MICROCONTROLLER

List of Figures (Continued)

Page Title Page
Number Number

16-1 A/D Converter Control Register (ADCON).................................................................16-2

16-2 A/D Converter Data Register (ADDATAH/L)..............................................................16-3

16-3 A/D Converter Functional Block Diagram...................................................................16-4

16-4 Recommended A/D Converter Circuit for Highest Absolute Accuracy ......................16-5

17-1 Serial I/O Module Control Registers (SIOCON).........................................................17-2

17-2 SIO Pre-scaler Register (SIOPS)...............................................................................17-3

17-3 SIO Functional Block Diagram ...................................................................................17-3

17-4 Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0) ..............17-4

17-5 Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1)...............17-4

18-1 UART 0 High Byte Control Register (UART0CONH).................................................18-3

18-2 UART 0 Low Byte Control Register (UART0CONL) ..................................................18-4

18-3 UART 0 Data Register (UDATA0)..............................................................................18-5

18-4 UART 0 Baud Rate Data Register (BRDATA0) .........................................................18-5

18-5 UART 0 Functional Block Diagram.............................................................................18-7

18-6 Timing Diagram for Serial Port Mode 0 Operation.....................................................18-8

18-7 Timing Diagram for Serial Port Mode 1 Operation.....................................................18-9

18-8 Timing Diagram for Serial Port Mode 2 Operation.....................................................18-10

18-9 Timing Diagram for Serial Port Mode 3 Operation.....................................................18-11

18-10 Connection Example for Multiprocessor Serial Data Communications .....................18-13

19-1 UART 1 High Byte Control Register (UART1CONH).................................................19-3

19-2 UART 1 Low Byte Control Register (UART1CONL) ..................................................19-4

19-3 UART 1 Data Register (UDATA1)..............................................................................19-5

19-4 UART 1 Baud Rate Data Register (BRDATA1) .........................................................19-5

19-5 UART 1 Functional Block Diagram.............................................................................19-7

19-6 Timing Diagram for Serial Port Mode 0 Operation.....................................................19-8

19-7 Timing Diagram for Serial Port Mode 1 Operation.....................................................19-9

19-8 Timing Diagram for Serial Port Mode 2 Operation.....................................................19-10

19-9 Timing Diagram for Serial Port Mode 3 Operation.....................................................19-11

19-10 Connection Example for Multiprocessor Serial Data Communications .....................19-13

20-1 Pattern Generation Flow.............................................................................................20-1

20-2 Pattern Generation Control Register (PGCON).........................................................20-2

20-3 Pattern Generation Circuit Diagram...........................................................................20-2

21-1 Flash Memory Control Register (FMCON).................................................................21-3

21-2 Flash Memory User Programming Enable Register (FMUSR) ..................................21-4

21-3 Flash Memory Sector Address Register High Byte (FMSECH).................................21-5

21-4 Flash Memory Sector Address Register Low Byte (FMSECL) ..................................21-5

21-5 Program Memory Address Space..............................................................................21-6

21-6 Sector Configurations in User Program Mode ...........................................................21-8

S3F84VB_UM_REV1.00 MICROCONTROLLER xvii

List of Figures (Concluded)

Page Title Page
Number Number

22-1 Input Timing for External Interrupts ........................................................................... 22-6

22-2 Input Timing for nRESET........................................................................................... 22-6

22-3 Stop Mode Release Timing Initiated by nRESET......................................................22-8

22-4 Stop Mode Release Timing Initiated by Interrupts..................................................... 22-8

22-5 LVR (Low Voltage Reset) Timing .............................................................................. 22-10

22-6 Serial Data Transfer Timing....................................................................................... 22-11

22-7 Waveform for UART Timing Characteristics.............................................................. 22-12

22-8 Timing Waveform for the UART Module.................................................................... 22-13

22-9 Clock Timing Measurement at XIN............................................................................ 22-15

22-10 Clock Timing Measurement at XTIN.......................................................................... 22-15

22-11 Operating Voltage Range .......................................................................................... 22-16

23-1 Package Dimensions (64-QFP-1420F) ..................................................................... 23-1

23-2 Package Dimensions (64-SDIP-750)......................................................................... 23-2

24-1 S3F84VB Pin Assignments (64-QFP-1420F)............................................................ 24-2

24-2 S3F84VB Pin Assignments (64-SDIP-750)...............................................................24-3

24-3 RC Delay Circuit ........................................................................................................ 24-4

24-4 PCB design guide for on board programming...........................................................24-5

25-1 Emulator Product Configuration................................................................................. 25-2

25-2 TB84VB Target Board Configuration......................................................................... 25-3

25-3 40-Pin Connectors (J101, J102) for TB84VB............................................................25-6

25-4 S3E84Z0 Cables for 64-QFP Package......................................................................25-7

xviii S3F84VB_UM_REV1.00 MICROCONTROLLER

List of Tables

Table Title Page
Number Number

1-1 S3F84VB Pin Descriptions.........................................................................................1-7

2-1 S3F84VB Register Type Summary............................................................................2-4

4-1 Set 1 Registers...........................................................................................................4-1

4-2 Set 1, Bank 0 Registers..............................................................................................4-2

4-3 Set 1, Bank 1 Registers..............................................................................................4-3

4-4 Page 8 Registers........................................................................................................4-4

5-1 Interrupt Vectors.........................................................................................................5-6

5-2 Interrupt Control Register Overview...........................................................................5-7

5-3 Interrupt Source Control and Data Registers.............................................................5-9

6-1 Instruction Group Summary........................................................................................6-2

6-2 Flag Notation Conventions.........................................................................................6-8

6-3 Instruction Set Symbols..............................................................................................6-8

6-4 Instruction Notation Conventions ...............................................................................6-9

6-5 Opcode Quick Reference...........................................................................................6-10

6-6 Condition Codes.........................................................................................................6-12

8-1 S3F84VB Set 1 Register and Values After RESET ...................................................8-2

8-2 S3F84VB Set 1, Bank 0 Register and Values after RESET.......................................8-3

8-3 S3F84VB Set 1, Bank 1 Register and Values after RESET.......................................8-4

8-4 S3F84VB Page 8 Register and Values After RESET ................................................8-5

9-1 S3F84VB Port Configuration Overview......................................................................9-2

9-2 Port Data Register Summary......................................................................................9-3

S3F84VB_UM_REV1.00 MICROCONTROLLER xix

List of Tables (Continued)

Table Title Page
Number Number

18-1 Commonly Used Baud Rates Generated by BRDATA0............................................ 18-6

19-1 Commonly Used Baud Rates Generated by BRDATA1............................................ 19-6

21-1 ISP Sector Size.......................................................................................................... 21-7

21-2 Reset Vector Address................................................................................................ 21-7

22-1 Absolute Maximum Ratings....................................................................................... 22-2

22-2 D.C. Electrical Characteristics................................................................................... 22-2

22-3 A.C. Electrical Characteristics ................................................................................... 22-6

22-4 Input/Output Capacitance.......................................................................................... 22-7

22-5 Data Retention Supply Voltage in Stop Mode ........................................................... 22-7

22-6 A/D Converter Electrical Characteristics ................................................................... 22-9

22-7 Low Voltage Reset Electrical Characteristics............................................................ 22-10

22-8 Synchronous SIO Electrical Characteristics.............................................................. 22-11

22-9 UART Timing Characteristics in Mode 0 (12.0MHz) ................................................. 22-12

22-10 LCD Capacitor Bias Electrical Characteristics........................................................... 22-13

22-11 Main Oscillator Characteristics.................................................................................. 22-14

22-12 Sub Oscillation Characteristics.................................................................................. 22-14

22-13 Main Oscillation Stabilization Time............................................................................ 22-15

22-14 Sub Oscillation Stabilization Time ............................................................................. 22-15

22-15 Internal Flash ROM Electrical Characteristics........................................................... 22-16

24-1 Descriptions of Pins Used to Read/Write the Flash ROM......................................... 24-4

24-2 Reference Table for Connection................................................................................24-6

25-1 Components of TB84VB............................................................................................ 25-4

25-2 Setting of the Jumper in TB84VB .............................................................................. 25-5

xx S3F84VB_UM_REV1.00 MICROCONTROLLER

List of Programming Tips

Description Page
Number

Chapter 2: Address Spaces

Using the Page Pointer for RAM clear (Page 0, Page 1) .........................................................................2-7

Setting the Register Pointers....................................................................................................................2-11

Using the RPs to Calculate the Sum of a Series of Registers..................................................................2-12

Addressing the Common Working Register Area.....................................................................................2-16

Standard Stack Operations Using PUSH and POP..................................................................................2-21

Chapter 5: Interrupt Structure

How to clear an interrupt pending bit........................................................................................................5-16

Chapter 7: Clock Circuit

How to Use Stop Instruction .....................................................................................................................7-6

Switching the CPU clock...........................................................................................................................7-7

Chapter 11: 8-Bit Timer A/B

To generate 38 kHz, 1/3duty signal through P3.0 ....................................................................................11-11

To generate a one pulse signal through P3.0...........................................................................................11-12

Chapter 15: LCD Controller/Driver

LCD display on, after capacitor bias selected ..........................................................................................15-16

Chapter 20: Pattern Generation module

Using the Pattern Generation ...................................................................................................................20-3

Chapter 21: Embedded Flash Memory Interface

Sector Erase .............................................................................................................................................21-9

Programming.............................................................................................................................................21-11

Reading.....................................................................................................................................................21-12

Hard Lock Protection ................................................................................................................................21-13

S3F84VB_UM_REV1.00 MICROCONTROLLER xxi

List of Register Descriptions

Register Full Register Name Page
Identifier Number

ADCON A/D Converter Control Register .................................................................................4-6

BTCON Basic Timer Control Register.....................................................................................4-7

CLKCON System Clock Control Register..................................................................................4-8

FLAGS Set Flags Register......................................................................................................4-9

FMCON Flash Memory Control Register.................................................................................4-10

FMSECH Flash Memory Sector Address Register (High Byte).................................................4-11

FMSECL Flash Memory Sector Address Register (Low Byte)..................................................4-11

FMUSR Flash Memory User Programming Enable Register..................................................4-12

IMR Interrupt Mask Register..............................................................................................4-13

INTPND Interrupt Pending Register.........................................................................................4-14

IPH Instruction Pointer (High Byte) .................................................................................4-15

IPL Instruction Pointer (Low Byte) ..................................................................................4-15

IPR Interrupt Priority Register ...........................................................................................4-16

IRQ Interrupt Request Register.........................................................................................4-17

LCON LCD Control Register.................................................................................................4-18

LMOD LCD Mode Control Register.......................................................................................4-19

OSCCON Oscillator Control Register.........................................................................................4-20

P0CONH Port 0 Control Register (High Byte)............................................................................4-21

P0CONL Port 0 Control Register (Low Byte) ............................................................................4-22

P1CONH Port 1 Control Register (High Byte)............................................................................4-23

P1CONL Port 1 Control Register (Low Byte) ............................................................................4-24

P1PUR Port 1 Pull-up Resistor Enable Register ....................................................................4-25

PNE1 Port 1 N-channel Open-drain Mode Register.............................................................4-26

P2CONH Port 2 Control Register (High Byte)............................................................................4-27

P2CONL Port 2 Control Register (Low Byte) ............................................................................4-28

P2INTH Port 2 Interrupt Control Register (High Byte) .............................................................4-29

P2INTL Port 2 Interrupt Control Register (Low Byte)..............................................................4-30

P2PND Port 2 Interrupt Pending Register...............................................................................4-31

P3CONH Port 3 Control Register (High Byte)............................................................................4-32

P3CONM Port 3 Control Register (Middle Byte)........................................................................4-33

P3CONL Port 3 Control Register (Low Byte) ............................................................................4-34

P3PUR Port 3 Pull-up Resistor Enable Register ....................................................................4-35

PNE3 Port 3 N-channel Open-drain Mode Register.............................................................4-36

P4CONH Port 4 Control Register (High Byte)............................................................................4-37

P4CONL Port 4 Control Register (Low Byte) ............................................................................4-38

P4INTH Port 4 Interrupt Control Register (High Byte) .............................................................4-39

P4INTL Port 4 Interrupt Control Register (Low Byte)..............................................................4-40

S3F84VB_UM_REV1.00 MICROCONTROLLER xxiii

List of Register Descriptions (Continued)

Register Full Register Name Page
Identifier Number

P4PND Port 4 Interrupt Pending Register...............................................................................4-41

P5CONH Port 5 Control Register (High Byte)............................................................................4-42

P5CONL Port 5 Control Register (Low Byte).............................................................................4-43

P6CONH Port 6 Control Register (High Byte)............................................................................4-44

P6CONL Port 6 Control Register (Low Byte).............................................................................4-45

P6PUR Port 6 Pull-up Resistor Enable Register.....................................................................4-46

PNE6 Port 6 N-channel Open-drain Mode Register.............................................................4-47

PGCON Pattern Generation Module Control Register.............................................................4-48

PP Register Page Pointer ................................................................................................4-49

RP0 Register Pointer 0.......................................................................................................4-50

RP1 Register Pointer 1.......................................................................................................4-50

SIOCON SIO Control Register ..................................................................................................4-51

SPH Stack Pointer (High Byte)...........................................................................................4-52

SPL Stack Pointer (Low Byte)............................................................................................4-52

STPCON Stop Control Register.................................................................................................4-53

SYM System Mode Register...............................................................................................4-54

TACON Timer A Control Register............................................................................................4-55

TBCON Timer B Control Register............................................................................................4-56

TCCON Timer C Control Register............................................................................................4-57

TD0CON Timer D0 Control Register..........................................................................................4-58

TD1CON Timer D1 Control Register..........................................................................................4-59

UART0CONH UART 0 Control Register (High Byte).........................................................................4-60

UART0CONL UART 0 Control Register (Low Byte) .........................................................................4-61

UART1CONH UART 1 Control Register (High Byte).........................................................................4-62

UART1CONL UART 1 Control Register (Low Byte) .........................................................................4-63

WTCON Watch Timer Control Register....................................................................................4-64

xxiv S3F84VB_UM_REV1.00 MICROCONTROLLER

List of Instruction Descriptions

Instruction Full Register Name Page
Mnemonic Number

ADC Add with Carry............................................................................................................6-14

ADD Add .............................................................................................................................6-15

AND Logical AND ...............................................................................................................6-16

BAND Bit AND.......................................................................................................................6-17

BCP Bit Compare ...............................................................................................................6-18

BITC Bit Complement..........................................................................................................6-19

BITR Bit Reset.....................................................................................................................6-20

BITS Bit Set .........................................................................................................................6-21

BOR Bit OR.........................................................................................................................6-22

BTJRF Bit Test, Jump Relative on False ...............................................................................6-23

BTJRT Bit Test, Jump Relative on True.................................................................................6-24

BXOR Bit XOR.......................................................................................................................6-25

CALL Call Procedure............................................................................................................6-26

CCF Complement Carry Flag.............................................................................................6-27

CLR Clear...........................................................................................................................6-28

COM Complement...............................................................................................................6-29

CP Compare.....................................................................................................................6-30

CPIJE Compare, Increment, and Jump on Equal .................................................................6-31

CPIJNE Compare, Increment, and Jump on Non-Equal .........................................................6-32

DA Decimal Adjust ...........................................................................................................6-33

DEC Decrement..................................................................................................................6-35

DECW Decrement Word........................................................................................................6-36

DI Disable Interrupts.......................................................................................................6-37

DIV Divide (Unsigned).......................................................................................................6-38

DJNZ Decrement and Jump if Non-Zero..............................................................................6-39

EI Enable Interrupts........................................................................................................6-40

ENTER Enter...........................................................................................................................6-41

EXIT Exit..............................................................................................................................6-42

IDLE Idle Operation.............................................................................................................6-43

INC Increment ...................................................................................................................6-44

INCW Increment Word..........................................................................................................6-45

IRET Interrupt Return..........................................................................................................6-46

JP Jump...........................................................................................................................6-47

JR Jump Relative.............................................................................................................6-48

LD Load............................................................................................................................6-49

LDB Load Bit ......................................................................................................................6-51

S3F84VB_UM_REV1.00 MICROCONTROLLER xxv

List of Instruction Descriptions (Continued)

Instruction Full Register Name Page
Mnemonic Number

LDC/LDE Load Memory..............................................................................................................6-52

LDCD/LDED Load Memory and Decrement....................................................................................6-54

LDCI/LDEI Load Memory and Increment......................................................................................6-55

LDCPD/LDEPD Load Memory with Pre-Decrement.............................................................................6-56

LDCPI/LDEPI Load Memory with Pre-Increment..............................................................................6-57

LDW Load Word..................................................................................................................6-58

MULT Multiply (Unsigned).....................................................................................................6-59

NEXT Next.............................................................................................................................6-60

NOP No Operation ..............................................................................................................6-61

OR Logical OR..................................................................................................................6-62

POP Pop from Stack ...........................................................................................................6-63

POPUD Pop User Stack (Decrementing).................................................................................6-64

POPUI Pop User Stack (Incrementing) ..................................................................................6-65

PUSH Push to Stack..............................................................................................................6-66

PUSHUD Push User Stack (Decrementing)...............................................................................6-67

PUSHUI Push User Stack (Incrementing) ................................................................................6-68

RCF Reset Carry Flag.........................................................................................................6-69

RET Return.........................................................................................................................6-70

RL Rotate Left..................................................................................................................6-71

RLC Rotate Left through Carry...........................................................................................6-72

RR Rotate Right................................................................................................................6-73

RRC Rotate Right through Carry.........................................................................................6-74

SB0 Select Bank 0..............................................................................................................6-75

SB1 Select Bank 1..............................................................................................................6-76

SBC Subtract with Carry.....................................................................................................6-77

SCF Set Carry Flag.............................................................................................................6-78

SRA Shift Right Arithmetic..................................................................................................6-79

SRP/SRP0/SRP1 Set Register Pointer....................................................................................................6-80

STOP Stop Operation............................................................................................................6-81

SUB Subtract ......................................................................................................................6-82

SWAP Swap Nibbles..............................................................................................................6-83

TCM Test Complement under Mask ...................................................................................6-84

TM Test under Mask.........................................................................................................6-85

WFI Wait for Interrupt.........................................................................................................6-86

XOR Logical Exclusive OR..................................................................................................6-87

xxvi S3F84VB_UM_REV1.00 MICROCONTROLLER

S3F84VB_UM_REV1.00 PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

S3C8-SERIES MICROCONTROLLERS

Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range
of integrated peripherals, and various mask-programmable ROM sizes. Among the major CPU features are:

— Efficient register-oriented architecture
— Selectable CPU clock sources
— Idle and Stop power-down mode release by interrupts
— Built-in basic timer with watchdog function

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned to
specific interrupt levels.

S3F84VB MICROCONTROLLER

The S3F84VB single-chip CMOS microcontrollers
are fabricated using the highly advanced CMOS
process, based on Samsung’s newest CPU
architecture.

The S3F84VB is a microcontroller with a 64K-byte
Flash ROM embedded respectively.

Using a proven modular design approach, Samsung
engineers have successfully developed the
S3F84VB by integrating the following peripheral
modules with the powerful SAM8 core:

— Seven programmable I/O ports, including six 8-

bit ports, and one 6-bit port, for a total of 54 pins

— Sixteen bit-programmable pins for external

interrupts

— One 8-bit basic timer for oscillation stabilization

and watchdog functions (system reset)

— Three 8-bit timer/counter and two 16-bit

timer/counter with selectable operating modes
— Watch timer for real time
— LCD Controller/driver
— A/D converter with 8 selectable input pins
— Synchronous SIO modules
— Two asynchronous UART modules
— Pattern generation module

They are currently available in 64-pin QFP and 64­pin SDIP package

1-1

PRODUCT OVERVIEW S3F84VB_UM_REV1.00

FEATURES

CPU

• SAM88 RC CPU core

Memory

• Program Memory (ROM)

- 64K × 8 bits program memory

- Internal flash memory (program memory)
√ Sector size: 128 bytes
√ 10 years data retention
√ Fast programming time
√ User program and sector erase available
√ Endurance: 10,000 erase/program cycles
√ External serial programming support
√ Expandable OBP

TM

(on board program)

sector

• Data Memory (RAM)

- Including LCD display data memory

- 2,098 × 8 bits data memory

Instruction Set

• 78 instructions

• Idle and stop instructions added for power-down
modes

54 I/O Pins

• I/O: 18 pins (Sharing with other signal pins)

• I/O: 36 pins (Sharing with LCD signal outputs)

Interrupts

• 8 interrupt levels and 30 interrupt sources

• Fast interrupt processing feature

8-Bit Basic Timer

• Watchdog timer function

• 4 kinds of clock source

8-Bit Timer/Counter B

• Programmable 8-bit internal timer

• Carrier frequency generator

Two 16-Bit Timer/Counter C

• Programmable 8-bit internal timer

• PWM function

Two 16-Bit Timer/Counter (D0/D1)

• Programmable 16-bit internal timer

• External event counter function

• PWM and capture function

Watch Timer

• Interval time: 1.995mS, 0.125S, 0.25S, and 0.5S
at 32.768 kHz

• 0.5/1/2/4 kHz Selectable buzzer output

LCD Controller/Driver

• 28 segments and 8 common terminals

• 1/2, 1/3, 1/4, and 1/8 duty selectable

• Capacitor or resistor bias selectable

• Regulator and booster circuit for LCD bias

Analog to Digital Converter

• 8-channel analog input

• 10-bit conversion resolution

• 25uS conversion time

Two Channels UART

• Full-duplex serial I/O interface

• Four programmable operating modes

• Auto generating parity bit

8-Bit Timer/Counter A

• Programmable 8-bit internal timer

• External event counter function

• PWM and capture function

8-bit Serial I/O Interface

• 8-bit transmit/receive mode

• 8-bit receive mode

• LSB-first or MSB-first transmission selectable

• Internal or external clock source

1-2

S3F84VB_UM_REV1.00 PRODUCT OVERVIEW

FEATURES (Continued)

Pattern Generation Module

• Pattern generation module triggered by timer
match signal and software

Low Voltage Reset (LVR)

• Criteria voltage: 2.2V

• En/Disable by smart option (ROM address: 3FH)

Two Power-Down Modes

• Idle: only CPU clock stops

• Stop: selected system clock and CPU clock stop

Oscillation Sources

• Crystal, ceramic, or RC for main clock

• Main clock frequency: 0.4 MHz − 12.0 MHz

• 32.768 kHz crystal oscillation circuit for
sub clock

Instruction Execution Times

• 333nS at 12.0 MHz fx (minimum)

• 122.1uS at 32.768 kHz fxt (minimum)

Operating Voltage Range

• 2.0 V to 5.5 V at 0.4 − 4.2 MHz

• 2.7 V to 5.5 V at 0.4 − 12.0 MHz

Operating Temperature Range

• −40°C to +85°C

Package Type

• 64-QFP-1420F, 64-SDIP-750

IVC

• Internal Voltage Converter for 5 V operations

Smart Option

• Low Voltage Reset (LVR) level and
enable/disable are at your hardwired option
(ROM address 3FH)

• ISP related option selectable
(ROM address 3EH)

1-3

PRODUCT OVERVIEW S3F84VB_UM_REV1.00

BLOCK DIAGRAM

P5.7/

P5.6/

XTIN

XIN XOUT

XTOUT

P0.0-P0.1/COM0-COM1
P0.2-P0.7/COM2-COM7

P1.2-P1.7/SEG6-SEG11
P2.0-P2.7/SEG12-SEG19
P3.0-P3.7/SEG20-SEG27
P6.0-P6.5/SEG28-SEG33

P5.0-P5.3/VLC0-VLC3

P3.3/TD0OUT/TD0PWM

P3.5/TD1OUT/TD1PWM

SEG0-SEG5

P5.4/CA
P5.5/CB

P1.7/TACLK

P1.6/TACAP

P1.6/TAOUT/TAPWM

P3.0/TBPWM

P3.1/TCOUT/TCPWM

P3.4/TD0CLK

P3.3/TD0CAP

P3.6/TD1CLK

P3.5/TD1CAP

P6.0/SCK

P6.1/SI

P6.2/SO

SEG20-SEG27/

PG0-PG7

Low Voltage

Reset

LCD Driver/

Controller

Regulator

and

Booster

8-bit Timer/

Counter A

8-bit Timer/

Counter B

8-bit Timer/

Counter C

16-bit Timer/

Counter D0

16-bit Timer/

Counter D1

SIO

Pattern

Generation

Main OSC

I/O Port and Interrupt

Control

Sub OSC

Watch-dog

Timer

Basic Timer

Watch Timer BUZ/P3.7

P0.0-P0.7I/O Port 0

I/O Port 1

P1.0-P1.7

SAM88 RC

Core

64-Kbyte

ROM

nRESETTEST

IVCREF

2,098-byte

RAM

VDD

AVREF

VSS1
VSS2

AVSS

I/O Port 2

I/O Port 3

I/O Port 4

I/O Port 5

I/O Port 6

UART0

UART1

10-bit ADC

INTERRUPT

P2.0-P2.7

P3.0-P3.7

P4.0-P4.7

P5.0-P5.7

P6.0-P6.5

TXD0/P1.3
RXD0/P1.2

TXD1/P1.5
RXD1/P1.4

P4.0-P4.7/
AD0-AD7

P2.0-P2.7/
INT0-INT7

P4.0-P4.7/
INT8-INT15

Figure 1-1. Block Diagram

1-4

S3F84VB_UM_REV1.00 PRODUCT OVERVIEW

PIN ASSIGNMENT

P1.6/TAOUT/TAPWM/TACAP/SEG10

P1.7/TACLK/SEG11

P2.0/INT0/SEG12

P2.1/INT1/SEG13

P2.2/INT2/SEG14

AVREF

AVSS

P1.2/RXD0/SEG6

P1.3/TXD0/SEG7

P1.0

P1.1

P1.4/RXD1/SEG8

P1.5/TXD1/SEG9

P4.7/INT15/AD7
P4.6/INT14/AD6
P4.5/INT13/AD5
P4.4/INT12/AD4
P4.3/INT11/AD3
P4.2/INT10/AD2

P4.1/INT9/AD1
P4.0/INT8/AD0

VDD

VSS1

XOUT

XIN

TEST

P5.7/XT

P5.6/XT

nRESET

P5.5/CB
P5.4/CA

P5.3/VLC3

OUT

Figure 1-2. S3F84VB Pin Assignments (64-QFP-1420F)

6362616059585756555453

64

1
2
3
4
5
6
7
8
9
10
11
12
13

IN

14
15
16
17
18
19

S3F84VB

(64-QFP-1420F)

2021222324

VLC2/P5.2

VLC1/P5.1

VLC0/P5.0

COM7/SEG5/P0.7

2526272829

COM3/SEG1/P0.3

COM4/SEG2/P0.4

COM5/SEG3/P0.5

COM6/SEG4/P0.6

COM2/SEG0/P0.2

30

COM1/P0.1

COM0/P0.0

52

51

SEG15/INT3/P2.3

50

SEG16/INT4/P2.4

49

SEG17/INT5/P2.5

48

SEG18/INT6/P2.6

47

SEG19/INT7/P2.7

46

SEG20/TBPWM/PG0/P3.0

45

SEG21/TCOUT/TCPWM/PG1/P3.1

44

SEG22/PG2/P3.2

43

SEG23/TD0OUT/TD0PWM/TD0CAP/PG3/P3.3

42

IVCREF

41
40
39
38
37
36
35
34
33

31

32

SEG33/P6.5

SEG32/P6.4

SS2

V
SEG24/TD0CLK/PG4/P3.4
SEG25/TD1OUT/TD1PWM/TD1CAP/PG5/P3.5
SEG26/TD1CLK/PG6/P3.6
SEG27/BUZ/PG7/P3.7
SEG28/SCK/P6.0
SEG29/SI/P6.1
SEG30/SO/P6.2
SEG31/P6.3

1-5

PRODUCT OVERVIEW S3F84VB_UM_REV1.00

64

P1.4/RXD1/SEG8

P1.3/TXD0/SEG7

P1.1
P1.0

AVSS

AVREF

P4.7/INT15/AD7

P4.6/INT14/AD6
P4.5/INT13/AD5
P4.4/INT12/AD4
P4.3/INT11/AD3
P4.2/INT10/AD2

P4.1/INT9/AD1
P4.0/INT8/AD0

P0.7/SEG5/COM7
P0.6/SEG4/COM6
P0.5/SEG3/COM5

VSS1

XOUT

TEST

P5.7/XT

P5.6/XT

nRESET

P5.5/CB

P5.4/CA
P5.3/VLC3
P5.2/VLC2
P5.1/VLC1
P5.0/VLC0

VDD

XIN

OUT

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

IN

22
23
24
25
26
27
28
29
30
31
32

S3F84VB

(64-SDIP-750)

SEG9/TXD1/P1.5

63

SEG10/TAOUT/TAPWM/TACAP/P1.6

62

SEG11/TACLK/P1.7P1.2/RXD0/SEG6

61

SEG12/INT0/P2.0

60

SEG13/INT1/P2.1

59

SEG14/INT2/P2.2

58

SEG15/INT3/P2.3

57

SEG16/INT4/P2.4

56

SEG17/INT5/P2.5

55

SEG18/INT6/P2.6
SEG19/INT7/P2.7

54
53

SEG20/TBPWM/PG0/P3.0
SEG21/TCOUT/TCPWM/PG1/P3.1

52
51

SEG22/PG2/P3.2
SEG23/TD0OUT/TD0PWM/TD0CAP/PG3/P3.3

50
49

IVCREF
V

48
47
46
45
44
43
42
41
40
38
38
37
36
35
34
33

SS2

SEG24/TD0CLK/PG4/P3.4
SEG25/TD1OUT/TD1PWM/TD1CAP/PG5/P3.5
SEG26/TD1CLK/PG6/P3.6
SEG27/BUZ/PG7/P3.7
SEG28/SCK/P6.0
SEG29/SI/P6.1
SEG30/SO/P6.2
SEG31/P6.3
SEG32P6.4
SEG33/P6.5
COM0/P0.0
COM1/P0.1
COM2/SEG0/P0.2
COM3/SEG1/P0.3
COM4/SEG2/P0.4

Figure 1-3. S3F84VB Pin Assignments (64-SDIP-750)

1-6

S3F84VB_UM_REV1.00 PRODUCT OVERVIEW

PIN DESCRIPTIONS

Table 1-1. S3F84VB Pin Descriptions

Pin

Names

P0.0
P0.1
P0.2−P0.7

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6

P1.7
P2.0−P2.7

P3.0
P3.1
P3.2

P3.3

P3.4
P3.5

P3.6
P3.7

P4.0−P4.7

Pin

Type

Pin

Description

I/O I/O port with bit-programmable pins;

Input or push-pull output and software
assignable pull-ups.

I/O I/O port with bit-programmable pins;

Input or push-pull, open-drain output and
software assignable pull-ups.

I/O I/O port with bit-programmable pins;

Schmitt trigger input or push-pull output and
software assignable pull-ups.
Alternately used for external interrupt
input(noise filters, interrupt enable and
pending control).

I/O I/O port with bit-programmable pins;

Input or push-pull, open-drain output and
software assignable pull-ups.

I/O The P4.2-P4.7 are the I/O port with bit-

programmable pins, but the P4.0/P4.1 are
the I/O port with two-bits-programmable pins
Schmitt trigger input or push-pull output and
software assignable pull-ups.

Circuit

Type

Pin

Numbers

(note)

H-44 30(37)

29(36)
28−23

(35−30)

H-42 62(5)

61(4)
60(3)
59(2)

58(1)
57(64)
56(63)

55(62)

H-43

54−47

(61−54)

H-42 46(53)

45(52)
44(51)

43(50)

40(47)
39(46)

38(45)
37(44)

F-16

8−1

(15−8)

Share

Pins

COM0
COM1

COM2−COM7/

SEG0−SEG5

−

−

RxD0/SEG6
TxD0/SEG7
RxD1/SEG8
TxD1/SEG9

TAOUT/TAPWM

/TACAP/SEG10

TACLK/SEG11

INT0−INT7/

SEG12−SEG19

TBPWM/PG0/

SEG20

TCOUT/TCPWM/

PG1/SEG21

PG2/SEG22

TD0OUT/

TD0PWM/

TD0CAP/

PG3/SEG23

TD0CLK/PG4/

SEG24

TD1OUT/

TD1PWM/

TD1CAP/

PG5/SEG25

TD1CLK/PG6/

SEG26

BUZ/PG7/

SEG27

AD0−AD7/

INT8−INT15

NOTE: Parentheses indicate pin number for 64-SDIP-750 package.

1-7

PRODUCT OVERVIEW S3F84VB_UM_REV1.00

Table 1-1. S3F84VB Pin Descriptions (Continued)

Pin

Names

P5.0−P5.3
P5.4

P5.5
P5.6

P5.7

P6.0
P6.1
P6.2
P6.3−P6.5

COM0−COM1
COM2−COM7

SEG0–SEG5

SEG6
SEG7
SEG8
SEG9
SEG10

SEG11
SEG12−SEG19

SEG20
SEG21
SEG22

SEG23

SEG24
SEG25

SEG26
SEG27

Pin

Type

I/O I/O port with bit-programmable pins;

Input or push-pull output and software
assignable pull-ups.

Pin

Description

Circuit

Type

F-17

Pin

Numbers

22−19

(29−26)

18(25)
17(24)

I/O I/O port with bit-programmable pins;

Input or push-pull output and software

D-2 15(22)

14(21)

assignable pull-ups.

I/O I/O port with bit-programmable pins;

Input or push-pull, open-drain output
and software assignable pull-ups.

H-42 36(43)

35(42)
34(41)
33−31

(40−38)

I/O LCD common signal output. H-44

30−29

(37−36)

28−23

(35−30)

I/O LCD segment signal output. H-44

28−23

(35−30)

I/O LCD segment signal output. H-42 60(3)

59(2)

58(1)
57(64)
56(63)

55(62)

I/O LCD segment signal output. H-43

54−47

(61−54)

I/O LCD segment signal output. H-42 46(53)

45(52)
44(51)

43(50)

40(47)
39(46)

38(45)
37(44)

Share

Pins

VLC0−VLC3

CA
CB

XT

OUT

XTIN

SCK/SEG28

SI/SEG29

SO/SEG30

SEG31−SEG33

P0.0−P0.1

P0.2−P0.7/

SEG0−SEG5

P0.2−P0.7/

COM2−COM7

P1.2/RxD0

P1.3/TxD0

P1.4/RxD1

P1.5/TxD1

P1.6/TAOUT/

TAPWM/TACAP

P1.7/TACLK

P2.0−P2.7/
INT0−INT7

P3.0/ PG0/

TBPWM

P3.1/PG1/

TCOUT/TCPWM

P3.2/PG2

P3.3/PG3/

TD0OUT/

TD0PWM/

TD0CAP

P3.4/PG4/TD0CLK

P3.5/PG5/

TD1OUT/

TD1PWM/

TD1CAP

P3.6/PG6/TD1CLK

P3.7/PG7/BUZ

NOTE: Parentheses indicate pin number for 64-SDIP-750 package.

1-8

S3F84VB_UM_REV1.00 PRODUCT OVERVIEW

Table 1-1. S3F84VB Pin Descriptions (Continued)

Pin

Names

SEG28
SEG29
SEG30
SEG31−SEG33

VLC0− VLC3

Pin

Type

Pin

Description

Circuit

Type

Pin

Numbers

I/O LCD segment signal output. H-42 36(43)

35(42)
34(41)
33−31

(40−38)

I/O LCD power supply pins. F-17

22−19

Share

Pins

P6.0/SCK

P6.1/SI

P6.2/SO

P6.3−P6.5

P5.0−P5.3

(29−26)

CA
CB

AD0−AD7

AV

REF

AVSS
PG0−PG3

PG4−PG7

TxD0
RxD0

TxD1
RxD1

TAOUT/
TAPWM

I/O Capacitor terminal for voltage booster. F-17 18(25)

17(24)

I/O A/D converter analog input channels. F-16 8–1

(15–8)

A/D converter reference voltage.

−
A/D converter ground.

−

−

−

I/O Pattern generation output. H-42

64(7)
63(6)

46−43

(53−50)

40−37

(47−44)

I/O Uart 0 data output, input. H-42 59(2)

60(3)

I/O Uart 1 data output, input. H-42 57(64)

58(1)

P5.4
P5.5

P4.0−P4.7/

INT8−INT15

−

−

P3.0−P3.3/

SEG20−SEG23

P3.4−P3.7/

SEG24−SEG27

P1.3/SEG7
P1.2/SEG6

P1.5/SEG9
P1.4/SEG8

I/O Timer A clock output and PWM output. H-42 56(63) P1.6/SEG10/

TACAP

TACAP I/O Timer A capture input. H-42 56(63) P1.6/SEG10/

TAOUT/TAPWM
TACLK I/O Timer A external clock input. H-42 55(62) P1.7/SEG11
TBPWM I/O Timer B carrier frequency output. H-42 46(53) P3.0/SEG20/

PG0

TCOUT/
TCPWM

TD0OUT/
TD0PWM

I/O Timer C clock output and PWM output. H-42 45(52) P3.1/SEG21/

PG1

I/O Timer D0 clock output and PWM

output.

H-42 43(50) P3.3/SEG23/

PG3/TD0CAP

TD0CAP I/O Timer D0 capture input. H-42 43(50) P3.3/SEG23/

PG3/TD0OUT/

TD0PWM

TD0CLK I/O Timer D0 external clock input. H-42 40(47) P3.4/SEG24/

PG4

TD1OUT/
TD1PWM

I/O Timer D1 clock output and PWM

output.

H-42 39(46) P3.5/SEG25/

PG5/TD1CAP

NOTE: Parentheses indicate pin number for 64-SDIP-750 package.

1-9

PRODUCT OVERVIEW S3F84VB_UM_REV1.00

Table 1-1. S3F84VB Pin Descriptions (Continued)

Pin

Names

Pin

Type

Pin

Description

Circuit

Type

Pin

Numbers

Share

Pins

TD1CAP I/O Timer D1 capture input. H-42 39(46) P3.5/SEG25/

PG5/TD1OUT/

TD1PWM

TD1CLK I/O Timer D1 external clock input. H-42 38(45) P3.6/SEG26/

PG6

BUZ I/O Output pin for buzzer signal. H-42 37(44) P3.7/SEG27/

PG7
SCK I/O Serial interface clock. H-42 36(43) P6.0/SEG28
SI I/O Serial interface data input. H-42 35(42) P6.1/SEG29
SO I/O Serial interface data output. H-42 34(41) P6.2/SEG30
INT0−INT7

INT8−INT15

nRESET I System reset pin B 16(23)
XIN

XOUT
XTIN

XTOUT
TEST I Test input: it must be connected to

I/O External interrupts input pins. H-43

I/O External interrupts input pins. F-16

Main oscillator pins.

−

Crystal oscillator pins for sub clock.

−

−

−

−

54−47

(61−54)

1−8

(8−15)

12(19)
11(18)

14(21)
15(22)

13(20)

P2.0−P2.7/

SEG12−SEG19

P4.0−P4.7/

AD0−AD7

−

−

P5.7

P5.6

−

VSS
VDD
VSS1

VSS2
IVCREF

Power supply input pins.

−
Ground pins.

−

Internal voltage controller reference

−

−

−

−

9(16)

10(17)
41(48)

42(49)

−

−

−

input pin. A capacitor (0.1uF) must be
connected between IVCREF and V

SS

.

NOTE: Parentheses indicate pin number for 64-SDIP-750 package.

1-10

S3F84VB_UM_REV1.00 PRODUCT OVERVIEW

PIN CIRCUITS

V

DD

V

DD

Data

Output
Disable

P-Channel

In

N-Channel

Figure 1-4. Pin Circuit Type A

VDD

P-Channel

N-Channel

Out

Pull-up
Resistor

In

Schmitt Trigger

Figure 1-5. Pin Circuit Type B

VDD

Pull-up
Resistor

Pull-up
Enable

Data

Output

Disable

Data

Pin Circuit

Type C

I/O

XTI

XTO

Figure 1-6. Pin Circuit Type C

Figure 1-7. Pin Circuit Type D-2 (P5.6–P5.7)

1-11

PRODUCT OVERVIEW S3F84VB_UM_REV1.00

VDD

Pull-up
Enable

Data

Output

Disable

ADCEN

ADC Select

Data

To ADC

Pull-up
Enable

Circuit

Type C

Figure 1-8. Pin Circuit Type F-16 (P4)

I/O

VDD

Data

Output

Disable

VLC/CA/CB

Select

Data

To LCD

Block

Circuit

Type C

I/O

Figure 1-9. Pin Circuit Type F-17 (P5.0 - P5.5)

1-12

S3F84VB_UM_REV1.00 PRODUCT OVERVIEW

VLC0

VLC1/2

COM/SEG

Output

Disable

VLC2/3

Out

Figure 1-10. Pin Circuit Type H-39

VDD

Pull-up
Resistor

Resistor
Enable

COM/SEG

Output

Disable

Data

Circuit

Type H-39

I/O

Figure 1-11. Pin Circuit Type H-43 (P2)

1-13

PRODUCT OVERVIEW S3F84VB_UM_REV1.00

VDD

Pull-up
Resistor

Resistor
Enable

COM/SEG

Output

Disable

Data

Circuit

Type H-39

I/O

Figure 1-12. Pin Circuit Type H-44 (P0)

VDD

Pull-up

VDD

Open-drain

P-CH

Data

Resistor

Resistor
Enable

I/O

Output

Disable1

COM/SEG

Output

Disable2

Data

Circuit

Type H-39

N-CH

Figure 1-13. Pin Circuit Type H-42 (P1, P3, P6)

1-14

S3F84VB_UM_REV1.00 ADDRESS SPACES

2 ADDRESS SPACES

OVERVIEW

The S3F84VB microcontroller has two types of address space:
— Internal program memory (ROM)

— Internal register file

A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and
data between the CPU and the register file.

The S3F84VB has an internal 64-Kbyte Flash ROM.
The 256-byte physical register space is expanded into an addressable area of 320 bytes using addressing

modes.
A 34-byte LCD display register file is implemented.

2-1

ADDRESS SPACES S3F84VB_UM_REV1.00

PROGRAM MEMORY (ROM)

Program memory (ROM) stores program codes or table data. The S3F84VB has 64K bytes internal Flash
program memory.

The first 256 bytes of the ROM (0H−0FFH) are reserved for interrupt vector addresses. Unused locations in this
address range can be used as normal program memory. If you use the vector address area to store a program
code, be careful not to overwrite the vector addresses stored in these locations.

The ROM address at which a program execution starts after a reset is 0100H in the S3F84VB.
The reset address of ROM can be changed by a smart option in the S3F84VB (Full-Flash Device). Refer to the

chapter 21. Embedded Flash Memory Interface for more detail contents.

(Decimal)

65535

255

0

64K-bytes

Internal

Program

Memory Area

Available

ISP Sector

Interrupt Vector Area

Smart option Area

Byte

(HEX)

FFFFH

8FFH

FFH

3FH

3CH

00H

Figure 2-1. Program Memory Address Space

2-2

S3F84VB_UM_REV1.00 ADDRESS SPACES

SMART OPTION

ROM Address: 003EH

.7 .6 .5 .4 .3 .2 .1 .0MSB LSB

ISP reset vector change enable/
disable bit:
0 = OBP reset vector address
1 = Normal vector (address 0100H)

ISP reset vector address selection bits:
00 = 200H(ISP area size: 256 byte)
01 = 300H(ISP area size: 512 byte)
10 = 500H(ISP area size: 1024 byte)
11 = 900H(ISP area size: 2048 byte)

.7 .6 .5 .4 .3 .2 .1 .0MSB LSB

Not used

.7 .6 .5 .4 .3 .2 .1 .0MSB LSB

Not used

ROM Address: 003FH

These bits should be

always logic "110b".

ROM Address: 003CH

Not used

ISP protection size selection bits:(note)
00 = 256 bytes
01 = 512 bytes
10 = 1024 bytes
11 = 2048 bytes

ISP protection enable/disable bit:
0 = Enable (not erasable by LDC)
1 = Disable (Erasable by LDC)

LVR enable/disable bit
(Criteria Voltage: 2.2V)
0 = Disable LVR
1 = Enable LVR

ROM Address: 003DH

.7 .6 .5 .4 .3 .2 .1 .0MSB LSB

Not used

NOTES:

1. After selecting ISP reset vector address in selecting ISP protection size, don't select upper than ISP
area size.

2. When any values are written in the Smart Option area (003CH-003FH) by LDC instruction, the data of
the area may be changed but the Smart Option is not affected. The data for Smart Option should be
written in the Smart Option area (003CH-003FH) by OTP/MTP tools (SPW2 plus single programmer,
or GW-PRO2 gang programmer).

Figure 2-2. Smart Option

Smart option is the ROM option for start condition of the chip. The ROM address used by smart option is from
003CH to 003FH. The S3F84VB only use 003EH to 003FH.

2-3

ADDRESS SPACES S3F84VB_UM_REV1.00

REGISTER ARCHITECTURE

In the S3F84VB implementation, the upper 64-byte area of register files is expanded two 64-byte areas, called set
1 and set 2. The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank 1),

and the lower 32-byte area is a single 32-byte common area.
In case of S3F84VB the total number of addressable 8-bit registers is 2,192. Of these 2,192 registers, 13 bytes

are for CPU and system control registers, 34 bytes are for LCD data registers, 81 bytes are for peripheral control
and data registers, 16 bytes are used as a shared working registers, and 2,048 registers are for general-purpose
use, page 0-page 7.

You can always address set 1 register locations, regardless of which of the ten register pages is currently
selected. Set 1 locations, however, can only be addressed using register addressing modes.

The extension of register space into separately addressable areas (sets, banks, and pages) is supported by
various addressing mode restrictions, the select bank instructions, SB0 and SB1, and the register page pointer
(PP).

Specific register types and the area (in bytes) that they occupy in the register file are summarized in Table 2-1.

Table 2-1. S3F84VB Register Type Summary

Register Type Number of Bytes

General-purpose registers (including the 16-byte
common working register area, eight 192-byte prime
register area, and eight 64-byte set 2 area)
LCD data registers
CPU and system control registers
Mapped clock, peripheral, I/O control, and data registers

Total Addressable Bytes

2,064

34
13
81

2,192

2-4

S3F84VB_UM_REV1.00 ADDRESS SPACES

64

Bytes

32

Bytes

34

Bytes

48

Bytes

FFH

E0H
DFH

D0H
CFH

C0H

51H

30H
2FH

Set1

Bank 1

Bank 0

System and

Peripheral Control

System and

Peripheral Control

(Register Addressing Mode)

System Registers

(Register Addressing Mode)

General Purpose Register

(Register Addressing Mode)

(All addressing modes)

LCD Display Reigster

Peripheral Control Register

(All addressing modes)

Registers

Registers

Page 8

Prime

Data Registers

192

Bytes

FFH

FFH

C0H
BFH

FFH

FFH

FFH

FFH

FFH

FFH

Page 1

Page 1

Page 0

Set 2

Gen era l-Pu rp os e

Data Registers

(Indirect Register,

Indexed Mode, and

Stack Operations)

Page 0

~

~

Prime

Data Registers
(All Addressing

Modes)

Page 4

Page 3

Page 2

Page 7

Page 6

Page 5

~

~

~

256

Bytes

~

~

~

~

~

~

~

00H

00H

Figure 2-3. Internal Register File Organization (S3F84VB)

2-5

ADDRESS SPACES S3F84VB_UM_REV1.00

REGISTER PAGE POINTER (PP)

The S3C8-series architecture supports the logical expansion of the physical 256-byte internal register file (using
an 8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by
the register page pointer (PP, DFH). In the S3F84VB microcontroller, a paged register file expansion is
implemented for LCD data registers, and the register page pointer must be changed to address other pages.

After a reset, the page pointer's source value (lower nibble) and the destination value (upper nibble) are always
"0000", automatically selecting page 0 as the source and destination page for register addressing.

Register Page Pointer (PP)

DFH ,Set 1, R/W

LSBMSB .7 .6 .5 .4 .3 .2 .1 .0

Destination register page selection bits:
0000 Destination: Page 0

0001 Destination: Page 1
0010 Destination: Page 2
0011 Destination: Page 3
0100 Destination: Page 4
0101 Destination: Page 5
0110 Destination: Page 6
0111 Destination: Page 7
1000 Destination: Page 8
Others Not used for the S3F84VB

NOTES:

1. I n the S3F84VB microcontroller, the internal register file is configured as nine pages (Pages 0-7, 8).
The pages 0-7 are used for general purpose register file.

2. The page 8 of S3F84VB is used for LCD data register (30H~51H) and system register (00H~2FH).

Source register page selection bits:
0000 Source: page 0

0001 Source: page 1
0010 Source: page 2
0011 Source: page 3
0100 Source: page 4
0101 Source: page 5
0110 Source: page 6
0111 Source: page 7
1000 Source: page 8
Others Not used for the S3F84VB

Figure 2-4. Register Page Pointer (PP)

2-6

S3F84VB_UM_REV1.00 ADDRESS SPACES

 PROGRAMMING TIP ⎯ Using the Page Pointer for RAM clear (Page 0, Page 1)

LD PP, #00H ; Destination ← 0, Source ← 0
SRP #0C0H
LD R0,#0FFH ; Page 0 RAM clear starts
RAMCL0 CLR @R0
DJNZ R0,RAMCL0
CLR @R0 ; R0 = 00H

LD PP,#10H ; Destination ← 1, Source ← 0
LD R0,#0FFH ; Page 1 RAM clear starts
RAMCL1 CLR @R0
DJNZ R0,RAMCL1
CLR @R0 ; R0 = 00H

NOTE: You should refer to page 6-39 and use DJNZ instruction properly when DJNZ instruction is used in your program.

2-7

ADDRESS SPACES S3F84VB_UM_REV1.00

REGISTER SET 1

The term set 1 refers to the upper 64 bytes of the register file, locations C0H−FFH.
The upper 32-byte area of this 64-byte space (E0H−FFH) is expanded two 32-byte register banks, bank 0 and

bank 1. The set register bank instructions, SB0 or SB1, are used to address one bank or the other. A hardware
reset operation always selects bank 0 addressing.

The upper two 32-byte areas (bank 0 and bank 1) of set 1 (E0H−FFH) contains 56 mapped system and
peripheral control registers. The lower 32-byte area contains 16 system registers (D0H−DFH) and a 16-byte
common working register area (C0H−CFH). You can use the common working register area as a "scratch" area
for data operations being performed in other areas of the register file.

Registers in set 1 location are directly accessible at all times using Register addressing mode. The 16-byte
working register area can only be accessed using working register addressing (For more information about
working register addressing, please refer to Chapter 3, "Addressing Modes.")

REGISTER SET 2

The same 64-byte physical space that is used for set 1 location C0H–FFH is logically duplicated to add another
64 bytes of register space. This expanded area of the register file is called set 2. For the S3F84VB, the set 2
address range (C0H–FFH) is accessible on pages 0-7.

The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions. You can use only
Register addressing mode to access set 1 location. In order to access registers in set 2, you must use Register
Indirect addressing mode or Indexed addressing mode.

The set 2 register area is commonly used for stack operations.

2-8

S3F84VB_UM_REV1.00 ADDRESS SPACES

PRIME REGISTER SPACE

The lower 192 bytes (00H−BFH) of the S3F84VB's eight/four/two 256-byte register pages is called prime register
area. Prime registers can be accessed using any of the seven addressing modes

(see Chapter 3, "Addressing Modes.")
The prime register area on page 0 is immediately addressable following a reset. In order to address prime

registers on pages 0, 1, 2, 3, 4, 5, 6, 7, or 8 you must set the register page pointer (PP) to the appropriate source
and destination values.

Bank 0

FFH

FCH

E0H
D0H
C0H

CPU and system control

General-purpose

Peripheral and I/O
LCD data register

Set 1

Bank 1

FFH

FFH

C0H
BFH

00H

FFH

FFH

FFH

FFH

FFH

FFH

Page 4

Page 3

Page 2

Page 1

Page 0

Set 2

Page 0

Prime

Space

Page 7

Page 6

Page 5

51H

30H
2FH

00H

Page 8

LCD Data

Registr Area

Figure 2-5. Set 1, Set 2, Prime Area Register, and LCD Data Register Map

2-9

ADDRESS SPACES S3F84VB_UM_REV1.00

WORKING REGISTERS

Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields.
When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one
that consists of 32 8-byte register groups or "slices." Each slice comprises of eight 8-bit registers.

Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to
form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block
anywhere in the addressable register file, except the set 2 area.

The terms slice and block are used in this manual to help you visualize the size and relative locations of selected
working register spaces:

— One working register slice is 8 bytes (eight 8-bit working registers, R0–R7 or R8–R15)
— One working register block is 16 bytes (sixteen 8-bit working registers, R0–R15)

All the registers in an 8-byte working register slice have the same binary value for their five most significant
address bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file.
The base addresses for the two selected 8-byte register slices are contained in register pointers RP0 and RP1.

After a reset, RP0 and RP1 always point to the 16-byte common area in set 1 (C0H−CFH).

1 1 1 1 1 X X X

RP1 (Registers R8-R15)

Each register pointer points to
one 8-byte slice of the register
space, selecting a total 16-byte
working register block.

0 0 0 0 0 X X X

RP0 (Registers R0-R7)

Figure 2-6. 8-Byte Working Register Areas (Slices)

Slice 32
Slice 31

~ ~

Slice 2
Slice 1

FFH
F8H
F7H
F0H

Set 1
Only

CFH
C0H

10H
FH
8H
7H
0H

2-10

S3F84VB_UM_REV1.00 ADDRESS SPACES

USING THE REGISTER POINTS

Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable
8-byte working register slices in the register file. After a reset, they point to the working register common area:
RP0 points to addresses C0H−C7H, and RP1 points to addresses C8H−CFH.

To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction.
(see Figures 2-7 and 2-8).

With working register addressing, you can only access those two 8-bit slices of the register file that are currently
pointed to by RP0 and RP1. You cannot, however, use the register pointers to select a working register space in
set 2, C0H−FFH, because these locations can be accessed only using the Indirect Register or Indexed
addressing modes.

The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general
programming guideline, it is recommended that RP0 point to the "lower" slice and RP1 point to the "upper" slice
(see Figure 2-7). In some cases, it may be necessary to define working register areas in different (non­contiguous) areas of the register file. In Figure 2-8, RP0 points to the "upper" slice and RP1 to the "lower" slice.

Because a register pointer can point to either of the two 8-byte slices in the working register block, you can
flexibly define the working register area to support program requirements.

 PROGRAMMING TIP ⎯ Setting the Register Pointers

SRP #70H ; RP0 ← 70H, RP1 ← 78H
SRP1 #48H ; RP0 ← no change, RP1 ← 48H,
SRP0 #0A0H ; RP0 ← A0H, RP1 ← no change
CLR RP0 ; RP0 ← 00H, RP1 ← no change
LD RP1,#0F8H ; RP0 ← no change, RP1 ← 0F8H

Register File

Contains 32

8-Byte Slices

0 0 0 0 1 X X X

RP1

0 0 0 0 0 X X X

RP0

8-Byte Slice

8-Byte Slice

FH (R15)
8H

7H
0H (R0)

16-Byte
Contiguous
Working
Register block

Figure 2-7. Contiguous 16-Byte Working Register Block

2-11

ADDRESS SPACES S3F84VB_UM_REV1.00

F7H (R7)
F0H (R0)

16-Byte
Contiguous
working
Register block

7H (R15)
0H (R0)

1 1 1 1 0 X X X

RP0

0 0 0 0 0 X X X

RP1

8-Byte Slice

Register File

Contains 32

8-Byte Slices

8-Byte Slice

Figure 2-8. Non-Contiguous 16-Byte Working Register Block

 PROGRAMMING TIP ⎯ Using the RPs to Calculate the Sum of a Series of Registers

Calculate the sum of registers 80H−85H using the register pointer. The register addresses from 80H through 85H
contain the values 10H, 11H, 12H, 13H, 14H, and 15H, respectively:

SRP0 #80H ; RP0 ← 80H
ADD R0,R1 ; R0 ← R0 + R1
ADC R0,R2 ; R0 ← R0 + R2 + C
ADC R0,R3 ; R0 ← R0 + R3 + C
ADC R0,R4 ; R0 ← R0 + R4 + C
ADC R0,R5 ; R0 ← R0 + R5 + C

The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this
example takes 12 bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used to
calculate the sum of these registers, the following instruction sequence would have to be used:

ADD 80H,81H ; 80H ← (80H) + (81H)
ADC 80H,82H ; 80H ← (80H) + (82H) + C
ADC 80H,83H ; 80H ← (80H) + (83H) + C
ADC 80H,84H ; 80H ← (80H) + (84H) + C
ADC 80H,85H ; 80H ← (80H) + (85H) + C

Now, the sum of the six registers is also located in register 80H. However, this instruction string takes 15 bytes of
instruction code rather than 12 bytes, and its execution time is 50 cycles rather than 36 cycles.

2-12

S3F84VB_UM_REV1.00 ADDRESS SPACES

REGISTER ADDRESSING

The S3C8-series register architecture provides an efficient method of working register addressing that takes full
advantage of shorter instruction formats to reduce execution time.

With Register (R) addressing mode, in which the operand value is the content of a specific register or register
pair, you can access any location in the register file except for set 2. With working register addressing, you use a
register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that
space.

Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register
pair, the address of the first 8-bit register is always an even number and the address of the next register is always
an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register, and
the least significant byte is always stored in the next (+1) odd-numbered register.

Working register addressing differs from Register addressing as it uses a register pointer to identify a specific
8-byte working register space in the internal register file and a specific 8-bit register within that space.

MSB

Rn

LSB

Rn+1

n = Even address

Figure 2-9. 16-Bit Register Pair

2-13

ADDRESS SPACES S3F84VB_UM_REV1.00

Special-Purpose Registers

Bank 1 Bank 0

FFH

Control
Registers

E0H

D0H

C0H
BFH

RP1

RP0

Each register pointer (RP) can independently point
to one of the 24 8-byte "slices" of the register file
(other than set 2). After a reset, RP0 points to
locations C0H-C7H and RP1 to locations C8H-CFH
(that is, to the common working register area).

NOTE: In the S3F84VB microcontroller, pages 0-7, 8 are

Pages 0-7, 8 contain all of the addressable
registers in the internal register file.

System
Registers

Register
Pointers

General-Purpose Register

FFH

Set 2

CFH

C0H

Prime

Registers

LCD Data
Registers

System

Registers

00H

Register Addressing Only

Can be Pointed by Register Pointer

Page 0

All

Addressing

Modes

Page 0

Indirect Register,

Indexed

Addressing

Modes

All

Addressing

Modes

Can be Pointed to

By register Pointer

Figure 2-10. Register File Addressing

2-14

S3F84VB_UM_REV1.00 ADDRESS SPACES

COMMON WORKING REGISTER AREA (C0H−CFH)

After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations C0H

− CFH, as the active 16-byte working register block:
RP0 → C0H–C7H

RP1 → C8H–CFH

This 16-byte address range is called common area. That is, locations in this area can be used as working
registers by operations that address any location on any page in the register file. Typically, these working
registers serve as temporary buffers for data operations between different pages.

FFH

FCH

E0H

D0H
C0H

Following a hardware reset, register
pointers RP0 and RP1 point to the
common working register area,
locations C0H-CFH.

RP0 =
RP1 =

1 1 0 0 0 0 0 0
1 1 0 0 1 0 0 0

Set 1

FFH

FFH

C0H
BFH

00H

FFH

FFH

FFH

FFH

FFH

FFH

Page 4

Page 3

Page 2

Page 1

Page 0

Set 2

Page 0

Prime

Space

Page 7

Page 6

Page 5

~

~

~

~

~

~

~

~

51H

30H

2FH

00H

Page 8

LCD Data

Register Area

System

Register Area

Figure 2-11. Common Working Register Area

2-15

ADDRESS SPACES S3F84VB_UM_REV1.00

 PROGRAMMING TIP ⎯ Addressing the Common Working Register Area

As the following examples show, you should access working registers in the common area, locations C0H−CFH,
using working register addressing mode only.

Examples 1. LD 0C2H,40H ; Invalid addressing mode!

Use working register addressing instead:
SRP #0C0H

LD R2,40H ; R2 (C2H) → the value in location 40H

2. ADD 0C3H,#45H ; Invalid addressing mode!
Use working register addressing instead:
SRP #0C0H

ADD R3,#45H ; R3 (C3H) → R3 + 45H

4-BIT WORKING REGISTER ADDRESSING

Each register pointer defines a movable 8-byte slice of working register space. The address information stored in
a register pointer serves as an addressing "window" that makes it possible for instructions to access working
registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected
working register area, the address bits are concatenated in the following way to form a complete 8-bit address:

— The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0, "1" selects RP1).
— The five high-order bits in the register pointer select an 8-byte slice of the register space.
— The three low-order bits of the 4-bit address select one of the eight registers in the slice.

As shown in Figure 2-12, the result of this operation is that the five high-order bits from the register pointer are
concatenated with the three low-order bits from the instruction address to form the complete address. As long as
the address stored in the register pointer remains unchanged, the three bits from the address will always point to
an address in the same 8-byte register slice.

Figure 2-13 shows a typical example of 4-bit working register addressing. The high-order bit of the instruction
"INC R6" is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the
three low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B).

2-16

S3F84VB_UM_REV1.00 ADDRESS SPACES

RP0
RP1

Selects
RP0 or RP1

Address OPCODE

Register pointer
provides five
high-order bits

Figure 2-12. 4-Bit Working Register Addressing

RP0

0 1 1 1 0 0 0 0

0 1 1 1 0 1 1 0

Together they create an

8-bit register address

Selects RP0

Register
address
(76H)

4-bit address
provides three
low-order bits

RP1

0 1 1 1 1 0 0 0

R6

0 1 1 0 1 1 1 0

OPCODE

Instruction
'INC R6'

Figure 2-13. 4-Bit Working Register Addressing Example

2-17

ADDRESS SPACES S3F84VB_UM_REV1.00

8-BIT WORKING REGISTER ADDRESSING

You can also use 8-bit working register addressing to access registers in a selected working register area. To
initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value
"1100B." This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working
register addressing.

As shown in Figure 2-14, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit
addressing: Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address; the
three low-order bits of the complete address are provided by the original instruction.

Figure 2-15 shows an example of 8-bit working register addressing. The four high-order bits of the instruction
address (1100B) specify 8-bit working register addressing. Bit 4 ("1") selects RP1 and the five high-order bits in
RP1 (10101B) become the five high-order bits of the register address. The three low-order bits of the register
address (011) are provided by the three low-order bits of the 8-bit instruction address. The five address bits from
RP1 and the three address bits from the instruction are concatenated to form the complete register address,
0ABH (10101011B).

These address
bits indicate 8-bit
working register
addressing

RP0
RP1

Selects
RP0 or RP1

Address

1100

Register pointer
provides five
high-order bits

8-bit physical address

Three low-order bits

Figure 2-14. 8-Bit Working Register Addressing

8-bit logical
address

2-18

S3F84VB_UM_REV1.00 ADDRESS SPACES

RP0

0 1 1 0 0 0 0 0

1 1 0 0 1 0 1 1

Specifies working
register addressing

Figure 2-15. 8-Bit Working Register Addressing Example

Selects RP1

R11

8-bit address
form instruction
'LD R11, R2'

RP1

1 0 1 0 1 0 0 0

1 0 1 0 1 0 1 1

Register
address
(0ABH)

2-19

ADDRESS SPACES S3F84VB_UM_REV1.00

SYSTEM AND USER STACK

The S3C8-series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSH
and POP instructions are used to control system stack operations. The S3F84VB architecture supports stack
operations in the internal register file.

Stack Operations

Return addresses for procedure calls, interrupts, and data are stored on the stack. The contents of the PC are
saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents
of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to
their original locations. The stack address value is always decreased by one before a push operation and
increased by one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top
of the stack, as shown in Figure 2-16.

High Address

PCL

PCL

Top of

stack

PCH

Top of

stack

PCH

Flags

Stack contents

after a call
instruction

Low Address

Stack contents

after an

interrupt

Figure 2-16. Stack Operations

User-Defined Stacks

You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI,
PUSHUD, POPUI, and POPUD support user-defined stack operations.

Stack Pointers (SPL, SPH)

Register locations D8H and D9H contain the 16-bit stack pointer (SP) that is used for system stack operations.
The most significant byte of the SP address, SP15–SP8, is stored in the SPH register (D8H), and the least
significant byte, SP7–SP0, is stored in the SPL register (D9H). After a reset, the SP value is undetermined.

Because only internal memory space is implemented in the S3F84VB, the SPL must be initialized to an 8-bit
value in the range 00H–FFH. The SPH register is not needed and can be used as a general-purpose register, if
necessary.

When the SPL register contains the only stack pointer value (that is, when it points to a system stack in the
register file), you can use the SPH register as a general-purpose data register. However, if an overflow or
underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register
during normal stack operations, the value in the SPL register will overflow (or underflow) to the SPH register,
overwriting any other data that is currently stored there. To avoid overwriting data in the SPH register, you can
initialize the SPL value to "FFH" instead of "00H".

2-20

S3F84VB_UM_REV1.00 ADDRESS SPACES

 PROGRAMMING TIP ⎯ Standard Stack Operations Using PUSH and POP

The following example shows you how to perform stack operations in the internal register file using PUSH and
POP instructions:

LD SPL,#0FFH ; SPL ← FFH
; (Normally, the SPL is set to 0FFH by the initialization
; routine)

•

•

PUSH PP ; Stack address 0FEH ← PP
PUSH RP0 ; Stack address 0FDH ← RP0
PUSH RP1 ; Stack address 0FCH ← RP1
PUSH R3 ; Stack address 0FBH ← R3

•

•

POP R3 ; R3 ← Stack address 0FBH
POP RP1 ; RP1 ← Stack address 0FCH
POP RP0 ; RP0 ← Stack address 0FDH
POP PP ; PP ← Stack address 0FEH

•

•

2-21

S3F84VB_UM_REV1.00 ADDRESSING MODES

3 ADDRESSING MODES

OVERVIEW

Instructions that are stored in program memory are fetched for execution using the program counter. Instructions
indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to
determine the location of the data operand. The operands specified in SAM88RC instructions may be condition
codes, immediate data, or a location in the register file, program memory, or data memory.

The S3C8-series instruction set supports seven explicit addressing modes. Not all of these addressing modes are
available for each instruction. The seven addressing modes and their symbols are:

— Register (R)
— Indirect Register (IR)
— Indexed (X)
— Direct Address (DA)
— Indirect Address (IA)
— Relative Address (RA)
— Immediate (IM)

3-1

ADDRESSING MODES S3F84VB_UM_REV1.00

REGISTER ADDRESSING MODE (R)

In Register addressing mode (R), the operand value is the content of a specified register or register pair
(see Figure 3-1).

Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8-byte
working register space in the register file and an 8-bit register within that space (see Figure 3-2).

Program Memory Register File

8-bit Register

File Address

One-Operand

Instruction

(Example)

Sample Instruction:

dst

OPCODE

Point to One

OPERAND

Register in Register

File

Value used in

Instruction Execution

DEC CNTR ; Where CNTR is the label of an 8-bit register address

4-bit

Working Register

Two-Operand

Instruction

(Example)

Sample Instruction:

Figure 3-1. Register Addressing

Program Memory

dst

OPCODE

src

MSB Point to

RP0 ot RP1

3 LSBs

Point to the

Working Register

(1 of 8)

Register File

RP0 or RP1

Selected
RP points
to start
of working
register
block

OPERAND

ADD R1, R2 ; Where R1 and R2 are registers in the currently

selected working register area.

Figure 3-2. Working Register Addressing

3-2

S3F84VB_UM_REV1.00 ADDRESSING MODES

INDIRECT REGISTER ADDRESSING MODE (IR)

In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the
operand. Depending on the instruction used, the actual address may point to a register in the register file, to
program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).

You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to
indirectly address another memory location. Please note, however, that you cannot access locations C0H−FFH in
set 1 using the Indirect Register addressing mode.

Program Memory Register File

8-bit Register

File Address

One-Operand

Instruction
(Example)

dst

OPCODE

Point to One

ADDRESS

Register in Register

File

Address of Operand

used by Instruction

Value used in

Instruction Execution

Sample Instruction:
RL @SHIFT ; Where SHIFT is the label of an 8-bit register address

OPERAND

Figure 3-3. Indirect Register Addressing to Register File

3-3

ADDRESSING MODES S3F84VB_UM_REV1.00

INDIRECT REGISTER ADDRESSING MODE (Continued)

Register File

Program Memory

Example

Instruction

References

Program

Memory

Sample Instructions:
CALL @RR2

JP @RR2

REGISTER

dst

OPCODE

Points to

Register Pair

Value used in

Instruction

PAIR

Program Memory

OPERAND

Figure 3-4. Indirect Register Addressing to Program Memory

16-Bit
Address
Points to
Program
Memory

3-4

S3F84VB_UM_REV1.00 ADDRESSING MODES

INDIRECT REGISTER ADDRESSING MODE (Continued)

Register File

MSB Points to

4-bit
Working
Register
Address

Program Memory

dst

OPCODE

src

RP0 or RP1

3 LSBs

Point to the

Working Register

(1 of 8)

RP0 or RP1

Selected
RP points

~~

ADDRESS

to start fo
working register
block

~~

Sample Instruction:
OR R3, @R6

Value used in

Instruction

OPERAND

Figure 3-5. Indirect Working Register Addressing to Register File

3-5

ADDRESSING MODES S3F84VB_UM_REV1.00

INDIRECT REGISTER ADDRESSING MODE (Concluded)

Register File

MSB Points to

4-bit Working

Register Address

Example Instruction

References either

Program Memory or

Data Memory

Program Memory

dst

OPCODE

src

RP0 or RP1

Next 2-bit Point

to Working

Register Pair

(1 of 4)

LSB Selects

Value used in

Instruction

RP0 or RP1

Register

Pair

Program Memory

or

Data Memory

OPERAND

Selected
RP points
to start of
working
register
block

16-Bit
address
points to
program
memory
or data
memory

Sample Instructions:
LCD R5,@RR6 ; Program memory access

LDE R3,@RR14 ; External data memory access
LDE @RR4, R8 ; External data memory access

Figure 3-6. Indirect Working Register Addressing to Program or Data Memory

3-6

S3F84VB_UM_REV1.00 ADDRESSING MODES

INDEXED ADDRESSING MODE (X)

Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to
calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access
locations in the internal register file or in external memory. Please note, however, that you cannot access
locations C0H−FFH in set 1 using Indexed addressing mode.

In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range −128
to +127. This applies to external memory accesses only (see Figure 3-8.)

For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained
in a working register. For external memory accesses, the base address is stored in the working register pair
designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to that base address
(see Figure 3-9).

The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction
(LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory and for
external data memory, when implemented.

Two-Operand

Instruction

Example

Sample Instruction:
LD R0, #BASE[R1] ; Where BASE is an 8-bit immediate value

Program Memory

Base Address

dst/src

OPCODE

x

Value used in

Instruction

+

3 LSBs

Point to One of the

Woking Register

(1 of 8)

Register File

RP0 or RP1

~~

Selected RP
points to

OPERAND

start of
working
register
block

~~

INDEX

Figure 3-7. Indexed Addressing to Register File

3-7

ADDRESSING MODES S3F84VB_UM_REV1.00

INDEXED ADDRESSING MODE (Continued)

Register File

MSB Points to

4-bit Working

Register Address

Program Memory

OFFSET

dst/src

OPCODE

x

RP0 or RP1

NEXT 2 Bits

Point to Working

Register Pair

(1 of 4)

LSB Selects

RP0 or RP1

Selected
RP points

~~

Register

Pair

Program Memory

or

Data Memory

to start of
working
register
block

16-Bit
address
added to
offset

+

8-Bits

16-Bits

16-Bits

OPERAND

Sample Instructions:
LDC R4, #04H[RR2] ; The values in the program address (RR2 + 04H)

are loaded into register R4.

LDE R4,#04H[RR2] ; Identical operation to LDC example, except that

external program memory is accessed.

Value used in
Instruction

Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset

3-8

S3F84VB_UM_REV1.00 ADDRESSING MODES

INDEXED ADDRESSING MODE (Concluded)

Register File

MSB Points to

4-bit Working

Register Address

Program Memory

OFFSET
OFFSET

dst/src

OPCODE

src

RP0 or RP1

NEXT 2 Bits

Point to Working

Register Pair

LSB Selects

RP0 or RP1

Selected
RP points

~~

Register

Pair

Program Memory

or

Data Memory

to start of
working
register
block

16-Bit
address
added to
offset

+

8-Bits

16-Bits

16-Bits

Sample Instructions:
LDC R4, #1000H[RR2] ; The values in the program address (RR2 + 1000H)

are loaded into register R4.

LDE R4,#1000H[RR2] ; Identical operation to LDC example, except that

external program memory is accessed.

OPERAND

Value used in
Instruction

Figure 3-9. Indexed Addressing to Program or Data Memory

3-9

ADDRESSING MODES S3F84VB_UM_REV1.00

DIRECT ADDRESS MODE (DA)

In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call
(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC
whenever a JP or CALL instruction is executed.

The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for
Load operations to program memory (LDC) or to external data memory (LDE), if implemented.

Program or

Data Memory

Memory

Program Memory

Address
Used

Upper Address Byte

Lower Address Byte

dst/src

Sample Instructions:
LDC R5,1234H ; The values in the program address (1234H)
LDE R5,1234H ; Identical operation to LDC example, except that

"0" or "1"

OPCODE

are loaded into register R5.
external program memory is accessed.

LSB Selects Program
Memory or Data Memory:
"0" = Program Memory
"1" = Data Memory

Figure 3-10. Direct Addressing for Load Instructions

3-10

S3F84VB_UM_REV1.00 ADDRESSING MODES

DIRECT ADDRESS MODE (Continued)

Program Memory

Next OPCODE

Memory
Address
Used

Upper Address Byte
Lower Address Byte

OPCODE

Sample Instructions:
JP C,JOB1 ; Where JOB1 is a 16-bit immediate address

CALL DISPLAY ; Where DISPLAY is a 16-bit immediate address

Figure 3-11. Direct Addressing for Call and Jump Instructions

3-11

ADDRESSING MODES S3F84VB_UM_REV1.00

INDIRECT ADDRESS MODE (IA)

In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program
memory. The selected pair of memory locations contains the actual address of the next instruction to be executed.
Only the CALL instruction can use the Indirect Address mode.

Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program
memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are
assumed to be all zeros.

Program Memory

Next Instruction

LSB Must be Zero

Current

Instruction

Lower Address Byte
Upper Address Byte

Sample Instruction:
CALL #40H ; The 16-bit value in program memory addresses 40H

and 41H is the subroutine start address.

dst

OPCODE

Program Memory
Locations 0-255

Figure 3-12. Indirect Addressing

3-12

S3F84VB_UM_REV1.00 ADDRESSING MODES

RELATIVE ADDRESS MODE (RA)

In Relative Address (RA) mode, a twos-complement signed displacement between − 128 and + 127 is specified in
the instruction. The displacement value is then added to the current PC value. The result is the address of the
next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction
immediately following the current instruction.

Several program control instructions use the Relative Address mode to perform conditional jumps. The
instructions that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR.

Program Memory

Next OPCODE

Program Memory
Address Used

Current

Displacement

Current Instruction

Sample Instructions:
JR ULT,$+OFFSET ; Where OFFSET is a value in the range +127 to -128

OPCODE

PC Value

Signed
Displacement Value

+

Figure 3-13. Relative Addressing

3-13

ADDRESSING MODES S3F84VB_UM_REV1.00

IMMEDIATE MODE (IM)

In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand
field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate
addressing mode is useful for loading constant values into registers.

Program Memory

OPERAND

OPCODE

(The Operand value is in the instruction)

Sample Instruction:
LD R0,#0AAH

Figure 3-14. Immediate Addressing

3-14

S3F84VB_UM_REV1.00 CONTROL REGISTER

4 CONTROL REGISTERS

OVERVIEW

In this chapter, detailed descriptions of the S3F84VB control registers are presented in an easy-to-read format.
You can use this chapter as a quick-reference source when writing application programs. Figure 4-1 illustrates
the important features of the standard register description format.

Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed
information about control registers is presented in the context of the specific peripheral hardware descriptions in
Part II of this manual.

Data and counter registers are not described in detail in this reference chapter. More information about all of the
registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this
manual.

The locations and read/write characteristics of all mapped registers in the S3F84VB register file are listed in Table
4-1. The hardware reset value for each mapped register is described in Chapter 8, "RESET and Power-Down."

Table 4-1. Set 1 Registers

Register Name Mnemonic Decimal Hex R/W

Basic Timer Control Register BTCON 211 D3H R/W
System Clock Control Register CLKCON 212 D4H R/W
System Flags Register FLAGS 213 D5H R/W
Register Pointer 0 RP0 214 D6H R/W
Register Pointer 1 RP1 215 D7H R/W
Stack Pointer (High Byte) SPH 216 D8H R/W
Stack Pointer (Low Byte) SPL 217 D9H R/W
Instruction Pointer (High Byte) IPH 218 DAH R/W
Instruction Pointer (Low Byte) IPL 219 DBH R/W
Interrupt Request Register IRQ 220 DCH R
Interrupt Mask Register IMR 221 DDH R/W
System Mode Register SYM 222 DEH R/W
Register Page Pointer PP 223 DFH R/W

4-1

CONTROL REGISTERS S3F84VB_UM_REV1.00

Table 4-2. Set 1, Bank 0 Registers

Register Name Mnemonic Decimal Hex R/W

A/D Converter Data Register (High Byte) ADDATAH 208 D0H R
A/D Converter Data Register (Low Byte) ADDATAL 209 D1H R
A/D Converter Control Register ADCON 210 D2H R/W
Timer A Counter Register TACNT 224 E0H R
Timer A Data Register TADATA 225 E1H R/W
Timer A Control Register TACON 226 E2H R/W
Timer B Control Register TBCON 227 E3H R/W
Timer B Data Register (High Byte) TBDATAH 228 E4H R/W
Timer B Data Register (Low Byte) TBDATAL 229 E5H R/W
Watch Timer Control Register WTCON 230 E6H R/W
SIO Control Register SIOCON 231 E7H R/W
SIO Data Register SIODATA 232 E8H R/W
SIO Pre-Scaler Register SIOPS 233 E9H R/W
Timer C Counter Register TCCNT 234 EAH R
Timer C Data Register TCDATA 235 EBH R/W
Timer C Control Register TCCON 236 ECH R/W

Locations EDH−EFH are not mapped.
LCD Control Register LCON 240 F0H R/W
LCD Mode Register LMOD 241 F1H R/W

Locations F2H−F3H are not mapped.
Interrupt Pending Register INTPND 244 F4H R/W
STOP Control Register STPCON 245 F5H R/W
Flash Memory Sector Address Register (High Byte) FMSECH 246 F6H R/W
Flash Memory Sector Address Register (Low Byte) FMSECL 247 F7H R/W
Flash Memory User Programming Enable Register FMUSR 248 F8H R/W
Flash Memory Control Register FMCON 249 F9H R/W
Oscillator Control Register OSCCON 250 FAH R/W

Locations FBH−FCH are not mapped.

Basic Timer Counter BTCNT 253 FDH R

Location FEH is not mapped.

Interrupt Priority Register IPR 255 FFH R/W

4-2

S3F84VB_UM_REV1.00 CONTROL REGISTER

Table 4-3. Set 1, Bank 1 Registers

Register Name Mnemonic Decimal Hex R/W

Pattern Generation Control Register PGCON 208 D0H R/W
Pattern Generation Data Register PGDATA 209 D1H R/W

Location D2H is not mapped.
Port 0 Control Register (High Byte) P0CONH 224 E0H R/W
Port 0 Control Register (Low Byte) P0CONL 225 E1H R/W
Port 1 Control Register (High Byte) P1CONH 226 E2H R/W
Port 1 Control Register (Low Byte) P1CONL 227 E3H R/W
Port 1 Pull-up Resistor Enable Register P1PUR 228 E4H R/W
Port 1 N-Channel Open-drain Mode Register PNE1 229 E5H R/W
Port 2 Control Register (High Byte) P2CONH 230 E6H R/W
Port 2 Control Register (Low Byte) P2CONL 231 E7H R/W
Port 2 Interrupt Control Register (High Byte) P2INTH 232 E8H R/W
Port 2 Interrupt Control Register (Low Byte) P2INTL 233 E9H R/W
Port 2 Interrupt Pending Register P2PND 234 EAH R/W
Port 3 Interrupt Control Register (High Byte) P3CONH 235 EBH R/W
Port 3 Interrupt Control Register (Middle Byte) P3CONM 236 ECH R/W
Port 3 Interrupt Control Register (Low Byte) P3CONL 237 EDH R/W
Port 3 Pull-up Resistor Enable Register P3PUR 238 EEH R/W
Port 3 N-Channel Open-drain Mode Register PNE3 239 EFH R/W
Port 5 Control Register (High Byte) P5CONH 240 F0H R/W
Port 5 Control Register (Low Byte) P5CONL 241 F1H R/W
Port 6 Control Register (High Byte) P6CONH 242 F2H R/W
Port 6 Control Register (Low Byte) P6CONL 243 F3H R/W
Port 6 Pull-up Resistor Enable Register P6PUR 244 F4H R/W
Port 6 N-Channel Open-drain Mode Register PNE6 245 F5H R/W
Timer D0 Counter Register (High Byte) TD0CNTH 246 F6H R
Timer D0 Counter Register (Low Byte) TD0CNTL 247 F7H R
Timer D0 Data Register (High Byte) TD0DATAH 248 F8H R/W
Timer D0 Data Register (Low Byte) TD0DATAL 249 F9H R/W
Timer D0 Control Register TD0CON 250 FAH R/W
Timer D1 Control Register TD1CON 251 FBH R/W
Timer D1 Counter Register (High Byte) TD1CNTH 252 FCH R
Timer D1 Counter Register (Low Byte) TD1CNTL 253 FDH R
Timer D1 Data Register (High Byte) TD1DATAH 254 FEH R/W
Timer D1 Data Register (Low Byte) TD1DATAL 255 FFH R/W

4-3

CONTROL REGISTERS S3F84VB_UM_REV1.00

Table 4-4. Page 8 Registers

Register Name Mnemonic Decimal Hex R/W

Port 0 Data Register
Port 1 Data Register
Port 2 Data Register
Port 3 Data Register
Port 4 Data Register
Port 5 Data Register
Port 6 Data Register

P0 0 00H R/W
P1 1 01H R/W
P2 2 02H R/W
P3 3 03H R/W
P4 4 04H R/W
P5 5 05H R/W
P6 6 06H R/W

Locations 07H−0BH are not mapped.
Port 4 Control Register (High Byte)
Port 4 Control Register (Low Byte)
Port 4 Interrupt Control Register (High Byte)
Port 4 Interrupt Control Register (Low Byte)
Port 4 Interrupt Pending Register

P4CONH

P4CONL

P4INTH

P4INTL
P4PND

12 0CH R/W
13 0DH R/W
14 0EH R/W
15 0FH R/W
16 10H R/W

Locations 11H−13H are not mapped.
UART 0 Control Register (High Byte)

UART 0 Control Register (Low Byte)
UART 0 Data Register
UART 0 Baud Rate Data Register
UART 1 Control Register (High Byte)
UART 1 Control Register (Low Byte)
UART 1 Data Register
UART 1 Baud Rate Data Register

UART0CONH

UART0CONL

UDATA0

BRDATA0

UART1CONH

UART1CONL

UDATA1

BRDATA1

20 14H R/W
21 15H R/W
22 16H R/W
23 17H R/W
24 18H R/W
25 19H R/W
26 1AH R/W
27 1BH R/W

Locations 1CH−2FH are not mapped.

4-4

S3F84VB_UM_REV1.00 CONTROL REGISTER

r

0

Bit number(s) that is/are appended to
the register name for bit addressing

Full Register nameRegister ID

FLAGS - System Flags Register

Bit Identifier
RESET Value
Read/Write
Bit Addressing
Mode

.7 Carry Flag (C)

.6 Zero Flag (Z)

.5

R/W R/W R/W

Register addressing mode only

0
1

0
1

Sign Flag (S)

0
1

Name of individual
bit or related bits

Register address
(hexadecimal)

D5H

.7 .6 .5

xxx

Operation does not generate a carry or borrow condition

Operation generates carry-out or borrow into high-order bit 7

Operation result is a non-zero value
Operation result is zero

Operation generates positive number (MSB = "0")
Operation generates negative number (MSB = "1")

.4 .3 .2 .1 .0

x

R/W

x

R/W

x

R/W

Register location
in the internal
register file

Set 1

x

R/W

0

R/W

R = Read-only
W = Write-only
R/W = Read/write
'-' = Not used

Type of addressing
that must be used to
address the bit
(1-bit, 4-bit, or 8-bit)

Description of the
effect of specific
bit settings

Bit numbe
MSB = Bit
LSB = Bit

RESET value notation:
'-' = Not used
'x' = Undetermined value
'0' = Logic zero
'1' = Logic one

Figure 4-1. Register Description Format

4-5

CONTROL REGISTERS S3F84VB_UM_REV1.00

ADCON — A/D Converter Control Register D2H Set 1, Bank 0

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value
Read/Write
Addressing Mode

.7

.6–.4 A/D Input Pin Selection Bits

.3 End-of-Conversion Bit (Read-only)

.2–.1 Clock Source Selection Bits

.0 Start or Enable Bit

– 0 0 0 0 0 0 0
– R/W R/W R/W R R/W R/W R/W

Register addressing mode only

Not used for the S3F84VB

0 0 0 AD0
0 0 1 AD1
0 1 0 AD2
0 1 1 AD3
1 0 0 AD4
1 0 1 AD5
1 1 0 AD6
1 1 1 AD7

0 Conversion not complete
1 Conversion complete

0 0 fxx/16
0 1 fxx/8
1 0 fxx/4
1 1 fxx/1

0 Disable operation
1 Start operation

4-6

S3F84VB_UM_REV1.00 CONTROL REGISTER

BTCON — Basic Timer Control Register D3H Set 1

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value
Read/Write
Addressing Mode

.7–.4 Watchdog Timer Function Disable Code (for System Reset)

.3–.2

.1

.0

1 Clear both clock frequency dividers

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

1 0 1 0 Disable watchdog timer function

Others Enable watchdog timer function

Basic Timer Input Clock Selection Bits

(3)

0 0 fxx/4096
0 1 fxx/1024
1 0 fxx/128
1 1 fxx/16

Basic Timer Counter Clear Bit

(1)

0 No effect
1 Clear the basic timer counter value

Clock Frequency Divider Clear Bit for Basic Timer and Timer/Counters

(2)

0 No effect

NOTES:

1. When you write a “1” to BTCON.1, the basic timer counter value is cleared to "00H". Immediately following the write
operation, the BTCON.1 value is automatically cleared to “0”.

2. When you write a "1" to BTCON.0, the corresponding frequency divider is cleared to "00H". Immediately following the
write operation, the BTCON.0 value is automatically cleared to "0".

3. The fxx

is selected clock for system (main OSC. or sub OSC.).

4-7

CONTROL REGISTERS S3F84VB_UM_REV1.00

CLKCON — System Clock Control Register D4H Set 1

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value
Read/Write
Addressing Mode

.7 Oscillator IRQ Wake-up Function Bit

.6–.5

.4–.3

.2–.0

0 – – 0 0 – – –

R/W – – R/W R/W – – –

Register addressing mode only

0 Enable IRQ for main wake-up in power down mode
1 Disable IRQ for main wake-up in power down mode

Not used for the S3F84VB

(note)

CPU Clock (System Clock) Selection Bits

0 0 fxx/16
0 1 fxx/8
1 0 fxx/2
1 1 fxx/1

Not used for the S3F84VB

NOTE: After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load
the appropriate values to CLKCON.3 and CLKCON.4.

4-8

S3F84VB_UM_REV1.00 CONTROL REGISTER

FLAGS — System Flags Register D5H Set 1

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value
Read/Write
Addressing Mode

.7 Carry Flag (C)

0 Operation does not generate a carry or borrow condition
1 Operation generates a carry-out or borrow into high-order bit 7

.6 Zero Flag (Z)

0 Operation result is a non-zero value
1 Operation result is zero

.5 Sign Flag (S)

0 Operation generates a positive number (MSB = "0")
1 Operation generates a negative number (MSB = "1")

.4 Overflow Flag (V)

0
1 Operation result is > +127 or < –128

.3 Decimal Adjust Flag (D)

0 Add operation completed
1 Subtraction operation completed

.2 Half-Carry Flag (H)

0 No carry-out of bit 3 or no borrow into bit 3 by addition or subtraction
1 Addition generated carry-out of bit 3 or subtraction generated borrow into bit 3

.1 Fast Interrupt Status Flag (FIS)

0 Interrupt return (IRET) in progress (when read)
1 Fast interrupt service routine in progress (when read)

.0 Bank Address Selection Flag (BA)

0 Bank 0 is selected
1 Bank 1 is selected

x x x x x x 0 0

R/W R/W R/W R/W R/W R/W R R/W

Register addressing mode only

Operation result is ≤ +127 or ≥ –128

4-9

CONTROL REGISTERS S3F84VB_UM_REV1.00

FMCON — Flash Memory Control Register F9H Set 1, Bank 0

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value
Read/Write
Addressing Mode

.7–.4 Flash Memory Mode Selection Bits

0 1 0 1 Programming mode
1 0 1 0 Sector erase mode
0 1 1 0 Hard lock mode
Others Not available

.3 Sector Erase Status Bit (Read-only)

0 Success sector erase
1 Fail sector erase

.2–.1

.0 Flash Operation Start Bit

0 Operation stop bit
1 Operation start bit

0 0 0 0 0 – – 0

R/W R/W R/W R/W R – – R/W

Register addressing mode only

Not used for the S3F84VB

NOTE: The FMCON.0 will be cleared automatically just after the corresponding operation completed.

4-10

S3F84VB_UM_REV1.00 CONTROL REGISTER

FMSECH — Flash Memory Sector Address Register (High Byte) F6H Set 1, Bank 0

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value
Read/Write
Addressing Mode

.7–.0 Flash Memory Sector Address Bits (High Byte)

NOTE: The high-byte flash memory sector address pointer value is higher eight bits of the 16-bit pointer address.

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

th-8th

The 15

to select a sector of Flash ROM

FMSECL — Flash Memory Sector Address Register (Low Byte) F7H Set 1, Bank 0

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value
Read/Write
Addressing Mode

.7 Flash Memory Sector Address Bit (Low Byte)

.6–.0

NOTE: The low-byte flash memory sector address pointer value is lower eight bits of the 16-bit pointer address.

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R R/W

Register addressing mode only

th

The 7

Not used for the S3F84VB

bit to select a sector of Flash ROM

4-11

CONTROL REGISTERS S3F84VB_UM_REV1.00

FMUSR — Flash Memory User Programming Enable Register F8H Set 1, Bank 0

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value
Read/Write
Addressing Mode

.7–.0 Flash Memory User Programming Enable Bits

1 0 1 00101Enable user programming mode
Others Disable user programming mode

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

4-12

S3F84VB_UM_REV1.00 CONTROL REGISTER

IMR — Interrupt Mask Register DDH Set 1

Bit Identifier .7 .6
RESET Value
Read/Write
Addressing Mode

x x

R/W R/W

Register addressing mode only

.5 .4 .3 .2 .1 .0

x x x x x x

R/W R/W R/W R/W R/W R/W

.7 Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P4.0–4.7

0 Disable (mask)
1 Enable (unmask)

.6 Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P2.0–2.7

0 Disable (mask)
1 Enable (unmask)

.5 Interrupt Level 5 (IRQ5) Enable Bit; UART0/1 Transmit, UART0/1 Receive

0 Disable (mask)
1 Enable (unmask)

.4 Interrupt Level 4 (IRQ4) Enable Bit; Watch Timer, SIO

0 Disable (mask)
1 Enable (unmask)

.3 Interrupt Level 3 (IRQ3) Enable Bit; Timer D0/D1 Match/Capture or Overflow

0 Disable (mask)
1 Enable (unmask)

.2 Interrupt Level 2 (IRQ2) Enable Bit; Timer C Match/Overflow

0 Disable (mask)
1 Enable (unmask)

.1 Interrupt Level 1 (IRQ1) Enable Bit; Timer B Match

0 Disable (mask)
1 Enable (unmask)

.0 Interrupt Level 0 (IRQ0) Enable Bit; Timer A Match/Capture or Overflow

NOTE: When an interrupt level is masked, any interrupt requests that may be issued are not recognized by the CPU.

0 Disable (mask)
1 Enable (unmask)

4-13

CONTROL REGISTERS S3F84VB_UM_REV1.00

INTPND — Interrupt Pending Register F4H Set 1, Bank 0

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value
Read/Write
Addressing Mode

.7–.6

.5 Timer D1 Match/Capture Interrupt Pending Bit

.4 Timer D1 Overflow Interrupt Pending Bit

.3 Timer D0 Match/Capture Interrupt Pending Bit

.2 Timer D0 Overflow Interrupt Pending Bit

.1 Timer A Match/Capture Interrupt Pending Bit

.0 Timer A Overflow Interrupt Pending Bit

– – 0 0 0 0 0 0
– – R/W R/W R/W R/W R/W R/W

Register addressing mode only

Not used for the S3F84VB

No interrupt pending (when read), clear pending bit (when write)

0

Interrupt is pending (when read)

1

No interrupt pending (when read), clear pending bit (when write)

0

Interrupt is pending (when read)

1

0 No interrupt pending (when read), clear pending bit (when write)
1 Interrupt is pending (when read)

0 No interrupt pending (when read), clear pending bit (when write)
1 Interrupt is pending (when read)

0 No interrupt pending (when read), clear pending bit (when write)
1 Interrupt is pending (when read)

0 No interrupt pending (when read), clear pending bit (when write)
1 Interrupt is pending (when read)

4-14

S3F84VB_UM_REV1.00 CONTROL REGISTER

IPH — Instruction Pointer (High Byte) DAH Set 1

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value
Read/Write
Addressing Mode

.7–.0 Instruction Pointer Address (High Byte)

x x x x x x x x

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction
pointer address (IP15–IP8). The lower byte of the IP address is located in the IPL
register (DBH).

IPL — Instruction Pointer (Low Byte) DBH Set 1

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value
Read/Write
Addressing Mode

.7–.0 Instruction Pointer Address (Low Byte)

The low-byte instruction pointer value is the lower eight bits of the 16-bit instruction

x x x x x x x x

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

pointer address (IP7–IP0). The upper byte of the IP address is located in the IPH
register (DAH).

4-15

CONTROL REGISTERS S3F84VB_UM_REV1.00

IPR — Interrupt Priority Register FFH Set 1, Bank 0

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value
Read/Write
Addressing Mode

.7, .4, and .1 Priority Control Bits for Interrupt Groups A, B, and C

0 0 0 Group priority undefined

0 0 1 B > C > A
0 1 0 A > B > C
0 1 1 B > A > C
1 0 0 C > A > B
1 0 1 C > B > A
1 1 0 A > C > B
1 1 1 Group priority undefined

.6 Interrupt Subgroup C Priority Control Bit

.5 Interrupt Group C Priority Control Bit

.3 Interrupt Subgroup B Priority Control Bit

.2 Interrupt Group B Priority Control Bit

.0 Interrupt Group A Priority Control Bit

x x x x x x x x

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

0 IRQ6 > IRQ7
1 IRQ7 > IRQ6

0 IRQ5 > (IRQ6, IRQ7)
1 (IRQ6, IRQ7) > IRQ5

0 IRQ3 > IRQ4
1 IRQ4 > IRQ3

0 IRQ2 > (IRQ3, IRQ4)
1 (IRQ3, IRQ4) > IRQ2

0 IRQ0 > IRQ1
1 IRQ1 > IRQ0

NOTE: Interrupt group A -IRQ0, IRQ1
Interrupt group B -IRQ2, IRQ3, IRQ4
Interrupt group C -IRQ5, IRQ6, IRQ7

4-16

S3F84VB_UM_REV1.00 CONTROL REGISTER

IRQ — Interrupt Request Register DCH Set 1

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value
Read/Write
Addressing Mode

.7 Level 7 (IRQ7) Request Pending Bit; External Interrupts P4.0–4.7

.6 Level 6 (IRQ6) Request Pending Bit; External Interrupts P2.0–2.7

.5 Level 5 (IRQ5) Request Pending Bit; UART0/1 Transmit, UART0/1 Receive

.4 Level 4 (IRQ4) Request Pending Bit; Watch Timer, SIO

.3 Level 3 (IRQ3) Request Pending Bit; Timer D0/D1 Match/Capture or Overflow

.2 Level 2 (IRQ2) Request Pending Bit; Timer C Match/Overflow

.1 Level 1 (IRQ1) Request Pending Bit; Timer B Match

.0 Level 0 (IRQ0) Request Pending Bit; Timer A Match/Capture or Overflow

0 0 0 0 0 0 0 0

R R R R R R R R

Register addressing mode only

0 Not pending
1 Pending

0 Not pending
1 Pending

0 Not pending
1 Pending

0 Not pending
1 Pending

0 Not pending
1 Pending

0 Not pending
1 Pending

0 Not pending
1 Pending

0 Not pending
1 Pending

4-17

CONTROL REGISTERS S3F84VB_UM_REV1.00

LCON — LCD Control Register F0H Set 1, Bank 0

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value
Read/Write
Addressing Mode

.7–.6 LCD Clock Selection Bits

.5–.3 LCD Duty and Bias Selection Bits

.2–.1

.0 LCD Display Control Bits

NOTES:

1. When LCON.2-.1 are selected to ‘01’, P5.0-.5 are automatically selected to VLCn, CA and CB pin. (n=0-3).
When LCON.2-.1 are capacitor bias selected, LCON.0 is select to ‘1’ after 1 millisecond delay.

2. When LCON.2-.1 are selected to ‘10’, P5.0-.3 are automatically selected to VLCn. (n=0-3)

3. When LCON.2-.1 are selected to ‘11’, P5.0-.3 are automatically selected to VLCn. (n=0-3)

4. The clock and duty for LCD controller/driver is automatically initialized by hardware, whenever LCON register data value is
re-write. So, the LCON register don’t re-write frequently.

5. The P5.3/VLC3-P5.0/VLC0 must be used as LCD bias pins if the LCD block is used. So, the LCON.2-.1 must not be set to
'00b' when LCON.0=1

.

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

0 0
0 1
1 0
1 1

fw/2
fw/2
fw/2
fw/2

8
7
6
5

(128 Hz)
(256 Hz)
(512 Hz)
(1024 Hz)

0 0 0 1/8duty, 1/4 bias
0 0 1 1/4duty, 1/3 bias
0 1 0 1/3duty, 1/3 bias
0 1 1 1/3duty, 1/2 bias
1 x x 1/2duty, 1/2 bias

LC0

(note)

– V

, CA and CB pins are bias pin

LC3

LCD Bias Type Selection Bits

0 0
0 1

V

LC0

− V

, CA and CB pins are normal I/O pin

LC3

Capacitor bias; V

1 0 Internal resistor bias (The voltage booster is always stopped and cut off);

V

LC0

− V

are bias pin, CA, and CB pins are normal pin

LC3

1 1 External resistor bias (The voltage booster is always stopped and cut off);

V

LC0

− V

are bias pin, CA, and CB pins are normal pin

LC3

0 All LCD signals are low (The voltage booster is always stopped and cut off)
1

Turn display on (When LCON.2−.1 = “01”, Run and connect voltage booster)

4-18

S3F84VB_UM_REV1.00 CONTROL REGISTER

LMOD — LCD Mode Control Register F1H Set 1, Bank 0

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value
Read/Write
Addressing Mode

.7–.3

.2–.0 VLCD Voltage Selection Bits (Only when the capacitor bias is selected)

– – – – – 0 0 0
– – – – – R/W R/W R/W

Register addressing mode only

Not used for the S3F84VB

Values
0 0 0 3.6V
0 0 1 3.8V
0 1 0 4.0V
0 1 1 4.2V
1 0 0 4.4V
1 0 1 4.6V
1 1 0 4.8V
1 1 1 5.0V

1/4 Bias

4-19

CONTROL REGISTERS S3F84VB_UM_REV1.00

OSCCON — Oscillator Control Register FAH Set 1, Bank 0

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value
Read/Write
Addressing Mode

.7–.4

.3 Main Oscillator Control Bit

.2 Sub Oscillator Control Bit

.1

.0 System Clock Selection Bit

– – – – 0 0 – 0
– – – – R/W R/W – R/W

Register addressing mode only

Not used for the S3F84VB

0 Main oscillator RUN
1 Main oscillator STOP

0 Sub oscillator RUN
1 Sub oscillator STOP

Not used for the S3F84VB

0 Select main oscillator for system clock
1 Select sub oscillator for system clock

4-20

S3F84VB_UM_REV1.00 CONTROL REGISTER

P0CONH — Port 0 Control Register (High Byte) E0H Set 1, Bank 1

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value
Read/Write
Addressing Mode

.7–.6 P0.7/SEG5/COM7 Configuration Bits

.5–.4 P0.6/SEG4/COM6 Configuration Bits

.3–.2 P0.5/SEG3/COM5 Configuration Bits

.1–.0 P0.4/SEG2/COM4 Configuration Bits

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

0 0 Input mode
0 1 Input mode, pull-up
1 0 Alternative function (LCD signal)
1 1 Output mode, push-pull

0 0 Input mode
0 1 Input mode, pull-up
1 0 Alternative function (LCD signal)
1 1 Output mode, push-pull

0 0 Input mode
0 1 Input mode, pull-up
1 0 Alternative function (LCD signal)
1 1 Output mode, push-pull

0 0 Input mode
0 1 Input mode, pull-up
1 0 Alternative function (LCD signal)
1 1 Output mode, push-pull

4-21

CONTROL REGISTERS S3F84VB_UM_REV1.00

P0CONL — Port 0 Control Register (Low Byte) E1H Set 1, Bank 1

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value
Read/Write
Addressing Mode

.7–.6 P0.3/SEG1/COM3 Configuration Bits

.5–.4 P0.2/SEG0/COM2 Configuration Bits

.3–.2 P0.1/COM1 Configuration Bits

.1–.0 P0.0/COM0 Configuration Bits

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

0 0 Input mode
0 1 Input mode, pull-up
1 0 Alternative function (LCD signal)
1 1 Output mode, push-pull

0 0 Input mode
0 1 Input mode, pull-up
1 0 Alternative function (LCD signal)
1 1 Output mode, push-pull

0 0 Input mode
0 1 Input mode, pull-up
1 0 Alternative function (LCD signal)
1 1 Output mode, push-pull

0 0 Input mode
0 1 Input mode, pull-up
1 0 Alternative function (LCD signal)
1 1 Output mode, push-pull

4-22

S3F84VB_UM_REV1.00 CONTROL REGISTER

P1CONH — Port 1 Control Register (High Byte) E2H Set 1, Bank 1

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value
Read/Write
Addressing Mode

.7–.6 P1.7/TACLK/SEG11 Configuration Bits

.5–.4 P1.6/TAOUT/TAPWM/TACAP/SEG10 Configuration Bits

.3–.2 P1.5/TxD1/SEG9 Configuration Bits

.1–.0 P1.4/RxD1/SEG8 Configuration Bits

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

0 0 Input mode (TACLK)
0 1 Not available
1 0 Alternative function (LCD signal)
1 1 Output mode

0 0 Input mode (TACAP)
0 1 Alternative function (TAOUT/TAPWM)
1 0 Alternative function (LCD signal)
1 1 Output mode

0 0 Input mode
0 1 Alternative function (TxD1)
1 0 Alternative function (LCD signal)
1 1 Output mode

0 0 Input mode (RxD1)
0 1 Alternative function (RxD1 out)
1 0 Alternative function (LCD signal)
1 1 Output mode

4-23

CONTROL REGISTERS S3F84VB_UM_REV1.00

P1CONL — Port 1 Control Register (Low Byte) E3H Set 1, Bank 1

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value
Read/Write
Addressing Mode

.7–.6 P1.3/TxD0/SEG7 Configuration Bits

.5–.4 P1.2/RxD0/SEG6 Configuration Bits

.3–.2 P1.1 Configuration Bits

.1–.0 P1.0 Configuration Bits

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

0 0 Input mode
0 1 Alternative function (TxD0 out)
1 0 Alternative function (LCD signal)
1 1 Output mode

0 0 Input mode (RxD0)
0 1 Alternative function (RxD0 out)
1 0 Alternative function (LCD signal)
1 1 Output mode

0 0 Input mode
0 1 Not available
1 0 Not available
1 1 Output mode

0 0 Input mode
0 1 Not available
1 0 Not available
1 1 Output mode

4-24

S3F84VB_UM_REV1.00 CONTROL REGISTER

P1PUR — Port 1 Pull-up Resistor Enable Register E4H Set 1, Bank 1

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value
Read/Write
Addressing Mode

.7 P1.7 Pull-up Resistor Enable Bit

0 Pull-up disable
1 Pull-up enable

.6 P1.6 Pull-up Resistor Enable Bit
0 Pull-up disable
1 Pull-up enable

.5 P1.5 Pull-up Resistor Enable Bit

0 Pull-up disable
1 Pull-up enable

.4 P1.4 Pull-up Resistor Enable Bit

0 Pull-up disable
1 Pull-up enable

.3 P1.3 Pull-up Resistor Enable Bit

0 Pull-up disable
1 Pull-up enable

.2 P1.2 Pull-up Resistor Enable Bit

0 Pull-up disable
1 Pull-up enable

.1 P1.1 Pull-up Resistor Enable Bit

0 Pull-up disable
1 Pull-up enable

.0 P1.0 Pull-up Resistor Enable Bit

0 Pull-up disable
1 Pull-up enable

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

NOTE: A pull-up resistor of port 1 is automatically disabled only when the corresponding pin is selected as push-pull
output or alternative function.

4-25

CONTROL REGISTERS S3F84VB_UM_REV1.00

PNE1 — Port 1 N-channel Open-drain Mode Register E5H Set 1, Bank 1

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value
Read/Write
Addressing Mode

.7 P1.7 Output Mode Selection Bit

0 Output mode, push-pull
1 Output mode, open-drain

.6 P1.6 Output Mode Selection Bit
0 Output mode, push-pull
1 Output mode, open-drain

.5 P1.5 Output Mode Selection Bit

0 Output mode, push-pull
1 Output mode, open-drain

.4 P1.4 Output Mode Selection Bit

0 Output mode, push-pull
1 Output mode, open-drain

.3 P1.3 Output Mode Selection Bit

0 Output mode, push-pull
1 Output mode, open-drain

.2 P1.2 Output Mode Selection Bit

0 Output mode, push-pull
1 Output mode, open-drain

.1 P1.1 Output Mode Selection Bit

0 Output mode, push-pull
1 Output mode, open-drain

.0 P1.0 Output Mode Selection Bit

0 Output mode, push-pull
1 Output mode, open-drain

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

4-26